JP3226838B2 - PLL frequency synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Lo
The present invention relates to a PLL frequency synthesizer that performs frequency control by a cked loop method.

[0002]

2. Description of the Related Art As shown in FIG. 5, a conventional basic PLL frequency synthesizer includes a reference frequency oscillator 10 for oscillating and outputting a reference frequency, a first frequency divider 20 for dividing the reference frequency, and a DC A voltage controlled oscillator (VCO circuit) 70 for converting an input voltage into an oscillation frequency, a second frequency divider 30 set by channel data, an output frequency of the first frequency divider 20 and a second frequency divider 30 A phase comparator 40 for detecting a phase difference of the output frequency and outputting a phase difference signal corresponding to the phase difference, a charge pump 50 for using the phase difference signal as a difference signal voltage, and smoothing the difference signal voltage to a DC voltage And a loop filter 60 that feeds back to the voltage controlled oscillator 70.

[0003]

However, the conventional PLL
In the frequency synthesizer, it is necessary to set the modulation sensitivity of the voltage-controlled oscillator to be high in order to make the voltage-controlled oscillator correspond to a wide frequency range.
Since the (Carrier / Noise) ratio deteriorates, if the modulation sensitivity cannot be increased, it is necessary to increase the power supply for the charge pump.

Further, when the frequency is changed, the control voltage of the voltage controlled oscillator changes, but when the frequency changes greatly, the control voltage also changes greatly, and the lock-up time becomes longer.

An object of the present invention is to provide a PLL frequency synthesizer which can cope with a wide frequency range even when the modulation sensitivity is lowered, can shorten a lock-up time, and has a small temperature error.

[0006]

In a PLL frequency synthesizer according to the present invention, a voltage variable supply section for changing a voltage by an output of a loop filter, a storage section, a temperature detection section for detecting an apparatus temperature of the synthesizer, and a control section. And first and second two control terminals are provided in parallel on the input side of the voltage-controlled oscillator so that the frequency output from the voltage-controlled oscillator is changed by two DC input voltages. . A voltage output from the loop filter is input to the first control terminal, and a voltage output from the voltage variable supply unit is applied to the second control terminal. The voltage applied to the second control terminal is varied so that the voltage input to the first control terminal becomes constant.
The control unit detects the voltage of the second control terminal when the PLL frequency is stable, stores the voltage in the storage unit, and immediately before the frequency lock operation is performed again, the voltage variable supply unit changes the voltage stored in the storage unit to the second voltage. The storage unit and the variable voltage supply unit are controlled so as to be applied to the control terminal. The voltage corresponding to the temperature detected by the temperature detecting unit is stored in the storage unit, and the variable voltage supply unit applies the stored voltage to the second control terminal according to the control of the control unit.

When a voltage corresponding to the temperature detected by the temperature detecting section does not exist in the storage section, two voltages corresponding to two high and low temperatures close to the detected temperature are read from the storage section, and the two voltages are read from the two voltages. A voltage corresponding to the detected temperature is calculated, and the calculated voltage is applied to the second control terminal.

Further, the control unit detects the voltage of the second control terminal when the PLL frequency is stable, and stores the detected voltage in the storage unit in association with the temperature detected by the temperature detection unit.

[0009]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. This PL
The L frequency synthesizer comprises a reference frequency oscillator 10, a first
Frequency divider 20, voltage controlled oscillator 70, second frequency divider 3
0, the phase comparator 40, the charge pump 50, and the loop filter 60 have the following configuration added to the basic configuration.

On the input side of the voltage controlled oscillator 70, first and second two control terminals 71 and 72 are provided in parallel.
The O circuit 73 changes the oscillation frequency according to the two DC input voltages input to the two control terminals 71 and 72, respectively. Each of the control terminals 71 and 72 includes a variable capacitance diode, a resistor, and a capacitor.

Further, since the voltage applied to the second control terminal 72 can be varied based on the stored data, the control unit 1
20, a storage unit 130, a D / A converter 90, and an A / D converter 100. In addition, in order to compensate for a temperature change, a temperature detector 110 for detecting the device temperature of the PLL frequency synthesizer is provided.

A comparator 80 and a low-pass filter (LP) serve as a variable voltage supply for the voltage controlled oscillator 70.
F) 140 has been added. The output from the loop filter 60 is directly input to the first control terminal 71, and the output of the comparator 80 is connected to the second control terminal 72.
Input through F140. When the PLL frequency synthesizer is operating, the output of the loop filter 60 is also input to the comparator 80. Comparator 80
Compares the output of the loop filter 60 with the reference voltage Vref, and inputs the output to the second control terminal 72 such that the voltage input from the loop filter 60 to the first control terminal 71 becomes constant (reference voltage Vref). The voltage to be applied.

For example, by switching channels, VC
When the oscillation frequency of the O-circuit 73 is switched from fa to fb and further to fc, the comparator 80 controls the second control terminal so that the voltage input to the first control terminal 71 does not change from the constant voltage Vref. Va applied to 72
To Vb and then to Vc.

Therefore, when the voltage applied to the second control terminal 72 is changed, V has a characteristic as shown in FIG.
With the CO circuit 73, the PLL operation can be performed without changing the modulation sensitivity of the voltage controlled oscillator 70. Further, even if the VCO characteristic change and the frequency are switched due to the temperature change, the first
Since the input voltage of the control terminal 71 does not change, a wide frequency range can be accommodated without increasing the modulation sensitivity of the voltage controlled oscillator 70 and without increasing the voltage of the charge pump 50.

The A / D converter 100 detects the output of the LPF 60, converts the analog output to digital, and inputs it to the control unit 120. The D / A converter 90 converts the digital output from the control unit 120 to analog. Convert to the second
To the control terminal 72.

From the voltage controlled oscillator 70, for example, the frequency fa
Is generated, the control unit 120 immediately before the PLL operation
The frequency division number of the frequency dividers 20 and 30 is set to be the frequency fa. Immediately after the start of the PLL operation, the control unit 120 reads voltage data corresponding to the frequency fa from the storage unit 130 in order to apply a voltage corresponding to the frequency fa to the second control terminal 72. The read voltage data is D
Is converted to analog by the A / A converter 90 and applied to the second control terminal 72 (the voltage at this time is Va).
Is input a predetermined constant voltage Vt1. For this reason, the output frequency of the PLL frequency synthesizer can be stabilized to fa at a higher speed than at the start of the operation.

The control unit 120 is provided with the first control terminal 7.
When the input voltage is stable at a predetermined constant voltage Vt1, the voltage applied to the second control terminal 72 is changed to a voltage corresponding to the channel (a voltage for the second control terminal 72). Is stored in the storage unit 130. Therefore, again
When operating in this channel, the voltage at the time of stability can be applied to the second control terminal 72, so that even if there is a variation in the device, an operation with a small error can be performed.

Next, when the frequency of the voltage controlled oscillator 70 is switched from fa to fb by switching the channel, the control unit 120 immediately sets the P
The output operation of the LL frequency synthesizer is temporarily stopped, and the voltage data corresponding to the frequency fb is similarly read from the storage unit 130 and input to the D / A converter 90. Thereby, the voltage applied to the second control terminal 72 changes from Va to Vb, and thereafter, the output operation of the PLL frequency synthesizer is restarted by the control unit 120. FIG. 3 is a timing chart of such an operation.

Further, the control unit 120 takes in the temperature detected by the temperature detection unit 110 immediately before the start of the PLL operation, and reads out from the storage unit 130 voltage data for the second control terminal 72 corresponding to the operation channel and the device temperature. . The read voltage data is converted into an analog signal by the D / A converter 90 and applied to the second control terminal 72.
Immediately after the start of the L operation, a constant voltage independent of the device temperature is input to the first control terminal 71.

Therefore, even if the device temperature changes rapidly, the input voltage of the first control terminal 71 stabilizes to a constant voltage that does not depend on the device temperature immediately after the start of the PLL operation. Even in the case where the operation is performed by switching the frequency, a stable operation that is not affected by the device temperature is guaranteed.

The control unit 120 includes a temperature detection unit 110
The voltage applied to the second control terminal 72 is stored in the storage unit 130 at the same time as the device temperature at the time of the PLL operation detected in the step. By referring to the stored voltage data as described above,
Operation with less error due to temperature is possible even if there is a variation in the device.

Further, immediately before the operation, if the voltage data corresponding to the device temperature detected by the temperature detection unit 110 does not exist in the storage unit 130, the control unit 120 selects the voltage data from the stored voltage data. Voltage data corresponding to two high and low temperatures closest to the temperature is read from the storage unit 130, and one voltage value corresponding to the device temperature is calculated from the two read voltage data by calculation.

For example, if the device temperature detected by the temperature detection unit 110 is 25 ° C. and the data currently stored in the storage unit 130 is as shown in FIG. 4, the voltage data V30 corresponding to 30 ° C. and 20 ° C. The corresponding voltage data V20 is read, and the voltage V25 at the device temperature of 25 ° C. is V25 = V20 + (V
30-V20), and this voltage is applied to the second control terminal 72. Also in this case, an operation with a small error due to the temperature can be performed.

[0025]

According to the present invention, without increasing the modulation sensitivity of the voltage controlled oscillator and without increasing the charge pump voltage,
Can support a wide frequency range. Further, since the modulation sensitivity can be reduced, the C / N ratio does not deteriorate.

Since the voltage applied to the first control voltage of the voltage controlled oscillator immediately before the PLL operation becomes almost the same as that during the PLL operation, lock-up occurs when the PLL is operated again and when the frequency is switched. Time can be reduced.

Since the voltage applied to the second control terminal of the voltage controlled oscillator is varied according to the change in the device temperature to perform the temperature correction, the lock-up time can be shortened even if the device temperature changes.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a voltage-frequency characteristic diagram of the voltage-controlled oscillator in the first embodiment.

FIG. 3 is a timing chart for explaining the above operation.

FIG. 4 is a diagram illustrating a storage mode of a storage unit in FIG.

FIG. 5 is a block diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Reference frequency oscillator 20 1st frequency divider 30 2nd frequency divider 40 Phase comparator 50 Charge pump 60 Loop filter 70 Voltage control oscillator 71 1st control terminal 72 2nd control terminal 73 VCO circuit 80 Comparator 90 D / A converter 100 A / D converter 110 Temperature detection unit 120 Control unit 130 Storage unit

Claims (3)

(57) [Claims] A reference frequency oscillator for oscillating and outputting a reference frequency; a first frequency divider for dividing the reference frequency; a voltage controlled oscillator for converting a DC input voltage to an oscillation frequency; 2 frequency divider, a phase comparator that detects a phase difference between the output frequency of the first frequency divider and the output frequency of the second frequency divider, and outputs a phase difference signal corresponding to the phase difference, and the phase difference In a PLL frequency synthesizer comprising a charge pump for converting a signal into a differential signal voltage, a loop filter for smoothing the differential signal voltage to a DC voltage and feeding back to a voltage controlled oscillator, a voltage which changes a voltage by an output of the loop filter A variable supply unit, a storage unit, a temperature detection unit for detecting a device temperature of the synthesizer, and a control unit; and two frequencies output from the voltage-controlled oscillator. First and second two control terminals are provided in parallel on the input side of the voltage controlled oscillator so as to be changed by a DC input voltage; and the first control terminal outputs from the loop filter. A voltage is input, and a voltage output from the voltage variable supply unit is applied to the second control terminal. The voltage variable supply unit controls the voltage input to the first control terminal to be constant. The control unit detects the voltage of the second control terminal when the PLL frequency is stable, stores the voltage in the storage unit, and immediately before the frequency lock operation is performed again, when the PLL frequency is stable. The voltage variable supply unit applies a voltage stored in a storage unit to a second control terminal,
Controlling the storage unit and the variable voltage supply unit; storing a voltage corresponding to the temperature detected by the temperature detection unit in the storage unit; and controlling the stored voltage by the control unit. Applying to the second control terminal according to the following. 2. The control section reads two voltages corresponding to two high and low temperatures close to the detected temperature from the storage section when the voltage corresponding to the temperature detected by the temperature detection section does not exist in the storage section. The voltage variable supply unit and the storage unit are controlled so as to calculate a voltage corresponding to the detected temperature from the two voltages and apply the calculated voltage to a second control terminal. A PLL frequency synthesizer as described. 3. The control unit detects the voltage of the second control terminal when the PLL frequency is stable, and stores the detected voltage in the storage unit in association with the detected temperature by the temperature detection unit. Item 3. The PLL frequency synthesizer according to Item 1 or 2.