JP3227166B2 - Absolute value circuit - Google Patents
Absolute value circuitInfo
- Publication number
- JP3227166B2 JP3227166B2 JP09124691A JP9124691A JP3227166B2 JP 3227166 B2 JP3227166 B2 JP 3227166B2 JP 09124691 A JP09124691 A JP 09124691A JP 9124691 A JP9124691 A JP 9124691A JP 3227166 B2 JP3227166 B2 JP 3227166B2
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- Prior art keywords
- voltage
- amplifier
- wave
- circuit
- input
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- 230000003321 amplification Effects 0.000 claims description 19
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000003796 beauty Effects 0.000 claims 1
- 230000000630 rising effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Description
【0001】[0001]
【発明の属する技術分野】この発明は、特に広帯域の絶
対値回路に関するものである。BACKGROUND OF THE INVENTION The present invention, in particular also the related to the absolute value circuit of broadband.
【0002】[0002]
【従来例】絶対値回路は全波整流回路の一種であって、
交流入力電圧の一方の半波の極性を他方の半波と同じ極
性に変換するものであり、一般に利用されている絶対値
回路の1つに図5に示すような例がある。2. Description of the Related Art An absolute value circuit is a type of full-wave rectifier circuit.
It converts the polarity of one half-wave of the AC input voltage to the same polarity as the other half-wave, and there is an example shown in FIG. 5 as one of the generally used absolute value circuits.
【0003】同図の回路においては、例えば入力抵抗R
1、増幅器A1、ダイオードD1,及び帰還抵抗R2を
組み合わせて正の半波出力を得る半波整流手段と、上記
入力抵抗R1及び増幅器A1を共有し、ダイオードD
2、帰還抵抗R3を組み合わせて負の半波出力を発する
半波整流手段と、増幅器A2及び抵抗R4,R5,R6
を組み合わせた電圧加算手段を備えており、各抵抗値に
ついては通常、 R2=R3 R4=2・R6 に設定されている。In the circuit shown in FIG.
1, a half-wave rectifier for obtaining a positive half-wave output by combining the amplifier A1, the diode D1, and the feedback resistor R2; and sharing the input resistor R1 and the amplifier A1 with the diode D
2. A half-wave rectifier for generating a negative half-wave output by combining a feedback resistor R3, an amplifier A2 and resistors R4, R5, R6
, And each resistance value is usually set to R2 = R3 R4 = 2 · R6.
【0004】したがって抵抗R1を介して増幅器A1に
加わる信号に対する同増幅器の利得は、R2/R1=R
3/R1である。また、抵抗R4を介して増幅器A2に
加わる信号に対する同増幅器の利得はR5/R4であ
り、抵抗R6を介して加わる信号に対する利得は、R5
/R6=R5/(R4/2)、すなわち2R5/R4で
あるから上記増幅度の2倍となる。Accordingly, the gain of the amplifier A1 with respect to a signal applied to the amplifier A1 via the resistor R1 is R2 / R1 = R
3 / R1. The gain of the amplifier A2 via the resistor R4 is R5 / R4, and the gain of the signal via the resistor R6 is R5 / R4.
Since / R6 = R5 / (R4 / 2), that is, 2R5 / R4, the amplification degree is twice as large.
【0005】ここで、例えば入力端子T1から抵抗R1
を介して増幅器A1へ図6の(A)に示すような最大値
をEとする正弦波の交流電圧e(i)を加えると、その
正の半波に対しては増幅器A1の出力が負となる。この
場合、増幅器A1の−入力端子はイマジナリアースであ
るから、同増幅器の出力側は−入力端子より低電位とな
り、したがってダイオードD1はオフで、そのカソード
側電圧e(a)は図6(B)に示すように接地電位すな
わちゼロとなる。Here, for example, a resistor R1 is connected from an input terminal T1.
When a sine-wave AC voltage e (i) having a maximum value E as shown in FIG. 6A is applied to the amplifier A1 via the line A, the output of the amplifier A1 becomes negative with respect to the positive half-wave. Becomes In this case, since the negative input terminal of the amplifier A1 is imaginary earth, the output side of the amplifier A1 has a lower potential than the negative input terminal, so that the diode D1 is off and the cathode side voltage e (a) is as shown in FIG. ), The ground potential, ie, zero.
【0006】入力電圧e(i)が負の半波の場合には増
幅器A1の出力が正であるからダイオードD1はオンと
なり、例えばR1=R2の場合には増幅器A1が利得1
の増幅器として動作するから、ダイオードD1のカソー
ド側電圧e(a)は同図6(B)に示すように入力電圧
e(i)と同じ大きさで極性が反転した半波整流形の電
圧 e(a)=−e(i) となる。When the input voltage e (i) is a negative half wave, the output of the amplifier A1 is positive and the diode D1 is turned on. For example, when R1 = R2, the amplifier A1 has a gain of 1
6B, the cathode-side voltage e (a) of the diode D1 has the same magnitude as the input voltage e (i) and a half-wave rectified voltage e of which polarity is inverted as shown in FIG. 6B. (A) = − e (i).
【0007】上記半波整流電圧e(a)は例えば抵抗R
6を介して増幅器A2に加えられ、入力電圧e(i)は
抵抗R4を介して同増幅器に加えられる。この場合、電
圧e(a)に対する増幅器A2の増幅度は上記したよう
に2R5/R4で、電圧e(i)に対する増幅度はR5
/R4である。この増幅度にて増幅された電圧をそれぞ
れ図6の(C)と(D)に示す。これらの増幅電圧が上
記増幅器A2で互いに加算されると、出力端子T2から
は図6(E)に示すように例えば負極性で、かつ、各半
波電圧の大きさが等しい全波整流電圧e(o)が得られ
る。The half-wave rectified voltage e (a) is, for example, a resistor R
6, and the input voltage e (i) is applied to the amplifier via a resistor R4. In this case, the amplification of the amplifier A2 with respect to the voltage e (a) is 2R5 / R4 as described above, and the amplification with respect to the voltage e (i) is R5.
/ R4. The voltages amplified at this amplification degree are shown in FIGS. 6C and 6D, respectively. When these amplified voltages are added to each other by the amplifier A2, a full-wave rectified voltage e having, for example, a negative polarity and the same magnitude of each half-wave voltage is output from the output terminal T2 as shown in FIG. (O) is obtained.
【0008】ところで、ダイオード類にはそのアノード
とカソード間に加わる順方向電圧が、例えばシリコンダ
イオードで約0.6Vを超えるとオンとなって電流が流
れ、それ以下の電圧すなわち0〜0.6V間ではオンに
ならないという不感電圧帯がある。上記図5の整流手段
においては、ダイオードD1がオンになると同ダイオー
ドD1と抵抗R2からなる帰還ループが閉成され、増幅
器A1は上記したように利得1の増幅器として動作す
る。When a forward voltage applied between the anode and the cathode of a diode exceeds, for example, about 0.6 V in a silicon diode, the diode turns on and a current flows, and a voltage lower than that, that is, 0 to 0.6 V There is a dead voltage zone in which it does not turn on between the two. In the rectifier of FIG. 5, when the diode D1 is turned on, a feedback loop including the diode D1 and the resistor R2 is closed, and the amplifier A1 operates as an amplifier having a gain of 1 as described above.
【0009】他方、不感電圧帯ではダイオードD1がオ
フのため帰還ループは開放状態となるが、この場合増幅
器A1は本来有する高利得、いわゆる裡の利得で動作す
る。よって例えば入力電圧e(i)の立ち上がりもしく
は立ち下がり近傍における極めて小さい電圧でも大きく
増幅し、不感電圧を超える出力を発してダイオードをオ
ンの状態にする。これによりダイオード類の不感電圧が
実質的に無視でき、上記図6(E)に示すような全波整
流形の出力電圧が得られる。On the other hand, in the dead voltage band, the feedback loop is open because the diode D1 is turned off. In this case, the amplifier A1 operates at the originally high gain, that is, the so-called gain. Therefore, for example, even a very small voltage near the rise or fall of the input voltage e (i) is greatly amplified, and an output exceeding the dead voltage is generated to turn on the diode. Thereby, the dead voltage of the diodes can be substantially ignored, and the output voltage of the full-wave rectification type as shown in FIG.
【0010】[0010]
【発明が解決しようとする課題】絶対値回路は、交流を
直流などに変換する分野に広く利用されているが、扱う
交流信号の周波数が高くなるに伴って絶対値回路の広帯
域化が望まれるようになってきた。しかし、従来の回路
においては、全波整流形の出力電圧e(o)を得る際、
交流電力電圧e(i)の等倍増幅電圧と半波整流電圧e
(a)の2倍増幅電圧を増幅器A2にて形成し、互いに
加算するようにしている。このため周波数の高い領域で
は、例えば上記図6の(F)に示すように出力電圧e
(o)の1サイクル中、一方の半波電圧と他方の半波電
圧間でレベルや時間幅に不一致を生じ、適用周波数の上
限値を拡大することが困難という問題がある。Absolute value circuit [0005] has been widely utilized in the field of converting alternating current and in direct current, bandwidth of the absolute value circuit is desired in accordance with the frequency of the AC signal to be handled is high It has become. However , in a conventional circuit, when obtaining a full-wave rectification type output voltage e (o),
Amplified voltage and half-wave rectified voltage e of AC power voltage e (i)
2-fold amplification voltage of (a) was formed by the amplifier A2, so that added together. For this reason, in the high frequency region, for example, as shown in FIG.
During one cycle of (o), there is a problem that a level or a time width mismatch occurs between one half-wave voltage and the other half-wave voltage, and it is difficult to increase the upper limit of the applicable frequency.
【0011】この発明は上記の事情を考慮してなされた
もので、その目的は、比較的簡単な構成で適用周波数の
上限値をほぼ従来装置の2倍に拡大可能な広帯域の絶対
値回路を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a wide-band absolute value circuit capable of expanding the upper limit of the applied frequency to approximately twice that of the conventional device with a relatively simple configuration. To provide.
【0012】[0012]
【課題を解決するための手段】図1の実施例を参照し
て、上記目的を達成するため、この発明は下記の(1)
ないし(4)の手段を備えている。すなわち、 (1)入力抵抗R1、増幅度1の増幅器A1、半導体整
流素子としてのダイオードD1および帰還抵抗R2を備
え、交流入力電圧e(i)の一方の半波電圧を整流する
第1の半波整流回路1。Means for Solving the Problems Referring to the embodiment of FIG .
In order to achieve the above object, the present invention provides the following (1)
Or (4) means. (1) Input resistor R1, the amplification degree 1 of amplifier A1, a semiconductor integer
With a diode D1 and a feedback resistor R2 as stream element, for rectifying one of the half-wave voltage of the AC input voltage e (i)
First half-wave rectifier circuit 1.
【0013】(2)上記入力抵抗R1と上記増幅器A1
を共有するとともに、ダイオードD2と上記帰還抵抗R
2と等しい値の帰還抵抗R3を備え、上記交流入力電圧
(e(i))の他方の半波電圧を整流する第2の半波整
流回路2。[0013] (2) above fill out force resistance R1 and the amplifier A1
And the diode D2 and the feedback resistor R
Comprising a feedback resistor R3 of 2 and equal, the second half-wave rectifier circuit for rectifying the other half-wave voltage of the AC input voltage (e (i)) 2.
【0014】(3)入力抵抗R7と増幅器A3および上
記入力抵抗R7と等しい値の帰還抵抗R8を有し、例え
ば上記第2の半波整流回路2の出力電圧を受けてその極
性を反転する増幅度1の反転回路3。[0014] (3) has a input resistor R7 and amplifier A3 and the feedback resistor with a value equal with the input resistor R7 R8, for example
For example, an inverting circuit 3 having an amplification degree of 1 which receives the output voltage of the second half-wave rectifier circuit 2 and inverts its polarity.
【0015】(4)等しい値の2つの入力抵抗R4,R
6と増幅器A2および上記入力抵抗R4,R6と等しい
値の帰還抵抗R5を備え、例えば上記入力抵抗R4を介
して上記第1の半波整流回路1から半波整流電圧を受け
るとともに、上記入力抵抗R6を介して上記反転回路3
から極性が反転した他方の半波整流電圧を受け、両半波
整流電圧を加算する増幅度1の加算回路4。[0015] (4) the two input resistors, such as arbitrary values R4, R
6 and includes a feedback resistor R5 equal to the amplifier A2 and the input resistor R4, R6, for example, with receiving the half-wave rectified voltage from the half-wave rectifier circuit 1 of the first through the input resistor R4, the the inverting circuit 3 via an input resistor R6
And an amplification circuit 1 having an amplification degree of 1 for receiving the other half-wave rectified voltage of which the polarity is inverted and adding the two half-wave rectified voltages.
【0016】[0016]
【作用】上記(1)及び(2)の手段により、大きさが
入力電圧と等しく互いに極性が異なった正、負2つの半
波整流電圧が得られる。よって(3)の手段により1つ
の半波整流電圧の極性を反転すると、加算回路4に加わ
る2つの半波整流電圧は同一極性となる。この2つの半
波整流電圧を上記手段(4)により互いに等しい増幅度
で加算すると、その加算出力は、従来回路における動作
周波数の上限値のほぼ2倍近傍まで入力電圧e(i)と
絶対値が等しい全波整流形の電圧となる。According to the means (1) and (2), two positive and negative half-wave rectified voltages having the same magnitude as the input voltage and different polarities can be obtained. Therefore, when the polarity of one half-wave rectified voltage is inverted by means of (3), the two half-wave rectified voltages applied to the adder circuit 4 have the same polarity. When the two half-wave rectified voltages are added by the means (4) with the same amplification degree, the added output becomes the input voltage e (i) and the absolute value up to almost twice the upper limit of the operating frequency in the conventional circuit. Are equal to each other.
【0017】[動作原理]以下、図2を参照しながらこ
の発明による絶対値回路の動作原理を説明する。図2の
(A)において、例えば時間t=0のとき増幅器にある
電圧eを加えると、その出力が立ち上がってから入力電
圧eと同じ大きさに到達するまでには若干の時間がかか
る。この立ち上がりの速さを一般にスルーレートと称
し、カタログ仕様などでは例えば増幅器の増幅度を1に
した場合の入力電圧eと、同増幅器の出力が入力電圧e
に到達するまでに要した時間t1との比e/t1[V/
μs]をスルーレートとしている。[Operation Principle] The operation principle of the absolute value circuit according to the present invention will be described below with reference to FIG. In FIG. 2A, for example, when a voltage e is applied to the amplifier at time t = 0, it takes some time from when the output rises to when it reaches the same magnitude as the input voltage e. This rising speed is generally called a slew rate. In catalog specifications and the like, for example, the input voltage e when the amplification degree of the amplifier is set to 1 and the output of the amplifier are the input voltage e.
E / t1 [V /
μs] is the slew rate.
【0018】出力電圧が立ち下がる場合も同様に定義さ
れ、例えばt=tnにおいて増幅器の入力電圧eをゼロ
にしたとき、その出力電圧が立ち下がってゼロに到達す
るのに要した時間をt2とすると、スルーレートはe/
t2[V/μs]で表す。なお、出力電圧の立ち上がり
と立ち下がりの時間は必ずしも等しくはないが、実用上
はt2=t1として取り扱っても特に不具合は無いの
で、カタログ仕様等には通常1つのスルーレート値が記
載されている。The case where the output voltage falls is similarly defined. For example, when the input voltage e of the amplifier becomes zero at t = tn, the time required for the output voltage to fall and reach zero is defined as t2. Then, the slew rate is e /
It is represented by t2 [V / μs]. Note that the rise time and the fall time of the output voltage are not necessarily equal, but there is no problem in practical use even if t2 = t1. Therefore, one slew rate value is usually described in catalog specifications and the like. .
【0019】よって、時間軸に対する出力電圧の立ち上
がり又は立ち下がりの傾斜角は等しいとみなし、それを
θとすると、 スルーレート=e/T ………(1) =tanθ ………(2) と書くことができる。これより θ=arctan(e/T) ………(3) となる。Therefore, assuming that the inclination angle of the rise or fall of the output voltage with respect to the time axis is equal and that is θ, the slew rate = e / T (1) = tan θ (2) Can write. Thus, θ = arctan (e / T) (3)
【0020】すなわち、スルーレートの値は出力電圧の
立ち上がりもしくは立ち下がりの傾斜角θと対応し、こ
の傾斜角に沿った立ち上がり、立ち下がりの電圧が、入
力電圧に対して当該増幅器の応答し得る最高速の出力電
圧となる。言い換えると、θを超え90°に至る間で立
ち上がる入力電圧もしくは立ち下がる入力電圧について
は、増幅器の出力が傾斜角θを超えることができず追随
し得ないことを表している。That is, the value of the slew rate corresponds to the rising or falling inclination angle θ of the output voltage, and the rising or falling voltage along this inclination angle can respond to the input voltage of the amplifier. This is the fastest output voltage. In other words, for an input voltage that rises between 90 ° and 90 ° or more, the output of the amplifier cannot exceed the tilt angle θ and cannot follow the input voltage.
【0021】ここで、図2の(B)に示すように増幅器
の入力電圧e(i)を例えば、 e(i)=Esinωt ………(4) なる正弦波電圧とする。ただし、Eは最大値、ω=2π
fでfは周波数である。Here, as shown in FIG. 2B, the input voltage e (i) of the amplifier is, for example, a sine wave voltage e (i) = Esinωt (4). Where E is the maximum value, ω = 2π
In f, f is a frequency.
【0022】いま、t=0の点において入力電圧e
(i)に接線OAを引き、この接線と横軸(時間軸)と
のなす角をθ(i)とすると、θ(i)は入力電圧e
(i)の立ち上がり角度を表す。よってθ(i)の値はNow, at the point of t = 0, the input voltage e
Assuming that a tangent OA is drawn in (i) and an angle between the tangent and the horizontal axis (time axis) is θ (i), θ (i) is an input voltage e.
(I) represents the rising angle. Therefore, the value of θ (i) is
【0023】[0023]
【数1】 としておくことができる。上式に式(4)を代入すると θ(i)=arctan(ωE) となる。このθ(i)は上記図2(A)のθを超えない
ようにしなければならないから、 θ(i)≦θ である。等号を採ってθ(i)=θとすると、 θ=arctan(ωE) 増幅器のスルーレートをSRと表記すると、上式と式
(3),(1)より ωE=e/T =SR である。よって 2πfE=SR ………(5) から f=SR/2πE ………(5a) を得る。式(5)又は(5a)によると、スルーレート
SRは増幅器に固有の値で、かつ既知であるから、同増
幅器が線形動作可能な交流信号e(i)の最高周波数f
はその電圧Eの大きさによって決まることになる。も
し、実際に取り扱っている周波数が f>SR/2πE 又は電圧に関して E>SR/2πf である場合には増幅器が追随不可能のとなり、出力電圧
波形にひずみが発生する。(Equation 1) You can keep. Substituting equation (4) into the above equation gives θ (i) = arctan (ωE). Since θ (i) must not exceed θ in FIG. 2A, θ (i) ≦ θ. If an equal sign is used and θ (i) = θ, θ = arctan (ωE) If the slew rate of the amplifier is expressed as SR, ωE = e / T = SR from the above equation and equations (3) and (1). is there. Therefore, f = SR / 2πE (5a) is obtained from 2πfE = SR (5). According to the formula (5) or (5a), the slew rate SR is a value specific to the amplifier and is known, so that the maximum frequency f of the AC signal e (i) in which the amplifier can linearly operate.
Is determined by the magnitude of the voltage E. If the frequency actually handled is f> SR / 2πE or E> SR / 2πf with respect to the voltage, the amplifier cannot follow and the output voltage waveform is distorted.
【0024】ここで、例えば上記電圧Eをn倍したとき
線形動作可能な周波数をf(n)とすると、式(5a)
より f(n)=SR/2πnE となる。上式に式(5)を代入すると f(n)=f/n を得る。すなわち、例えば装置内の各増幅器がほぼ等し
いスルーレートを有していて、それらの増幅器における
入出力信号の電圧レベルがEであるとすると、装置が上
記スルーレート内で線形動作可能な周波数の上限値はf
となる。しかし、いずれかの増幅器がそのn倍の電圧n
Eを入力又は出力とするような場合には、当該増幅器の
スルーレートをn倍大きくすることは困難であるから、
装置としての動作周波数帯域の上限を上記fの1/nに
制限する必要がある。Here, assuming that a frequency at which the voltage E can be linearly operated when the voltage E is multiplied by n is f (n), the equation (5a) is obtained.
Thus, f (n) = SR / 2πnE. By substituting equation (5) into the above equation, f (n) = f / n is obtained. That is, for example, assuming that each amplifier in the device has substantially the same slew rate and the voltage level of the input / output signal in those amplifiers is E, the upper limit of the frequency at which the device can linearly operate within the above slew rate The value is f
Becomes However, one of the amplifiers has n times the voltage n
When E is an input or an output, it is difficult to increase the slew rate of the amplifier by n times.
It is necessary to limit the upper limit of the operating frequency band of the device to 1 / n of f.
【0025】例えばn=2とした場合の一例を図2の
(C)に示す。同図におてい(イ)は最大電圧をEとす
る上記式(4)の信号Esinωtであり、OAはその
立ち上がり時点t=0における接線、θは増幅器のスル
ーレートに対応した傾斜角である。(ロ)は例えば最大
電圧を2Eとする信号2Esinωtであり、破線で示
すように上記θより大きい傾斜角で立ち上がる電圧もし
くは立ち下がる電圧に対しては増幅器が追随できず、そ
の応答出力は接線に沿った波形となってひずみが発生す
る。このような場合には(ハ)、(ニ)に示すように1
サイクルの繰り返し時間を(イ)又は(ロ)の2倍、す
なわち周波数をf/2にする。ちなみに、従来装置にお
いて周波数を1/2にしなかった場合、最終出力電圧が
入力電圧の絶対値と異なった値となる例を図3に示す。
なお、同図3の(A)〜(D)と(E)はそれぞれ前記
図6の(A)〜(D)と(F)に対応する。FIG. 2C shows an example where n = 2. In the figure, (a) is the signal Esinωt of the above equation (4) where the maximum voltage is E, OA is the tangent at the rising time t = 0, and θ is the inclination angle corresponding to the slew rate of the amplifier. . (B) is a signal 2Esinωt having a maximum voltage of 2E, for example, as shown by a broken line, the amplifier cannot follow a voltage rising or falling at an inclination angle larger than the above θ, and its response output is a tangent. Distortion occurs as a waveform along. In such a case, as shown in (c) and (d), 1
The cycle repetition time is set to twice (a) or (b), that is, the frequency is set to f / 2. Incidentally, FIG. 3 shows an example in which the final output voltage becomes a value different from the absolute value of the input voltage when the frequency is not reduced to 1/2 in the conventional device.
3A to 3D and FIG. 3E correspond to FIGS. 6A to 6D and 6F, respectively.
【0026】[0026]
【実施例】再び図1を参照すると、この発明に係る絶対
値回路は上記課題解決手段の項で述べたように、例えば
入力電圧の一方と他方の半波電圧をそれぞれ整流する2
つの半波整流回路1,2と、半波整流回路2の整流電圧
の極性を反転する反転回路3、および同回路にて極性が
反転した半波電圧と上記半波整流回路1が送出する半波
電圧とを加算する加算回路とを備え、かつ、各回路の増
幅器A1,A2,A3は増幅度1で動作するようにその
入力抵抗と帰還抵抗R1〜R8は、すべて等しい抵抗値
に設定されている。Referring again to FIG. 1, the absolute value circuit according to the present invention, as described in the above-mentioned means for solving the problems, for example, rectifies one and the other half-wave voltages of the input voltage, respectively.
Two half-wave rectifier circuits 1 and 2, an inverting circuit 3 for inverting the polarity of the rectified voltage of the half-wave rectifier circuit 2, and a half-wave voltage whose polarity has been inverted by the half-wave rectifier circuit 2 And the input resistors and the feedback resistors R1 to R8 are all set to the same resistance value so that the amplifiers A1, A2, and A3 of each circuit operate at an amplification factor of 1. ing.
【0027】次に、図4を併せて参照しながら各部の動
作を説明する。同図(A)に示すように例えば正弦波電
圧e(i)=Esinωtが入力端子T1(図1)に加
わると、半波整流回路1,2は増幅度1で動作する増幅
器A1とダイオードD1,D2によりそれぞれ図4の
(B)及び(C)に示すような半波整流電圧e(a)と
e(b)を形成して送出する。Next, the operation of each section will be described with reference to FIG. When a sine wave voltage e (i) = Esinωt is applied to the input terminal T1 (FIG. 1), for example, as shown in FIG. 2A, the half-wave rectifier circuits 1 and 2 operate as an amplifier A1 operating at an amplification factor of 1 and a diode D1. , D2 to form and transmit half-wave rectified voltages e (a) and e (b) as shown in FIGS. 4 (B) and 4 (C), respectively.
【0028】そのうち、一方の半波整流電圧e(a)は
例えば加算回路4の抵抗R4を介して増幅度1に設定さ
れた増幅器A2に加えられる。また、他方の半波整流電
圧e(b)は例えば反転回路3の抵抗R7を介して同じ
く増幅度1に設定された増幅器A3に加えられ、図4の
(D)に示すようにその極性が反転されたのち抵抗R6
を経て上記増幅器A2に加えられる。増幅器A2はこれ
ら2つのの半波整流電圧を等倍増幅して加算する。この
実施例においては装置内で取り扱う最大電圧をEとして
いるので、上記動作原理説明の項で示した式(5a)を
満足する周波数fを使用周波数帯域の上限値とした場
合、増幅器A2の加算出力e(o)は図4(E)に示す
ように入力電圧e(i)の大きさに対して絶対値が等し
い全波整流形の電圧となる。One half-wave rectified voltage e (a) is applied to an amplifier A2 set to an amplification degree of 1, for example, via a resistor R4 of an adder circuit 4. Further, the other half-wave rectified voltage e (b) is applied to the amplifier A3 which is also set to the amplification degree 1 via the resistor R7 of the inverting circuit 3, for example, and its polarity is changed as shown in FIG. After inversion, the resistance R6
, And is applied to the amplifier A2. The amplifier A2 amplifies these two half-wave rectified voltages at the same magnification and adds them. In this embodiment, since the maximum voltage handled in the device is E, if the frequency f that satisfies the expression (5a) shown in the above description of the operation principle is set as the upper limit value of the operating frequency band, the addition of the amplifier A2 is performed. The output e (o) is a full-wave rectified voltage having an absolute value equal to the magnitude of the input voltage e (i) as shown in FIG.
【0029】なお、上記は半波整流回路2の出力側と加
算回路4の入力抵抗R6間に反転回路3を設けた場合の
例であるが、半波整流回路1と加算回路4の入力抵抗R
4間に反転回路を設けてもよい。その場合図4(E)に
示す加算出力電圧の極性は正となるが、動作原理は上記
と同一なのでその説明は省略する。The above is an example in which the inverting circuit 3 is provided between the output side of the half-wave rectifier circuit 2 and the input resistor R6 of the adder circuit 4. R
An inversion circuit may be provided between the four. In this case, the polarity of the added output voltage shown in FIG. 4E is positive, but the principle of operation is the same as that described above, and a description thereof will be omitted.
【0030】[0030]
【効果】以上、詳細に説明したように、この発明におい
ては入力電圧e(i)を半波整流する2つの整流回路1
及び2と、極性反転回路3、加算回路4とを備え、上記
各回路を構成する増幅器A1,A2,A3の電圧増幅度
をそれぞれ1に設定するとともに、同増幅器のスルーレ
ートと上記入力電圧e(i)の最大値Eによって定まる
周波数fを動作周波数帯域の上限値としている。As described above in detail, according to the present invention, two rectifier circuits 1 for half-wave rectifying the input voltage e (i).
And 2, a polarity inverting circuit 3, and an adding circuit 4. The voltage amplification of the amplifiers A1, A2, and A3 constituting each of the above circuits is set to 1, and the slew rate of the amplifier and the input voltage e are set. The frequency f determined by the maximum value E of (i) is set as the upper limit of the operating frequency band.
【0031】したがってこの発明によると、例えば信号
処理の過程で最大値が入力電圧の2倍の電圧2Eを必要
とする従来装置に比べて周波数帯域の上限値をほぼ2倍
まで拡大することが可能となり、広帯域の絶対値回路を
実現することができる。Therefore, according to the present invention, it is possible to increase the upper limit of the frequency band to almost twice as much as that of a conventional device requiring a voltage 2E whose maximum value is twice the input voltage in the course of signal processing, for example. Thus, a wide-band absolute value circuit can be realized.
【図1】この発明を適用した実施例の構成を示すブロッ
ク線図。FIG. 1 is a block diagram showing a configuration of an embodiment to which the present invention is applied.
【図2】(A)〜(C) 動作原理説明用波形図。FIGS. 2A to 2C are waveform diagrams for explaining the operation principle.
【図3】動作原理説明用波形図。FIG. 3 is a waveform chart for explaining the operation principle.
【図4】各部の動作説明用波形図。FIG. 4 is a waveform chart for explaining the operation of each unit.
【図5】従来装置の構成を示すブロック線図。FIG. 5 is a block diagram showing a configuration of a conventional device.
【図6】従来装置の動作説明用波形図。FIG. 6 is a waveform chart for explaining the operation of the conventional device.
1 半波整流回路 2 半波整流回路 3 反転回路 4 加算回路 A1,A2,A3 増幅器 D1,D2 ダイオード e(i) 交流入力電圧 e(a),e(b) 半波整流電圧 e(o) 全波整流形出力電圧 R1,R4,R6 入力抵抗 R2,R3 帰還抵抗 REFERENCE SIGNS LIST 1 half-wave rectifier circuit 2 half-wave rectifier circuit 3 inverting circuit 4 adder circuit A1, A2, A3 amplifier D1, D2 diode e (i) AC input voltage e (a), e (b) half-wave rectified voltage e (o) Full-wave rectification output voltage R1, R4, R6 Input resistance R2, R3 Feedback resistance
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H02M 7/21 G01R 1/30 H03D 1/10 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H02M 7/21 G01R 1/30 H03D 1/10
Claims (1)
(A1)、帰還抵抗(R2)および半導体整流素子(D
1)を含み、交流入力電圧(e(i))の一方の半波電
圧を整流する第1の半波整流回路(1)と、上記入力抵
抗(R1)と上記増幅器(A1)を共有するとともに、
上記帰還抵抗(R2)と等しい値の帰還抵抗(R3)お
よび半導体整流素子(D2)を含み、上記交流入力電圧
(e(i))の他方の半波電圧を整流する第2の半波整
流回路(2)とを含んでいる絶対値回路において、 増幅度1に構成した増幅器(A3)を有し、上記第2の
整流回路(2)から送出する半波整流電圧(e(b))
の極性を反転する反転回路(3)と、 該反転回路(3)から送出する極性反転した半波整流電
圧(e(b))と上記第1の整流回路(1)から送出す
る半波整流電圧(e(a))とをそれぞれ等しい値の入
力抵抗(R6,R4)を介して受ける増幅度1の増幅器
(A2)を有し、同増幅器(A2)にて上記2つの入力
を加算することにより、全波整流形の電圧(e(o))
を形成する加算回路(4)を備えていることを特徴とす
る絶対値回路。[Claim 1] input resistor (R1), the amplification degree first amplifier (A1), a feedback resistor (R2) and the semiconductor rectifying element (D
Include 1), shared with the AC input voltage (e (i) the first half-wave rectifier circuit for rectifying one of the half-wave voltage) (1), the input resistor (R1) and the amplifier (A1) is With
A feedback resistor (R3) and a value equal to the feedback resistor (R2)
Includes a good beauty semiconductor rectifier (D2), and a said AC input voltage (e (i)) the second half-wave integer <br/> flow circuit for rectifying the other half-wave voltage (2) In the absolute value circuit, a half-wave rectified voltage (e (b)) having an amplifier (A3) configured to have an amplification factor of 1 and transmitted from the second rectifier circuit (2).
An inverting circuit (3) for inverting the polarity of the half-wave rectified voltage (e (b)) sent from the inverting circuit (3) and the half-wave rectified sent from the first rectifying circuit (1) It has an amplifier (A2) having an amplification degree of 1 which receives the voltage (e (a)) via input resistors (R6, R4) having the same value, and the two inputs are added by the amplifier (A2) . Thus , the voltage of the full-wave rectification type (e (o))
An absolute value circuit comprising: an adder circuit (4) for forming.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP09124691A JP3227166B2 (en) | 1991-03-29 | 1991-03-29 | Absolute value circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP09124691A JP3227166B2 (en) | 1991-03-29 | 1991-03-29 | Absolute value circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05199760A JPH05199760A (en) | 1993-08-06 |
| JP3227166B2 true JP3227166B2 (en) | 2001-11-12 |
Family
ID=14021065
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP09124691A Expired - Fee Related JP3227166B2 (en) | 1991-03-29 | 1991-03-29 | Absolute value circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3227166B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4072232B2 (en) * | 1997-03-13 | 2008-04-09 | 株式会社日立製作所 | Optical receiver circuit |
-
1991
- 1991-03-29 JP JP09124691A patent/JP3227166B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05199760A (en) | 1993-08-06 |
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