JP3227697B2 - Circuit board inspection method and apparatus - Google Patents
Circuit board inspection method and apparatusInfo
- Publication number
- JP3227697B2 JP3227697B2 JP00700898A JP700898A JP3227697B2 JP 3227697 B2 JP3227697 B2 JP 3227697B2 JP 00700898 A JP00700898 A JP 00700898A JP 700898 A JP700898 A JP 700898A JP 3227697 B2 JP3227697 B2 JP 3227697B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- voltage
- inspected
- circuit board
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000007689 inspection Methods 0.000 title claims description 39
- 238000000034 method Methods 0.000 title claims description 12
- 238000001514 detection method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000002950 deficient Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、複数の配線パター
ンからなる回路基板の各配線パターンの導通検査を行う
回路基板の検査方法とそのための検査装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board inspection method and an inspection apparatus for performing a continuity inspection of each wiring pattern of a circuit board composed of a plurality of wiring patterns.
【０００２】[0002]
【従来の技術】複数の配線パターンが形成されているプ
リント配線板、フレキシブル回路基板等の回路基板を構
成する各配線パターンの断線の有無や他の配線パターン
とのショートの有無等を調べる導通検査の方法として
は、従来、各配線パターンを一本ずつピックアップし、
それに電圧を印加することにより導通チェックをするこ
とがなされている。2. Description of the Related Art A continuity test is performed to check whether or not each wiring pattern constituting a circuit board such as a printed wiring board or a flexible circuit board having a plurality of wiring patterns is broken or short-circuited with another wiring pattern. Conventionally, each wiring pattern is picked up one by one,
A continuity check is made by applying a voltage thereto.
【０００３】このための検査装置としては、例えば、図
２に示すように、複数の配線パターンＬが形成されてい
る回路基板１の各配線パターンＬに順次電圧を印加して
いく切換回路１１と、この切換回路１１に所定の電圧を
印加するコントローラ１２と、配線パターンＬの導通チ
ェックを行う判別回路１３からなる検査装置１０が使用
されている。またこの場合、検査する配線パターンＬに
印加する電圧は、５Ｖ程度とされている。As an inspection device for this purpose, for example, as shown in FIG. 2, a switching circuit 11 for sequentially applying a voltage to each wiring pattern L of a circuit board 1 on which a plurality of wiring patterns L are formed is provided. An inspection apparatus 10 including a controller 12 for applying a predetermined voltage to the switching circuit 11 and a determination circuit 13 for checking the continuity of the wiring pattern L is used. In this case, the voltage applied to the wiring pattern L to be inspected is about 5V.
【０００４】[0004]
【発明が解決しようとする課題】ところで、配線パター
ンのピッチが０．３ｍｍ程度（パターン間隔０．１ｍｍ
程度）にファイン化した回路基板においては、配線パタ
ーン間に残存している不要な微細パターンが、回路間を
ショートさせる場合がある。また、かかる微細パターン
の抵抗は数１００ｋΩ〜数ＭΩとなる。The pitch of the wiring pattern is about 0.3 mm (pattern interval is 0.1 mm).
In a circuit board that has been refined to a degree, an unnecessary fine pattern remaining between wiring patterns may cause a short circuit between circuits. In addition, the resistance of such a fine pattern is several hundred kΩ to several MΩ.
【０００５】しかしながら、配線パターンに印加する電
圧を５Ｖ程度とする従来の検査装置では、数ｋΩ程度の
抵抗は検出することができるが、数１００ｋΩ〜数ＭΩ
の高抵抗は検出できないという問題がある。However, with a conventional inspection apparatus in which the voltage applied to the wiring pattern is about 5 V, a resistance of about several kΩ can be detected, but several hundred kΩ to several MΩ.
There is a problem that the high resistance cannot be detected.
【０００６】このような問題に対しては、検査する配線
パターンに印加する電圧を上げることが考えられ、２５
０Ｖ程度の高電圧を印加する検査装置も市販されてい
る。To solve such a problem, it is conceivable to increase the voltage applied to the wiring pattern to be inspected.
Inspection devices that apply a high voltage of about 0 V are also commercially available.
【０００７】しかし、印加電圧をこのように大きくする
と、配線パターンのピッチが０．３ｍｍ程度とファイン
化の進んだ回路基板では、パターン間で放電が生じ、か
えって導通チェックをすることができないという問題が
ある。さらに、印加電圧を大きくした検査装置は高価で
あるという問題もある。However, when the applied voltage is increased as described above, a circuit board with a finer wiring pattern pitch of about 0.3 mm generates a discharge between the patterns, which makes it impossible to check the continuity. There is. Further, there is a problem that an inspection apparatus having an increased applied voltage is expensive.
【０００８】本発明は以上のような従来技術の問題点を
解決しようとするものであり、複数の配線パターンから
なる回路基板の各配線パターンの導通を検査する方法あ
るいは装置において、配線パターンに高電圧を印加しな
くても、配線パターンの断線の有無やショートの有無を
検査できるようにすることを目的としている。An object of the present invention is to solve the above-mentioned problems of the prior art. In a method or an apparatus for inspecting the continuity of each wiring pattern of a circuit board composed of a plurality of wiring patterns, the present invention relates to a method for inspecting the continuity of wiring patterns. It is an object of the present invention to be able to inspect whether a wiring pattern is disconnected or short-circuited without applying a voltage.
【０００９】[0009]
【課題を解決するための手段】本発明は、上記の目的を
達成するため、複数の配線パターンからなる回路基板の
各配線パターンの導通を検査する回路基板の検査方法で
あって、被検査配線パターンの一方の端子と電圧印加手
段との間に直列に抵抗を挿入して該電圧印加手段から被
検査配線パターンに電圧を印加すると共に、少なくとも
該被検査配線パターンに隣接する他の配線パターンをＧ
ＮＤ電位に接地し、被検査配線パターンの他の端子の電
圧を検出することにより被検査配線パターンの導通を検
査することを特徴とする回路基板の検査方法を提供す
る。SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a circuit board inspection method for inspecting the continuity of each wiring pattern of a circuit board comprising a plurality of wiring patterns. A resistor is inserted in series between one terminal of the pattern and the voltage applying means to apply a voltage to the wiring pattern to be inspected from the voltage applying means, and to at least another wiring pattern adjacent to the wiring pattern to be inspected. G
Provided is a circuit board inspection method, wherein the circuit board is inspected for continuity by grounding to an ND potential and detecting a voltage of another terminal of the wiring pattern to be inspected.
【００１０】また、この方法を実施する装置として、複
数の配線パターンからなる回路基板の各配線パターンの
導通検査を行う回路基板の検査装置であって、被検査配
線パターンの一方の端子に電圧を印加する電圧印加手
段、該電圧印加手段と被検査配線パターンとの間に直列
に挿入された抵抗、被検査配線パターンの他の端子の電
圧を検出する電圧検出手段、及び電圧を印加する端子と
電圧を検出する端子とを順次被検査配線パターンとする
他の配線パターンの端子に切り換え、かつ少なくとも該
被検査配線パターンに隣接する他の配線パターンをＧＮ
Ｄ電位に接地する切換回路からなることを特徴とする検
査装置を提供する。Also, as an apparatus for performing this method, there is provided an inspection apparatus for a circuit board for conducting continuity inspection of each wiring pattern of a circuit board comprising a plurality of wiring patterns, wherein a voltage is applied to one terminal of the wiring pattern to be inspected. A voltage applying means for applying, a resistor inserted in series between the voltage applying means and the wiring pattern to be inspected, a voltage detecting means for detecting a voltage of another terminal of the wiring pattern to be inspected, and a terminal for applying the voltage. The terminal for detecting the voltage is sequentially switched to the terminal of another wiring pattern that is the wiring pattern to be inspected, and at least another wiring pattern adjacent to the wiring pattern to be inspected is GN.
There is provided an inspection apparatus comprising a switching circuit grounded to a D potential.
【００１１】本発明によれば、被検査配線パターンとそ
れに電圧を印加する電圧印加手段との間に直列に抵抗を
挿入するので、被検査配線パターンが正常な導通状態で
あれば、その被検査配線パターンの検出電圧としては、
電圧印加手段が印加する電圧が検出される。これに対し
て、配線パターン間が不要な微細パターン等によって隣
接する他の配線パターンとショートしている場合には、
当該他の配線パターンの端子はＧＮＤ電位に接地されて
いることから、被検査配線パターンの検出電圧は、その
被検査配線パターンと電圧印加手段との間に直列に挿入
された抵抗の電圧降下分だけ低くなる。したがって、電
圧印加手段によって被検査配線パターンに高電圧を印加
することなく、被検査配線パターンのショートの有無を
判断することが可能となる。また、被検査配線パターン
が断線している場合には、被検査配線パターンの検出電
圧はＧＮＤ電位となるので、被検査配線パターンの断線
も容易に判断することが可能となる。According to the present invention, a resistor is inserted in series between the wiring pattern to be inspected and the voltage applying means for applying a voltage thereto. As the detection voltage of the wiring pattern,
The voltage applied by the voltage applying means is detected. On the other hand, if the wiring pattern is short-circuited with another adjacent wiring pattern by an unnecessary fine pattern or the like,
Since the terminal of the other wiring pattern is grounded to the GND potential, the detection voltage of the wiring pattern to be inspected is equal to the voltage drop of the resistor inserted in series between the wiring pattern to be inspected and the voltage applying means. Only lower. Therefore, it is possible to determine the presence or absence of a short circuit in the wiring pattern to be inspected without applying a high voltage to the wiring pattern to be inspected by the voltage applying unit. Further, when the wiring pattern to be inspected is disconnected, the detection voltage of the wiring pattern to be inspected becomes the GND potential, so that the disconnection of the wiring pattern to be inspected can be easily determined.
【００１２】[0012]
【実施例】以下、本発明の一実施例を図面に基づいて具
体的に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be specifically described below with reference to the drawings.
【００１３】図１は、本発明の検査装置２０によって、
ベース基板２上に面付けされた回路基板１Ａ及び回路基
板１Ｂの検査を行う場合の回路の説明図である。なお、
同図（ａ）及び（ｂ）は、それぞれこの検査装置２０で
回路基板１Ａの異なる配線パターンＬ1 、Ｌ2 が当該導
通検査対象となっている状態を示している。FIG. 1 shows an inspection apparatus 20 of the present invention.
FIG. 3 is an explanatory diagram of a circuit when performing inspection of a circuit board 1A and a circuit board 1B imposed on a base substrate 2; In addition,
FIGS. 7A and 7B show a state in which different wiring patterns L1 and L2 of the circuit board 1A are subjected to the continuity inspection by the inspection apparatus 20, respectively.
【００１４】この検査装置２０は、導通検査を行う当該
回路基板１Ａの各端子が接続される切換回路２１、電圧
印加手段２２、切換回路２１と電圧印加手段２２との間
に直列に挿入された抵抗Ｒ1、及び電圧検出器２３から
なっている。The inspection apparatus 20 is inserted in series between the switching circuit 21 and the voltage applying means 22 to which each terminal of the circuit board 1A for conducting the continuity inspection is connected, and between the switching circuit 21 and the voltage applying means 22. It comprises a resistor R 1 and a voltage detector 23.
【００１５】切換回路２１は、回路基板１Ａ、１Ｂを構
成する各配線パターンのうち、導通検査を行う当該被検
査配線パターンの一方の端子Ｐに所定の電圧を印加でき
るようにすると共に、その被検査配線パターンの他の端
子Ｑの電圧を検出できるようにし、さらにこの電圧を印
加する端子Ｐと電圧を測定する端子Ｑを他の配線パター
ンの当該端子に順次切り換えるものである。また、この
切換回路２１は、少なくとも、被検査配線パターンに隣
接する他の配線パターン（例えば、被検査配線パターン
がＬ2である場合の配線パターンＬ1 、Ｌ3）をＧＮＤ電
位に接地する。The switching circuit 21 enables a predetermined voltage to be applied to one terminal P of the wiring pattern to be tested for continuity, among the wiring patterns constituting the circuit boards 1A and 1B. The voltage of the other terminal Q of the inspection wiring pattern can be detected, and the terminal P for applying this voltage and the terminal Q for measuring the voltage are sequentially switched to the terminal of the other wiring pattern. The switching circuit 21 grounds at least another wiring pattern adjacent to the wiring pattern to be inspected (for example, wiring patterns L1 and L3 when the wiring pattern to be inspected is L2) to the GND potential.
【００１６】電圧印加手段２２は、抵抗Ｒ1を介して被
検査配線パターンに所定の電圧を印加するものである。
この印加電圧の大きさは、被検査配線パターンの抵抗値
に応じて適宜定めることができるが、５０Ｖ以下とする
ことが好ましく、通常５〜５０Ｖ程度とする。The voltage application means 22 via the resistor R 1 is intended to apply a predetermined voltage to be inspected wiring pattern.
The magnitude of the applied voltage can be appropriately determined according to the resistance value of the wiring pattern to be inspected, but is preferably 50 V or less, and usually about 5 to 50 V.
【００１７】電圧検出器２３は、電圧を印加される被検
査配線パターンの端子Ｐの反対側の端子Ｑに接続され、
その端子Ｑの電位を検出する。この電圧検出器２３では
後述するように、切換回路２１と電圧印加手段２２との
間の抵抗Ｒ1による電圧降下を検出できる程度の検出精
度があればよく、一般的な電圧検出器を使用することが
できる。The voltage detector 23 is connected to a terminal Q opposite to the terminal P of the wiring pattern to be inspected to which a voltage is applied,
The potential of the terminal Q is detected. As described later in this voltage detector 23 may, if the degree of detection accuracy can detect the voltage drop due to the resistance R 1 between the switching circuit 21 and the voltage applying unit 22, using the common voltage detector be able to.
【００１８】切換回路２１と電圧印加手段２２との間の
抵抗Ｒ1は、この検査装置２０に特徴的な構成である。
この抵抗Ｒ1の抵抗値は、電圧印加手段２２による印加
電圧の大きさ、被検査配線パターンの抵抗値等に応じて
適宜設定することができるが、通常、５０ｋΩ〜５００
ｋΩとすることが好ましい。また、この抵抗Ｒ1は、必
要に応じて可変抵抗としてもよい。The resistance R 1 between the switching circuit 21 and the voltage applying means 22 is a characteristic configuration of the inspection device 20.
Resistance of the resistor R 1, the magnitude of the voltage applied by the voltage applying unit 22, it can be appropriately set in accordance with the resistance value or the like of the inspection wiring pattern, usually, 50Keiomega～500
It is preferably set to kΩ. Further, the resistor R 1 may be a variable resistor as required.
【００１９】この検査装置２０を用いて回路基板１Ａの
配線パターンの導通を検査する方法としては、まず、こ
の検査装置２０の切換回路２１の各端子と回路基板１Ａ
の配線パターンの各端子とを接続し、電圧印加手段２２
から、検査する当該配線パターンの一方の端子Ｐに抵抗
Ｒ1を介して所定の電圧を印加し、他方の端子Ｑの電圧
を電圧検出器２３で検出する。As a method of inspecting the continuity of the wiring pattern of the circuit board 1A using the inspection apparatus 20, first, each terminal of the switching circuit 21 of the inspection apparatus 20 is connected to the circuit board 1A.
To each terminal of the wiring pattern of
Then, a predetermined voltage is applied to one terminal P of the wiring pattern to be inspected via the resistor R 1 , and the voltage of the other terminal Q is detected by the voltage detector 23.
【００２０】このとき、図１（ａ）に示すように、導通
を検査する配線パターンＬ1が断線しておらず、また、
他の配線パターンとショートもしていない場合には、電
圧検出器２３には、電圧印加手段２２による印加電圧が
そのまま検出される。例えば、電圧印加手段２２の出力
電圧が１２Ｖの場合、電圧検出器２３における検出電圧
も１２Ｖとなる。At this time, as shown in FIG. 1A, the wiring pattern L1 for checking continuity is not disconnected.
If there is no short circuit with another wiring pattern, the voltage detector 23 detects the applied voltage by the voltage applying means 22 as it is. For example, when the output voltage of the voltage applying unit 22 is 12V, the detection voltage of the voltage detector 23 is also 12V.
【００２１】これに対して、図１（ｂ）に示すように、
導通を検査する配線パターンＬ2 が、隣接する他の配線
パターンＬ3 と抵抗Ｒ0の微細パターンでショートして
いる場合には、電圧検出器２３には、切換回路２１と電
圧印加手段２２との間の抵抗Ｒ1の電圧降下分の電圧が
低く検出される。On the other hand, as shown in FIG.
When the wiring pattern L2 to be inspected for continuity is short-circuited with another adjacent wiring pattern L3 by the fine pattern of the resistor R0 , the voltage detector 23 is connected between the switching circuit 21 and the voltage applying means 22. voltage of the voltage drop of the resistor R 1 of is detected low.
【００２２】例えば、配線パターンＬ2 と配線パターン
Ｌ3 とをショートさせる微細パターンの抵抗Ｒ0が１０
ＭΩ、電圧印加手段２２の出力電圧が１２Ｖ、抵抗Ｒ1
が１００ＫΩである場合、電圧検出器２３には、次式For example, the resistance R 0 of the fine pattern for short-circuiting the wiring pattern L 2 and the wiring pattern L 3 is 10
MΩ, the output voltage of the voltage applying means 22 is 12 V, and the resistance R 1
Is 100 KΩ, the voltage detector 23 has the following equation:
【００２３】[0023]
【数１】 (Equation 1)
【００２４】により１１．８８Ｖとなり、前述のショー
トのない配線パターンの場合に対して０．１２Ｖ低く検
出される。したがって、この抵抗Ｒ1の電圧降下分の電
圧変位があることにより、配線パターンＬ2 のショート
を容易に検出することができる。As a result, the voltage becomes 11.88 V, which is 0.12 V lower than that in the case of the above-described wiring pattern having no short circuit. Thus, there is a voltage drop of the voltage displacement of the resistor R 1, a short circuit wiring pattern L2 can be easily detected.
【００２５】このようにこの検査装置２０によると、配
線パターン間に放電を生じさせるような高電圧を印加す
ることなく、簡便な装置で確実に配線パターンのショー
トを検出することができる。また、このような配線パタ
ーンのショートの検出により、この回路基板１Ａを不良
基板と判定することができ、その時点で面順次に配置さ
れている次の回路基板１Ｂの導通検査を同様に行えばよ
い。As described above, according to the inspection apparatus 20, a short circuit of the wiring pattern can be reliably detected by a simple apparatus without applying a high voltage that causes a discharge between the wiring patterns. Further, by detecting such a short-circuit of the wiring pattern, the circuit board 1A can be determined to be a defective board, and the continuity test of the next circuit board 1B which is arranged face-to-face at that time can be similarly performed. Good.
【００２６】この検査装置２０において、被検査配線パ
ターンが断線している場合には、電圧検出器２３の検出
電圧は、電圧印加手段２２による電圧の印加に関わら
ず、ＧＮＤ電位のままとなるから、配線パターンの断線
の有無を検出することができる。またそれによって、回
路基板１Ａの良否を判定することができる。In the inspection apparatus 20, when the wiring pattern to be inspected is disconnected, the voltage detected by the voltage detector 23 remains at the GND potential regardless of the application of the voltage by the voltage applying means 22. In addition, the presence or absence of disconnection of the wiring pattern can be detected. Thereby, the quality of the circuit board 1A can be determined.
【００２７】なお、上述のように配線パターンＬ2 と配
線パターンＬ3 とがショートしている場合において、配
線パターンＬ3 が断線しているときには、電圧検出器２
３で上述のような電圧降下を検出できない場合もある
が、配線パターンＬ3 を被検査配線パターンとしたとき
にその断線が検出されるので、回路基板１Ａの良否の判
定は確実に行うことができる。When the wiring pattern L2 is short-circuited as described above and the wiring pattern L3 is disconnected, the voltage detector 2
3, the above-mentioned voltage drop may not be detected in some cases. However, when the wiring pattern L3 is used as the wiring pattern to be inspected, the disconnection is detected, so that the quality of the circuit board 1A can be reliably determined. .
【００２８】[0028]
【発明の効果】本発明によれば、複数の配線パターンか
らなる回路基板の各配線パターンの導通検査を、配線パ
ターンに高電圧を印加しなくても簡便に安価な装置で行
うことができる。According to the present invention, the continuity test of each wiring pattern of a circuit board composed of a plurality of wiring patterns can be performed simply and inexpensively without applying a high voltage to the wiring patterns.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の回路基板の検査装置の回路の説明図で
ある。FIG. 1 is an explanatory diagram of a circuit of a circuit board inspection device of the present invention.
【図２】従来の回路基板の検査装置の回路の説明図であ
る。FIG. 2 is an explanatory diagram of a circuit of a conventional circuit board inspection apparatus.
１、１Ａ、１Ｂ 回路基板 ２ ベース基板 １０ 検査装置 １１ 切換回路 １２ コントローラ １３ 判別回路 ２０ 検査装置 ２１ 切換回路 ２２ 電圧印加手段 ２３ 電圧検出器 Ｌ、Ｌ1、Ｌ2 配線パターン Ｒ0 配線パターンを短絡させる微細パターンの抵抗 Ｒ1 電圧印加手段と被検査配線パターンとの間に挿
入された抵抗DESCRIPTION OF SYMBOLS 1, 1A, 1B Circuit board 2 Base board 10 Inspection device 11 Switching circuit 12 Controller 13 Discrimination circuit 20 Inspection device 21 Switching circuit 22 Voltage applying means 23 Voltage detector L, L1, L2 Wiring pattern R 0 Fine pattern for short-circuiting wiring pattern a resistor inserted between the resistor R 1 voltage applying means and the object to be inspected wiring pattern of the pattern
Claims (6)
各配線パターンの導通を検査する回路基板の検査方法で
あって、被検査配線パターンの一方の端子と電圧印加手
段との間に直列に抵抗を挿入して該電圧印加手段から被
検査配線パターンに電圧を印加すると共に、少なくとも
該被検査配線パターンに隣接する他の配線パターンをＧ
ＮＤ電位に接地し、被検査配線パターンの他の端子の電
圧を検出することにより被検査配線パターンの導通を検
査することを特徴とする回路基板の検査方法。1. A circuit board inspection method for inspecting continuity of each wiring pattern of a circuit board comprising a plurality of wiring patterns, wherein a resistance is connected in series between one terminal of the wiring pattern to be inspected and a voltage applying means. To apply a voltage from the voltage applying means to the wiring pattern to be inspected, and to connect at least another wiring pattern adjacent to the wiring pattern to be inspected to G
A method of inspecting a circuit board, comprising: grounding to an ND potential; and detecting a continuity of a wiring pattern to be inspected by detecting a voltage of another terminal of the wiring pattern to be inspected.
間に直列に挿入する抵抗を、５０ｋΩ〜５００ｋΩとす
る請求項１記載の検査方法。2. The inspection method according to claim 1, wherein the resistance inserted in series between the voltage applying means and the wiring pattern to be inspected is 50 kΩ to 500 kΩ.
とする請求項１又は２記載の検査方法。3. The inspection method according to claim 1, wherein the output voltage of the voltage applying means is set to 50 V or less.
各配線パターンの導通検査を行う回路基板の検査装置で
あって、被検査配線パターンの一方の端子に電圧を印加
する電圧印加手段、該電圧印加手段と被検査配線パター
ンとの間に直列に挿入された抵抗、被検査配線パターン
の他の端子の電圧を検出する電圧検出手段、及び電圧を
印加する端子と電圧を検出する端子とを順次被検査配線
パターンとする他の配線パターンの端子に切り換え、か
つ少なくとも該被検査配線パターンに隣接する他の配線
パターンをＧＮＤ電位に接地する切換回路からなること
を特徴とする検査装置。4. A circuit board inspection apparatus for performing a continuity inspection of each wiring pattern of a circuit board including a plurality of wiring patterns, comprising: voltage application means for applying a voltage to one terminal of a wiring pattern to be inspected; A resistor inserted in series between the applying means and the wiring pattern to be inspected, a voltage detecting means for detecting the voltage of another terminal of the wiring pattern to be inspected, and a terminal for applying the voltage and a terminal for detecting the voltage are sequentially arranged. An inspection apparatus comprising: a switching circuit that switches to a terminal of another wiring pattern to be a wiring pattern to be inspected and grounds at least another wiring pattern adjacent to the wiring pattern to be inspected to a GND potential.
間に直列に挿入された抵抗が、５０ｋΩ〜５００ｋΩで
ある請求項４記載の検査装置。5. The inspection apparatus according to claim 4, wherein the resistance inserted in series between the voltage application means and the wiring pattern to be inspected is 50 kΩ to 500 kΩ.
である請求項４又は５記載の検査装置。6. The inspection apparatus according to claim 4, wherein an output voltage of the voltage applying means is 50 V or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP00700898A JP3227697B2 (en) | 1998-01-16 | 1998-01-16 | Circuit board inspection method and apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP00700898A JP3227697B2 (en) | 1998-01-16 | 1998-01-16 | Circuit board inspection method and apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11202016A JPH11202016A (en) | 1999-07-30 |
| JP3227697B2 true JP3227697B2 (en) | 2001-11-12 |
Family
ID=11654041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP00700898A Expired - Fee Related JP3227697B2 (en) | 1998-01-16 | 1998-01-16 | Circuit board inspection method and apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3227697B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101408583B (en) | 2008-11-25 | 2010-12-08 | 中兴通讯股份有限公司 | Method and device for detecting plug state between printed circuit boards and printed circuit board |
| JP6221358B2 (en) * | 2013-06-04 | 2017-11-01 | 日本電産リード株式会社 | Substrate inspection method and substrate inspection apparatus |
| JP2015001470A (en) * | 2013-06-17 | 2015-01-05 | 日本電産リード株式会社 | Substrate testing device |
| JP2015111082A (en) * | 2013-12-06 | 2015-06-18 | 富士通テレコムネットワークス株式会社 | Wiring tester, wiring test method and reference value measurement device |
-
1998
- 1998-01-16 JP JP00700898A patent/JP3227697B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11202016A (en) | 1999-07-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3228982B2 (en) | In-circuit test equipment | |
| CN1186643C (en) | Method and apparatus for testing signal paths between integrated circuit wafer and wafer tester | |
| US7629796B2 (en) | Contact type single side probe device and apparatus and method for testing open or short circuits of conductive lines using the same | |
| EP0573159A2 (en) | Identification of pin-open faults by capacitive coupling through the integrated circuit package | |
| JP2003050256A5 (en) | ||
| JP3227697B2 (en) | Circuit board inspection method and apparatus | |
| KR20080092523A (en) | Contact type single side probe, device for disconnection and short circuit of conductor and its method | |
| JP2004221574A (en) | Inspection method for mounting / non-mounting of bypass capacitor and through hole disconnection detection method for multilayer board | |
| JPH10142271A (en) | Circuit board pattern capacitance measurement method | |
| JP4982543B2 (en) | Detection method for through-hole breakage in multilayer boards | |
| JP4231682B2 (en) | Bypass capacitor mounting inspection method | |
| JP3524049B2 (en) | Wiring pattern inspection method | |
| JP2000346898A (en) | Inspection apparatus and inspection method for wiring board | |
| JPH0130429B2 (en) | ||
| JPH1183957A (en) | Inspection device and inspection method | |
| EP1914558A2 (en) | Method to test transparent - to - test capacitors | |
| JPH04355378A (en) | Confirmation of contact probe | |
| JPS6345544A (en) | Inspecting device for printed board | |
| JPH03244142A (en) | Method of testing semiconductor device | |
| KR20040080787A (en) | Test apparatus of Print Circuit Board | |
| JP2006337188A (en) | Semiconductor inspection device, and inspection method of circuit board for semiconductor inspection | |
| JPS60111973A (en) | Circuit board connection discriminating apparatus | |
| JPH0829472A (en) | Signal wiring quality inspection method | |
| JPH1126904A (en) | Electronic circuit board, method of discriminating the board type, and method of inspecting the board | |
| JPH07159489A (en) | Circuit board test system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080907 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080907 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090907 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090907 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100907 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100907 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110907 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120907 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130907 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130907 Year of fee payment: 12 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |