JP3228604B2 - Liquid crystal display drive - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a liquid crystal display driving device.

[0002]

2. Description of the Related Art FIG . 7 shows a conceptual diagram of a liquid crystal display (LCD) driving device. In FIG. 7 , 1 is a CPU (Central Processing Unit), and 2 is an LCD controller. The LCD controller 2 controls operations of the common driver 3, the first segment driver 4, and the second segment driver 5 according to a control signal input from the CPU 1.

The LCD controller 2 has a CP
The display data input from U1 is temporarily stored in a VRAM (video
(Random access memory) 7. And further, under the control of the CPU 1, the common signal h _1, h ₂ from the common driver 3, ..., the display data corresponding to h _n-1, h _n common electrode H _i selected by the reading from VRAM7 , To the first segment driver 4 and the second segment driver 5. Thus, the first segment driver 4
The display data sent to the second segment driver 5 is transmitted to the segment signals s ₁ ,
are converted to s ₂ ,..., s _m−1 , s _m and supplied to the segment electrode S _j . Thus, based on the common signal h _i (i = 1 to n) from the common driver 3 and the segment signal s _j (j = 1 to m) from the segment drivers 4 and 5, the LCD
6 to display an image.

FIG . 8 shows an internal circuit of a common driver in the LCD drive device of FIG . FIG. 9 shows waveforms of the basic clock signal a, the frequency-divided signals b to d of the basic clock signal a, the AC synchronization signal FRM, and the selection signals h1 to hn in FIG.

In FIG . 8 , the basic clock signal a is obtained by crystal oscillation or CR transmission. Then, the basic clock signal a is sequentially divided by 1 by the frequency dividers 8, 9, and 10.
The frequency-divided signals b, c, and d are generated by dividing the frequency by 1/2 to obtain an AC synchronization signal FRM.

The selection signal generation circuit 11 generates a NOR gate 15 based on the basic clock signal a and the frequency-divided signals b and c and a signal obtained by inverting the levels of these signals by the NOT gates 12, 13 and 14. , 16,…, 17
, Hn are generated.

The AC synchronizing signal FRM and the selection signal h 1 thus generated are level-shifted by the level shifters 18 and 19 to the liquid crystal voltage system of voltages V 1 to V 6 and sent to the common signal generation circuit 20. Then, in combination with the level of level AC synchronizing signal FRM of selection signals h1, only one voltage among the voltage V1~V6 is selected and output as the common signal h _1. Similarly, the common signal h ₂ to h _n is generated and output based on other selection signal H2～hn.

FIG . 10 shows the waveforms of the common signals h ₁ and h ₂ and the segment signal s _j supplied to the lit pixel (1, j) and the unlit pixel (2, j) on the LCD 6. here,
The AC synchronizing signal FRM is a pixel signal on the LCD 6.
When a direct current is applied to the liquid crystal material constituting (i, j), the liquid crystal material is degraded. Therefore, this is a synchronization signal for periodically reversing the direction of the voltage applied to the liquid crystal material. The waveform of the alternating synchronizing signal FRM is toggled once during a period in which the common electrode groups H ₁ , H ₂ ,..., H _n−1 , H _n in the LCD 6 are selected once. It will select the common electrode group H ₁ to H _n 2 times in one period.

[0009] pixel (i, j) on the LCD6 Do is on or off state on the on state, the pixel (i, j) the voltage of the common signal h _i applied to the common electrode H _i according to There selection state (level "V6" or level "V1": this voltage hereinafter referred to as selection voltage) the segment signal is applied to the segment electrode S _j at the time when it becomes s _j and common signal h _i
Is determined by the potential difference between

[0010] the potential difference in the lighting pixels in FIG. 10 (1, j), point A, B, C, and common signal h ₁ and the segment signal s _j voltage of the common signal h ₁ becomes to the selected voltage D Becomes α (= V6−V1), so that a lighting voltage is applied to the liquid crystal material of the pixel (1, j), and the pixel (1, j) is turned on.
On the other hand, in the unlit pixel (2, j), each time point E,
F, G, the voltage of the common signal h ₂ in H is the selected voltage. However, since the potential difference between the common signal h ₂ and the segment signal s _j is a β (= V5-V1 = V6 -V2 <V6-V1 = α), the lighting voltage to the liquid crystal material of the pixel (2, j) is applied Instead, the pixel (2, j) is turned off.

At this time, the lighting voltage α (= | V6-V1 |) is applied to the liquid crystal material at both the time points A and B, and the level of the AC synchronization signal FRM is ""the point a is a reference to the voltage of the common signal h _1" H + "while the voltage is applied to the liquid crystal element," L "and is based on the above point voltage of the common signal h ₁ in B" − "
Is applied. Therefore, the lighting pixel (1,
The voltage applied to the liquid crystal material in j) is canceled at the time points A and B, and no direct current is applied to the liquid crystal material.

Note that the time points A,
When the states of B, C, and D (selected states) are shifted by one reference clock, the states are at the points E, F, G, and H (selected states) at the light-off pixel (2, j). Thus, it is the common electrode H _i in the selected state is successively shifted toward the common electrode H ₁ to the common electrode H _n.

[0013]

As described above, the above L
In common driver for CD drives, AC synchronous signal FRM is the common signal h ₁ to h _n are sequentially selected voltage for each toggle. Then, the voltage to the liquid crystal material off pixels common signal h _i of the selection voltage is supplied β
Is applied and the electric charge is charged, so that there is a problem that power consumption is large.

Further, when displaying the staggered image on the pixel matrix of the LCD, the pixel (3, j) which is in the selected state at the time following the time point E (one week of the basic clock signal a).
(See FIG. 7 ). Therefore, the segment signal s _j at that time to the voltage V6, the potential difference between the segment signal s _j and common signals h ₃ to alpha. Therefore, when displaying the zigzag image period the selection voltage is V1 of the common signal h _i at the level "H" of the alternating current synchronous signal FRM
In the period (time A, time E,..., Time B in FIG. 10 ), the voltage of the segment signal s _j needs to be alternately repeated between V6 and V4, and is consumed more than when a constant voltage is supplied. There is a problem that electric power becomes large.

SUMMARY OF THE INVENTION An object of the present invention is to provide an LCD driving device capable of reducing the number of times that a pixel is charged with electric charges and reducing power consumption.

[0016]

In order to achieve the above object, the invention according to claim 1 is an LCD driving device for selectively applying a voltage to pixels arranged in a matrix on an LCD to display an image. A register for storing multiple information representing a multiple of a cycle for sequentially selecting each line of the pixel matrix with respect to a reference cycle, and dividing a basic clock signal by a predetermined number of times by 1/2 each time, and Frequency dividing means for outputting a frequency-divided signal of the basic clock signal; and any one of frequency-divided signals output from the frequency dividing means for each frequency division based on the multiple information stored in the register. A signal selecting means for selecting, and a frequency-divided signal selected by the signal selecting means are successively frequency-divided by 所 定 by a predetermined number of times to generate an AC synchronization signal, and a frequency-divided signal is generated for each frequency division. Output And Ryuka synchronizing signal generating means, and a dividing signal for each division from the frequency dividing signal and the alternating current synchronous signal generating means selected by said signal selecting means described above
Combine in the order according to the multiple information stored in the register
Each line of the pixel matrix and the multiple information
And a common signal generating means for generating a common signal for selection in a selection order and a selection interval according to the above.

[0017]

According to the first aspect of the present invention, when a basic clock signal is input to the frequency dividing means, the frequency dividing means sequentially divides the basic clock signal by a predetermined number of ず つ by a predetermined number of times. A frequency-divided signal of the basic clock signal is output every cycle. Then, based on the multiple information stored in the register, one of the frequency-divided signals output from the frequency-dividing means is selected by the signal selecting means, and the AC-synchronized synchronizing signal-generating means is selected. It is supplied to a common signal generating means .

Then, the frequency-divided signal from the signal selection means is sequentially changed to 1 by the AC synchronization signal generation means.
/ 2 is divided by a predetermined number of times and
A streaming synchronization signal is generated. At the same time, each division
A frequency-divided signal is output every time.

Further, by the common signal generating means , the supplied divided signal and the divided signal for each frequency division from the AC synchronizing signal generating means correspond to the multiple information.
In the above order, and
The common signal for selecting the input signal in the selection order and the selection interval according to the multiple information is generated.

Thus, based on the common signal,
Each line in the pixel matrix is stored in the register
Are selected in an order according to the multiple information stored in the. did
Accordingly, charging the pixels constituting the pixel matrix
The operation is thinned out according to the multiple information, and the power consumption is low.
Is reduced.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. The present invention reduces power consumption by reducing the number of times each pixel in an LCD is charged by setting a multiple mode in which a cycle for sequentially selecting each line in a pixel matrix of the LCD is multiplied by a predetermined number with respect to a reference cycle. Is intended to be reduced.

FIG. 1 is an internal circuit diagram of a common driver in the LCD drive device of the present embodiment. In FIG.
The frequency dividers 21, 22, and 23 divide frequency signals e, f, and g by sequentially dividing the clock signal by に, similarly to the frequency dividers 8, 9, and 10 in the conventional common driver shown in FIG. Generate. In this embodiment, two frequency dividers 24,
25, and generates a frequency-divided signal b obtained by dividing the reference clock signal a by あ る い は or a frequency-divided signal c obtained by dividing １. The selection circuit 26 selects one of the generated frequency-divided signals b and c based on the multiple mode information transmitted from the register 27 and transmits the selected signal to the frequency-divider circuit 21 as an input signal d.

The selection signal generation circuit 28 is the same as the selection signal generation circuit 11 in the conventional common driver shown in FIG. 8 , and generates selection signals h1 to hn. However, in this embodiment, the signals l,
As m and n, the selection circuit 29 switches and selects one of the frequency-divided signals d, e, and f based on the multiple mode information from the register 27. In other words, the frequency-divided signals d, e, and f are supplied to the selection signal generator 28 as the signals l, m, and n in accordance with the manner of association selected by the selection circuit 29.

As described above, by changing the manner of associating the frequency-divided signals d, e, f with the signals i, m, n, the order in which the selection signals h1 to hn become active can be changed. The order of selecting each line in the pixel matrix can be changed.

The common signal generation circuit 30 in the conventional common driver shown in FIG.
And generate the common signals h1 to hn. However,
In this embodiment, the cycle of the input signal d input to the frequency dividing circuit 21 is one time of the reference clock signal a when the multiple mode is the normal mode, and becomes equal to the reference clock signal when the multiple mode is the double mode. The clock signal a becomes twice as large as the reference clock signal a in the case of the quadruple mode. Therefore, in the normal mode, the AC synchronization signal FRM input to the common signal generation circuit 30 has the same cycle as the conventional AC synchronization signal FRM (hereinafter, referred to as a basic cycle), and the double synchronization mode FRM. In this case, the period is twice the basic period. In the case of the quadruple mode, the period is four times the basic period.

The register 27 is a 3-bit register for setting the multiple mode information. When the multiple mode is the normal mode, the CPU (not shown) stores the multiple mode information (1,0,0). The multiple mode information (0, 1, 0) is stored in the case of the double mode, and the multiple mode information (0, 0, 1) is stored in the case of the quadruple mode. Then, according to the multiple mode information stored in the register 27, the period of the signal d input to the frequency divider 21, the signals l, m, n input to the selection signal generator 28, and the common signal generator 30 The cycle of the AC synchronizing signal FRM to be input to is set.

That is, in the present embodiment, the frequency dividing means is constituted by the frequency dividing circuits 24 and 25, and the selecting circuit 26
Constitute the signal selecting means, and the frequency dividing circuits 21, 22, 23
Constitutes the AC synchronizing signal generating means, and the selecting circuit 2
9. Selection signal generation circuit 28 and common signal generation circuit 3
0 constitutes the common signal generation means.

FIG. 2 is a timing chart of the generation of each signal when the multiple mode is the double mode. Hereinafter, the operation of the common driver according to the present embodiment will be described with reference to FIGS. 1 and 2 taking an example where the multiple mode is the double mode.

The CPU stores the multiple mode information (0, 1, 0) indicating the double mode in the register 27.
Then, the multiple mode information stored in the register 27
According to each bit of (0, 1, 0), the divided circuit b obtained by dividing the reference clock signal a by 選 択 by the selecting circuit 26 is selected and input to the frequency dividing circuit 21 as an input signal d. Then, frequency-divided signals e, f, and g are obtained by sequentially dividing the input signal d by に よ っ て by the frequency-dividing circuits 21, 22, and 23. At this time, since the signal input to the frequency dividing circuit 21 is a signal obtained by dividing the basic clock signal a by ａ, the frequency dividing signal g output from the frequency dividing circuit 23 as the AC synchronizing signal FRM is used. The period is twice as long as the AC synchronizing signal FRM (hereinafter referred to as the basic AC synchronizing signal FRM) of the basic period obtained when the basic clock signal a is input to the frequency dividing circuit 21 in the normal mode.

Then, according to the multiple mode information (0, 1, 0) from the register 27, the frequency-divided signals d, e, f are changed to the signals l, m, n according to the association selected by the selection circuit 29. It is supplied to the generation circuit 28. Then, the selection signal generating circuit 28, the conventional case and the same way selection signal h1~hn the selection signal generating circuit 11 in FIG. 8 is generated.

However, at this time, since the signal d input to the frequency dividing circuit 21 is a signal obtained by dividing the basic clock signal a by 、, the selection signal h1 generated by the selection signal generating circuit 28 To hn are twice as long as in the normal mode, and the pulse width is also twice as long.

In the selection signal generating circuit 28, each NOR gate 3 outputs selection signals h1, h3, h5,... Supplied to odd lines of the pixel matrix of the LCD.
The divided signal f (= basic AC synchronization signal F)
RM) is input. On the other hand, the divided signal f is input to each of the NOR gates 32,... Which output the selection signals h2, h4,. Therefore, the level of the basic AC synchronizing signal FRM is "H".
, The odd-numbered selection signals h1, h3,... Become active, and only the odd-numbered lines become valid. If the signal is "L", the even-numbered selection signals h2, h4,. Only valid. As a result, when the level of the basic AC synchronization signal FRM is "H", the odd-numbered common signals h1, h3,... Sequentially become the selection voltage, and when the level is "L", the even-numbered common signals h2, h4. ,... Sequentially become selection voltages.

In this case, for example, focusing on the selection signal h1, the level of the basic AC synchronization signal FRM is "H".
Becomes active only in the case of
The pixel (1, j) according to ₁ seem to direct current is applied. However, the actual AC synchronization signal F output from the frequency divider 23 and supplied to the common signal generator 30 is
The period of the RM is the period in the normal mode (that is,
(The basic cycle). Thus, the liquid crystal material of the pixel (1, j) according to the common electrode H _1, the voltage of "+" as a reference voltage of the common signal h ₁ is applied alternately to each toggle AC synchronizing signal FRM However, the liquid crystal material does not deteriorate.

FIG. 3 shows an AC synchronizing signal FRM, selection signals h 1 and h 2,
5 is a timing chart of common signals h ₁ and h ₂ and a segment signal s _j .

The segment signal s _j in this case is shown in FIG.
10 is a waveform when a staggered image is displayed on the pixel matrix as in the case of No. 10 . The voltage of the common signal h ₁ according to the lighting pixel (1, j) becomes a selected state at I and point K, at the time point J and point L is a non-selected state. Further, the voltage of the common signal h ₂ according to the OFF pixel (2, j) becomes a selected state at J and point L, at the time I and point K is in a non-selected state. That is, when the multiple mode is the double mode, the common signal h
_i is selected in a cycle twice as long as the cycle in the normal mode.

[0036] Thus, the above each pixel (i, j) is common signal h _i according to the selected state, the number of times the charge on the pixel (i, j) is charged is the number at the time of the normal mode 1/2 Becomes Therefore, power consumption can be significantly reduced.

At this time, the number of times that the light-emitting pixel (1, j) is charged with electric charge is also / of the number of times in the normal mode. However, as described above, the common signal h ₁ pulse width of the selection signal h1~hn is doubled
Pulse width of ~h _n also has a two-fold. Thus, the charge amount charged to the lighting pixel (1, j) is maintained at the same charge amount as in the normal mode.

Consider a case where a staggered image is displayed on the pixel matrix of the LCD. Now, it is assumed that odd-numbered pixels in the same row are lighting pixels, and even-numbered pixels are lighting pixels. Then, as described above, when the multiple mode is the double mode, the basic AC synchronization signal F
Common signal h ₁ during the period of the odd-numbered RM level of "H", h _3, ... because only becomes sequentially selects voltage V1, the voltage of the segment signal s _j in order to light the odd-numbered pixel A constant voltage V6 during that period is sufficient.

As described above, when displaying the staggered image when the multiple mode is the double mode, the voltage level of the segment signal s _j can be set to a constant voltage during a half cycle of the basic AC synchronization signal FRM. . That is, the segment signal s _j
Changes only the same as in the case of the full lighting display (or the all-off display) in the normal mode as shown in FIG. 4 (see FIG. 3), so that the current consumption is significantly reduced.
(Current consumption increases as the number of times of turning on / off the light increases.) Therefore, the power consumption can be reduced as compared with the case of the staggered image display in the normal mode (the same as the case of the conventional LCD driving device shown in FIG. 10 ).

Next, the case where the multiple mode is the quadruple mode will be described. FIG. 5 is a generation timing chart of each signal when the multiple mode is the quadruple mode. Hereinafter, according to FIG . 1 and FIG.
The case of the double mode will be described.

The CPU stores the multiple mode information (0, 0, 1) indicating the quadruple mode in the register 27. Then, according to the multiple mode information (0, 0, 1), a frequency-divided signal c obtained by dividing the reference clock signal a by ａ is selected by the selection circuit 26 and input to the frequency-divider circuit 21 as an input signal d. The frequency-divided signals d, e, and f are supplied to the selection signal generation circuit 28 as the signals 1, m, and n in accordance with the correspondence selected by the selection circuit 29. Then, the selection signals h1 to hn are generated.

At this time, since the signal d input to the frequency dividing circuit 21 is a signal obtained by dividing the clock signal a by /, the cycle of the selection signals h 1 to hn generated by the selection signal generating circuit 28 Is four times the period (basic period) in the normal mode, and the pulse width is also four times.

Table 1 summarizes the order in which the selection signals h1 to hn become active for each multiple mode.

[Table 1]

According to Table 1, when the multiple mode is the quadruple mode, the selection signals h1 to hn become active every fourth line in synchronization with the input signal d to the frequency divider 21.

Also in the case of the present embodiment, focusing on the selection signal h1, it is active only when the level of the basic AC synchronization signal FRM is "H". However, the cycle of the actual AC synchronization signal FRM output from the frequency divider 23 and supplied to the common signal generator 30 is four times the basic cycle. Thus, for example, the liquid crystal material of the pixel (1, j) according to the common electrode H ₁ is applied alternately voltage of "+" as a reference voltage of the common signal h _1, the liquid crystal material is not deteriorated.

FIG . 6 shows the case where the multiple mode is the quadruple mode, the AC synchronizing signal FRM, the selection signals h1 and h2,
5 is a timing chart of common signals h ₁ and h ₂ and a segment signal s _j .

The voltage of the common signal h ₁ of the lighting pixel (1, j) in the case of level "H" of the alternating sync signal FRM becomes only at the selected time point M, point N, the time O and time In P, it is in a non-selected state. Further, the voltage of the common signal h ₂ according to the OFF pixel (2, j) is only becomes selected point N, at the time M, point O and point P is a non-selected state. That is, when the multiple mode is four times mode, the common signal h _i are become the selected state at four times the period of the cycle in the normal mode.

[0048] Thus, the common signal h _i according to each pixel (i, j) in the selected state, the number of times that charge in the pixel (i, j) is charged is in the normal mode 1 /
It becomes 4. Therefore, power consumption can be significantly reduced.

At this time, the number of times that the lighted pixel (1, j) is charged with electric charges is also / of the number of times in the normal mode. However, the common signals h _{1 to} h _n
Is four times as large, the charge amount charged to the lighting pixel (1, j) is maintained at the same charge amount as in the normal mode.

Consider a case where a staggered image is displayed on the pixel matrix of the LCD. Now, it is assumed that odd-numbered pixels in the same column are lighting pixels, and even-numbered pixels are lighting pixels. Then, as described above, when the multiple mode is the quadruple mode, the common signals h ₁ and h are used while the level of the basic AC synchronization signal FRM is “H”.
₅ there forward voltage of the segment signal s _j since the selection voltage V1 of the (odd) is the period during constant voltage V6 good. Next, during the period common signal h _2, h ₆ forward voltage of the segment signal s _j since the selection voltage V1 during which time a constant voltage (even-numbered) level of the basic AC synchronizing signal FRM is "L" V4 is good. Further, the period of the AC synchronization signal FRM is twice that in the double mode, and the time when the voltage level of the AC synchronization signal FRM becomes “L” and the level of the segment signal s _j is inverted is also twice. Become.

[0051] Thus, when the multiple mode is the 4-times mode can the voltage level of the segment signal s _j to a constant voltage during a half period of the fundamental alternating synchronizing signal FRM, and the voltage of the segment signal s _j Since the time when the level greatly changes can be made longer than in the case of the double mode, the power consumption can be further reduced as compared with the case of the double mode.

Each pixel constituting the pixel matrix of the LCD is equivalent to a capacitor. In this embodiment, the power consumption is reduced by thinning out the charging operation of each capacitor of the LCD to lengthen the time from charging to the next charging. However, this means that the discharge ratio relative to the number of times of charging is increased without any change. If the amount of charge becomes less than the amount of charge sufficient for lighting before the next charge, the display quality will deteriorate.

Therefore, in this embodiment, the CPU sets the multiple mode information in the register 27 so that the thinning amount of the charging operation can be set. Therefore, the CPU can detect, for example, the amount of charge of the liquid crystal material in each pixel of the LCD, and control the thinning amount of the charging operation according to the detection result. By doing so, it is possible to automatically realize high-quality display with low power consumption as much as possible.

As described above, in the present embodiment, the register 27 for storing multiple mode information in the common driver of the LCD driving device, the frequency dividing circuits 24 and 25, and the selecting circuit 2
6 is provided. Then, according to the multiple mode information set in the register 27 by the CPU, the selection circuit 26 selects either the frequency-divided signal b obtained by dividing the basic clock signal a by 1/2 or the frequency-divided signal c obtained by dividing the frequency by 1/4. This is selected and supplied to the frequency dividing circuits 21, 22, and 23 for generating the AC synchronization signal FRM.

Further, the selection circuit 29 is provided to divide the frequency-divided signals d, e, f according to the multiple mode information set in the register 27 in accordance with the correspondence selected by the selection circuit 29. It is supplied to the selection signal generation circuit 28 as n.

Therefore, the selection signal generation circuit 28 outputs selection signals h1 to hn in which the active periods are thinned out, the pulse width is changed, and the active order is changed according to the multiple mode information. You. And
From the common signal generation circuit 30, based on the AC synchronization signal FRM from the frequency division circuit 23 and the selection signals h1 to hn from the selection signal generation circuit 28, the common signal generation circuit 30 provides the selection voltage in accordance with the multiple mode information. number of decimated, and the pulse width is changed, and changes the order in which the selection voltage, is and alternating synchronization signal FRM is outputted a common signal h ₁ to h _n whose level is inverted every toggles once You.

That is, according to this embodiment, the LCD
The power consumption can be reduced by thinning out the charging operation for each pixel (i, j) constituting the pixel according to the multiple mode information.

The number of frequency dividing circuits for generating the input signal d to the frequency dividing circuit 21 and the number of bits of the register 27 are not limited to those in the above-described embodiment. What is necessary is just to set according to the set number of multiples with respect to a basic period. Also, the selection circuits 26/29,
The specific circuit configurations of the selection signal generation circuit 28 and the common signal generation circuit 30 are not limited to the circuit configurations shown in FIG.

[0059]

As is apparent from the above description, in the LCD driving apparatus according to the first aspect of the invention, the frequency dividing means sequentially divides the basic clock signal by １ by a predetermined number of times, and A frequency-divided signal is output, and one of the frequency-divided signals selected from the frequency-divider selected by the signal selector based on the multiple information stored in the register is supplied to the AC synchronization signal generator and the common signal generator . supplied by the alternating sync signal generating means to generate a frequency a predetermined number of times successively by 1/2 divided signal by dividing the divided signal to each division each in from the signal selecting means, the common signal By means of generation
Therefore, the frequency-divided signal from the signal selection means and the AC
Each divided signal from the period signal generation means is
In the same order, and
Since the common signal for selecting the input in the selection order and the selection interval according to the multiple information is generated,
The selection order of each line of the pixel matrix can be set according to the multiple information stored in the register.

Therefore, according to the present invention, the pixel
The charging operation for each pixel constituting the matrix
By thinning out according to the multiple information stored in the
Thus, power consumption can be reduced.

According to the present invention, for example, when the multiple information is "double", the selection order of each line is set every other line, and when the multiple information is "4 times", By setting the selection order of each line every third line, it is possible to reduce the level fluctuation of the segment signal when displaying the staggered image on the pixel matrix. In other words, the level fluctuation is the same as in the case of the all-on display (or the all-off display) in the normal mode, and the current consumption can be reduced significantly. Thus, further lower power consumption can be achieved.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of an internal circuit of a common driver in an LCD drive device of the present invention.

FIG. 2 is a timing chart of each signal in a 2 × mode in FIG. 1;

FIG. 3 is a diagram showing an example of a common signal in a 2 × mode generated by the common driver shown in FIG. 1;

FIG. 4 is a diagram showing an example of a common signal in a normal mode generated by the common driver shown in FIG. 1;

FIG. 5 is a timing chart of each signal in the quadruple mode in FIG. 1;

FIG. 6 is a diagram illustrating an example of a common signal in the quadruple mode generated by the common driver illustrated in FIG. 1;

FIG. 7 is a conceptual diagram of an LCD driving device.

It is a diagram illustrating an example of a conventional internal circuit of the common driver in the LCD driving apparatus shown in FIG. 8 Fig.

Is a timing chart of signals in FIG. 9 8.

10 is a diagram showing an example of the common signal produced by the common driver shown in FIG.

[Explanation of symbols]

21 to 25: frequency divider circuit, 26, 29 ... selection circuit, 27 ... register, 28 ... selection signal generation circuit, 30 ... common signal generation circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G09G 3/36 G02F 1/133 505 G09G 3/20 622

Claims (1)

(57) [Claims] 1. A liquid crystal display driving apparatus for selectively applying a voltage to pixels arranged in a matrix on a liquid crystal display to display an image, wherein a cycle of sequentially selecting each line of the pixel matrix is set with respect to a reference cycle. A register for storing multiple information representing a multiple, a frequency dividing means for sequentially dividing the basic clock signal by 所 定 by a predetermined number of times and outputting a frequency-divided signal of the basic clock signal for each frequency division; A signal selecting unit that selects one of frequency-divided signals output from the frequency dividing unit for each frequency division based on the multiple information stored in the register; and a frequency division selected by the signal selecting unit. Signal 1
An AC synchronizing signal generating means for generating an AC synchronizing signal by dividing the frequency by 1/2 for a predetermined number of times and outputting a frequency-divided signal for each frequency division; and a frequency-divided signal selected by the signal selecting means. on a divided signal for each division from the alternating current synchronous signal generating means and
Combination in the order corresponding to the multiple information stored in the register
In addition, each line of the pixel matrix is
A liquid crystal display driving device comprising a common signal generating means for generating a common signal for selecting in a selection order and a selection interval according to a report .