JP3229719B2 - Drive circuit for liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a liquid crystal display, and more particularly to a compensation circuit for a shift voltage (.DELTA.V) of a thin film transistor (TFT) having a large difference between a drain voltage and a source voltage.

[0002]

2. Description of the Related Art First, a TFT is provided in a display portion of a liquid crystal display device.
Consider the circuit arrangement of an active matrix type liquid crystal display device provided with the above.

FIG. 9 shows a circuit diagram of a general drain driver of a liquid crystal display device.

In FIG. 9, a drain driver 1 comprises a shift register 2 comprising a plurality of inverters and analog switches, a sample hold 3 comprising analog switches and capacitors, and an output buffer 4 comprising one inverter. .

[0005] Each inverter or each analog switch included in the drain driver is the simplest circuit and usually has two field effect transistors (hereinafter referred to as FETs).
The inverter has an input as a gate and an output as a source, and the analog switch has an input as a source and an output as a drain.

The video signal Vp held by the capacitor in the sample hold 3 is input to the output buffer 4 as a display data signal.
As an output signal to the drain line 6.

That is, the output buffer is connected to the drain line 6 of the liquid crystal panel 5 and applies a driving voltage to the liquid crystal 7 held between a pair of transparent electrodes in the liquid crystal panel.

In the liquid crystal panel, a row of drain lines 6
And a row of gate lines 8, a TFT 9 is installed near the intersection, and the TFTs connected to one row of gate lines conduct simultaneously, and output signals of different magnitudes applied to each drain line are applied from the TFT to the liquid crystal. As a result, an arbitrary display electrode of the liquid crystal panel can be selected.

However, the output signal applied from the output buffer to the drain line of the liquid crystal display device has a voltage drop (Δ) due to the parasitic capacitance Cgs between the gate and the source of the TFT.
V), and the voltage waveform applied to the liquid crystal differs between a positive output signal and a negative output signal.

FIG. 10 is a diagram showing various signal waveforms applied to such an active matrix type liquid crystal display device.

A selected gate line of the liquid crystal display device is turned on with a positive polarity represented by Vgh every vertical scanning period.
Is applied, while the operating layer is an n ^- type amorphous Si or polycrystalline Si TFT, an unselected gate line is represented by Vgl to turn off TFTs other than the selected row. A sufficiently low OFF gate signal is applied (FIG. 10a).

A drain signal 12 whose polarity is inverted with respect to the counter electrode potential 11 is applied to the drain of the TFT in the liquid crystal panel every one vertical scanning period so as to precede the gate signal (FIG. 10B).

When a signal from the drive circuit is transmitted from the drain of the TFT to the source, the TF connected to the display electrode
The source signal 13 applied to the source of T has a voltage drop (ΔV) called a shift voltage 14 when the gate signal is OFF.
, Which is offset with respect to the counter electrode potential (FIG. 10).
c).

That is, in the active matrix type liquid crystal display device, at the moment when the TFT is turned off, the source signal is shifted by the shift voltage ΔV, and as a result, an undesired DC voltage is applied to the liquid crystal.

The shift voltage ΔV is determined by the parasitic capacitance Cgs between the gate and the source of the TFT, the liquid crystal capacitance Clc, and the auxiliary capacitance C.
The magnitude is represented by ΔV = Vg × Cgs / (Cgs + Clc + Csc) (T. Yanagisawa, K. Kasah).
ara and M.S. Kajimura, JapanD
display '86, p192 (1986). ).

Here, Vg is the amount of change in the potential of the scanning line (=
Vgh-Vgl).

The above equation is readily derived from FIG. 11 which considers the amount of charge between the source in equilibrium and the other electrode.

In the figures, C is a counter electrode, S is TF
T represents the source, G represents the gate of the TFT, and SC represents the auxiliary capacitance electrode.

When the potential of the source 15 is Vs, the potential of the gate 16 is Vgh, and the potential of the counter electrode 17 is Vc when the gate signal is ON, the potential Vsc of the auxiliary capacitance electrode 18 electrically connected to the counter electrode is Vc, and the first electric quantity Q is Q = Cgs (Vs−Vgh) + Csc (Vs−Vc) +
Clc (Vs-Vc) (FIG. 11a).

Next, when the potential of the source changed from the power supply and changed is Vs 'and the potential of the gate 16 is Vgl, the quantity of electricity Q' when the gate voltage is OFF is Q '= Cgs (Vs'
−Vgl) + Csc (Vs′−Vc) + Clc (Vs ′)
−Vc) (FIG. 11b).

Since Q = Q 'from the meaning, Cgs (V
s−Vs ′) + Csc (Vs−Vs ′) + Clc (Vs
−Vs ′) = Cgs (Vgh−Vgl) + Csc (Vc
−Vc) + Clc (Vc−Vc), and when deformed, ΔV≡Vs−Vs ′ = Cgs (Vgh−Vgl) / (C
gs + Csc + Clc).

It is known that the shift voltage (ΔV) changes according to the magnitude of a video signal.

FIG. 12 shows a characteristic diagram in which the shift voltage ΔV changes depending on the magnitude of the video signal.

FIG. 12 shows that the shift voltage is small when the absolute value | Vp | of the video signal Vp is large, and becomes large when the absolute value | Vp | of the video signal is small.

This is because the dielectric anisotropy Δε = εε−ε‖
When a positive liquid crystal is used, as Vs increases,
As a result of the liquid crystal being aligned in parallel depending on the direction of the electric field, Clc = εS
It is interpreted that the value of / d increases and the shift voltage ΔV decreases.

In order to reduce the shift voltage ΔV which adversely affects the image quality and reliability of the liquid crystal display device as described above,
An auxiliary capacitance electrode is provided so as to overlap the pixel electrode, and an auxiliary capacitance Cst is added (TP Brody, JA).
Asars, G .; D. Dixon, IEEE Tran
s. Electron Devices, ED-2
0, p995-p1001 (1973). ).

In the configuration in which the storage capacitor is provided by overlapping the gate line and the pixel electrode, the denominator of the equation of the shift voltage is increased so that ΔV ≒ Vg × Cgs / Cst.

Further, the liquid crystal capacitance is increased by reducing the thickness of the liquid crystal layer for the size of the pixel electrode and the like.
Cgs was also considered (JP-A-60-1630).
No. 91).

When the liquid crystal layer is thinned to increase the liquid crystal capacitance Clc, the shift voltage is suppressed by ΔV ≒ Vg × Cgs / Clc, which is the thickness of the liquid crystal.

Further, there is provided a driving method in which an appropriate bias voltage is applied to the counter electrode signal so that a DC component is not applied to the liquid crystal on average even when a shift voltage is generated (Japanese Patent Laid-Open No. 61-116392). ).

This method focuses on the fact that the shift voltage, which is the difference between the drain signal and the source signal, is a DC component.
The counter electrode potential is lowered by the same value as the shift voltage so that no direct current is applied to the liquid crystal.

The first and second methods are methods for changing the capacitance C depending on the shape in the liquid crystal panel, and the third method is a method for changing the external potential V.

The present invention is included in a method of changing the external potential V. In general, an output buffer in which the input and the output are maintained in a similar relationship is provided with a bias voltage in the output in a non-similar relationship. It is.

Therefore, what is conventionally known about the output buffer will be briefly described below.

In general, the output buffer has a gate aspect ratio (W / L) of a single-crystal n-channel FET such that the input and output are symmetrical. ) Is set to 2.5 times.

FIG. 13 is a plan view of an output buffer in which the aspect ratio (W / L) of the gates of two p-channel and n-channel FETs is 2.5: 1.

In FIG. 13, W is the gate width, L is the gate length, and the aspect ratio (W / L) _n of the gate of the n-channel FET to which the low voltage GND 19 is connected is _n the high voltage V
It is designed to be 1 / 2.5 of the aspect ratio (W / L) _p of the gate of the p-channel FET to which dd20 is connected.

The display data signal of the positive polarity or the negative polarity is i
n, and an inverter outputs a negative or positive output signal with respect to the counter electrode potential from out.

The display data signal entering the fall 21 is involved in conduction of the p-type semiconductor sandwiched between the n ⁺ -type semiconductors, and the display data signal entering the rise 22 is the n-type semiconductor sandwiched between the p ⁺ -type semiconductors. Are involved in conduction.

(W / L) _p = 2.5 (W / L)
L) If _n , the switch speeds of the rising (Pull-up) and falling (Pull-down) become equal.

In this case, the rise time as the charge time and the fall time as the discharge time are equal,
Since the input / output curve is completely symmetrical and the inverter has the highest speed, it is applied to an output buffer aiming at faithful reproduction of a video pulse.

As is well known, the current I flowing through the channel of the FET is represented by a process gain coefficient K, which is a product of the capacitance C of the gate insulating film and the mobility μ of the inversion layer, and an aspect ratio (W / L) of the gate. Is known to be proportional to the product of That is, I∝ (μC) × (W / L).

Here, K × (W / L) is called a transistor gain constant β.

Expressing using the transistor gain constant β, when the speed of the element is maximized, β _p = β _n (∵ (W /
L) _p = 2.5 (W / L) _n , K _p = K _n /2.5).

As described above, since the output buffer faithfully transmits the display data signal to the drain line, the aspect ratio of the gate of the p-channel FET is the same as the aspect ratio of the gate of the n-channel FET in the CMOS structure made of single crystal Si. Is set to 2.5 times, and β _p = β _n .

Although a CMOS inverter using both a p-channel FET and an n-channel FET has been described above, the present invention is similarly applied to an NMOS inverter using a depletion FET and an enhancement FET.

FIG. 14 is a circuit diagram of an NMOS non-inverting output buffer.

When the enable signal (Enable) is L, the display data signal of the positive polarity indicated by Vi is applied to the gate of the enhancement FET as an ON signal and to the transmission gate as an OFF signal, and the enhancement FET 23 conducts, and the transmission gate is turned on. 2
4 are insulated.

Therefore, the high voltage Vdd is applied to the drain line of the liquid crystal panel from the non-inverting output buffer as a positive drain signal Vo through the enhancement FET.

On the other hand, the output buffer is connected to the outputs of the inverters in parallel so that the aspect ratio (W / L) of the total sum of the gates is about 128 so as not to accept the voltage fluctuation of the load connected to the output. Designed to be.

For this reason, the output buffer connected to the drain line requires an extremely large area, and its FET arrangement is devised.

FIG. 15 is a plan view of the gate wiring of the FET in the output buffer connected to one drain line.

In FIG. 15, the input rises 22
(Pull-up) or falling 21 (Pull-up)
down), and the output is connected to the connection unit 25.
(Connections to pad).

A plurality of outputs are centrally integrated by wiring, and are connected to a drain line of a liquid crystal panel as one electrode output by a bump 26 or the like.

As shown in FIG. 15, the rising edge (P
(ull-up) gate wiring and falling (Pull-up)
Since the (−down) gate wirings are formed in parallel with each other, the input wirings do not intersect with each other if the inverter configuration is adopted.

Conventionally, the capacitance C has been changed according to the shape of the liquid crystal display device, or a bias V has been applied to the video signal Vp and applied to an output buffer having symmetrical input / output characteristics.

[0057]

The first configuration in which an auxiliary capacitance electrode overlapping a pixel electrode is provided has a problem that the light transmittance of the pixel electrode is slightly reduced.

The second configuration, in which the thickness of the liquid crystal layer is reduced in order to increase the liquid crystal capacity, is difficult to make the thin liquid crystal layer uniform over a large area.
ry curve (I = sin ² [π√ (1 + u ² ) / 2] / (1
+ U ² ), u = 2dΔn / λ, I: light transmittance, d: liquid crystal layer thickness, Δn: refractive index anisotropy, λ: wavelength) tended to make light blocking difficult.

In the third configuration in which a bias voltage is applied, when the object to be applied is a video signal, the circuit before the output buffer becomes complicated, and the signal may be deformed due to interference between the circuits.

An object of the present invention is to provide a drive circuit for a liquid crystal display device which does not hinder light control and compensates for the shift voltage ΔV with a simple circuit.

[0061]

According to the present invention, there is provided a video signal circuit for generating a video signal, a shift register or a decoder for generating a shift pulse, a sample and hold for sampling a video signal and generating a display data signal,
In a drive circuit of a liquid crystal display device having an output buffer for amplifying a shift pulse or a display data signal and outputting the amplified signal to a line of a liquid crystal display panel, the input / output characteristics of the output buffer have a gain.

[0062]

When the output impedance is extremely large as in the case of the output buffer, it is not affected by the circuit characteristics of the previous stage of the output buffer.

Therefore, a signal for compensating the shift voltage is applied most effectively to the liquid crystal panel closest to the liquid crystal panel.

In addition, a liquid crystal panel or a contrast (Im) that is thin and difficult to control the interval and has an increased minimum light transmittance Imin.
ax / Imin) may be omitted.

[0065]

FIG. 1 shows an input / output characteristic diagram of an output buffer according to the present invention.

In FIG. 1, the X axis is a display data signal, and the Y axis is
The axis indicates an output signal, and the output buffer outputs a large output signal for a small display data signal.

The dotted line is a conventional symmetrical input / output characteristic line in which the pull-up time as the charging time is equal to the pull-down time as the discharging time.

On the other hand, in the embodiment a of the present invention, as the display data signal becomes smaller, the bias voltage 27 increases in the positive direction away from the symmetrical input / output straight line indicated by the dotted line.

In other words, the output signal Vout changes with a constant gradient with respect to the display data signal Vin, and the gain of the output buffer is a straight line.

On the other hand, b having a negative gain is a straight line whose absolute value increases in the direction of the negative polarity of the bias voltage as the display data signal increases, departing from the symmetrical input / output straight line indicated by the dotted line. Adjustment of the counter electrode potential is required.

In the case where the input signal is a display data signal, if the above-mentioned characteristics are provided in the output buffer, the image sticking which occurs due to a long afterimage peculiar to the liquid crystal display device is reduced.

Further, an arbitrary bias voltage can be applied in accordance with the magnitude of the video signal of the liquid crystal display device.

FIG. 2 shows a characteristic diagram of two FETs forming the output buffer of the present invention.

On the left side of FIG.
P characteristic 2 which is the drain voltage-current characteristic of the channel FET
8, a curve falling to the left indicates an n-characteristic 29 which is a drain voltage-current characteristic of the n-channel FET.

Further, the value of the drain saturation voltage Vsap of the p-channel FET is smaller than the value of the drain threshold voltage Vthn of the n-channel FET.

Now, the gate threshold voltage V of the n-channel FET
gthn is Vthn = Φms−Qss / C0 + 2Ψb +
(2ε0εsqNa) ^1/2 (2Ψb) ^1/2 , p-channel F
The gate threshold voltage Vgthp of ET is Vthp = −Φms
+ Qss / C0-2Ψb- (2ε0εsqNd)
^1/2 (2Ψa) It is expressed by ^1/2 .

Here, Φms: work function difference [V], Qs
s: fixed charge in oxide film [C], C0: gate oxide film capacity per unit area [Fm ⁻² ], Δb = (kT / q) ln
(Na / ni): semiconductor substrate potential [V], ε
0: vacuum dielectric constant [Fm ^-1 ], εs: semiconductor dielectric constant [Fm ^-1 ], q: electron charge [C], Na: acceptor impurity concentration [m ^-3 ], Nd: donor impurity concentration [M ^-3 ].

When a thin film transistor is used, Ψb = Ψ
a = 0.

Since Qss and the activity rate of the impurity change depending on the conditions, Vg is determined by the laser-annealed p-channel FET.
thp = −3 V, and Vgthp = −6 V for the thermally annealed p-channel FET.

An n-channel FE similarly laser-annealed
N-channel FE thermally annealed at Vgthn = 2V at T
At T, Vgtn = 1V.

When the gate voltage is at the threshold value, the drain voltage can be said to be 0 V. Therefore, Vth is controlled by controlling Vgthn.
n can be varied.

On the other hand, when the drain voltage Vd exceeds a certain voltage when the gate voltage Vg is constant, it becomes difficult for the drain current to flow any more.

This voltage becomes the saturation voltage Vsa, and the saturation voltage Vsan of the n-channel FET becomes Vsan = Vg-Φm
s + Qss / C0-2Ψb + (ε0εsqNa / C
^{0 2) {1- [1+ (} 2C0 2 / ε0εsqNa) (Vg
−Φms + Qss / C0−Vb)] ^1/2 }, and the saturation voltage Vsap of the p-channel FET is Vsan = −Vg + Φms
-Qss / C0 + 2Ψb- (ε0εsqNd / C0 2)
^{{1- [1+ (2C0 2 /} ε0εsqNd) (- Vg +
Φms-Qss / C0 + Va)] ^1/2 }.

As an example, lowering the acceptor impurity concentration lowers the saturation voltage Vsap of the p-channel FET (FIG. 2A).

Similarly, the threshold voltage Vthp of the p-channel FET is reduced by decreasing the implantation amount of Si ions and increasing the density of crystal nuclei in the p-channel FET (FIG. 2).
b).

Up to this point, the method of changing the inflection point of the input / output characteristics has been described. Next, the method of changing the slope of the curve of the input / output characteristics will be described.

The drain voltage-current characteristics of the n-channel FET are as follows: Id = (WμnC0 / L) with reference to drain current Id, drain voltage Vd, and source voltage Vs = 0.
{[Vg-Φms + Qss / C0-2} b] Vd-Vd
² / 2− (2γ / 3) [(Vd + 2Ψb−Vb) ^3/2 −
(2 {b−Vb) ^3/2 ]}.

Where γ = (2ε0εsqNa) ^1/2 /
C0, W: gate width [m], μn: electron drift mobility [m ² V ⁻¹ s ⁻¹ ], L: gate length [m].

When the drain voltage Vd is small and the semiconductor substrate potential Vb = 0 (corresponding to the case of a TFT), it is expressed by the following approximate expression.

Id = (WμnC0 / L) [(Vg−Vg
^{thn) Vd- (Vd 2/2} )] Since except that the μp any p-channel FET is in the preceding paragraph are the same equation, than normal gate aspect ratio W / L to gentle inclination as shown in FIG. 2 You can make it smaller.

Conventionally, a CMOS single-crystal output buffer has a gate aspect ratio (W) of a p-channel FET in order to make the rising and falling switching speeds equal.
/ L) _p has been set to 2.5 times (W / L) _n of the n-channel FET. In the present invention, the gate aspect ratio (W / L) _p of the p-channel FET is changed to (W / L) of the n-channel FET. _It is set to twice _n (FIG. 2c).

On the right side of FIG. 2, the downward-sloping curve is the input / output characteristic 30 of the output signal with respect to the input signal.

The output buffer designed as described above has p
When the saturation voltage Vsap of the channel FET is reduced,
An output signal characteristic with a larger positive bias signal for a smaller input signal is obtained (FIG. 2d).

Also, the threshold voltage Vth of the p-channel FET
When p is reduced, the output buffer of the present invention has an output signal characteristic with an output signal with a larger negative bias signal for a large input signal (FIG. 2e).

Further, unlike the previous two embodiments, when the gate aspect ratio (W / L) is set to β _p <β _n , the switch point Vinv of the inverter becomes smaller than 0.5 Vdd.

Therefore, a point serving as an inflection point is set on the positive / negative boundary of the output signal, and the positive gain is large and the negative gain is small (FIG. 2F).

The gate aspect ratio (W /
FIG. 3 shows a mask diagram of a CMOS output buffer in which L) _p is twice the gate aspect ratio (W / L) _n of the n-channel FET.

In FIG. 3, the polysilicon is composed of an input portion for inputting an input signal, a short gate of an n-channel FET connected to a falling edge 21 on the left half, and a p-channel FET connected to a rising edge 22 on the right half. Forming a long gate.

[0099] n-channel FET is composed of the source of the n ⁺ -type diffusion region connected to the ground by metal wiring made of Al, a p-type semiconductor region, and the drain of the n ⁺ -type diffusion region.

The drain of the n-channel FET and the source of the p-channel FET are both connected to the electrodes of the liquid crystal display panel by an output portion made of metal wiring made of Al.

The p-channel FET has a source of ap ⁺ type diffusion region connected to a power supply voltage by a metal wiring made of Al,
The well includes an n-type semiconductor region of a well and a drain of a p ⁺ -type diffusion region.

The gate of the p-channel FET may be bent on the n-type semiconductor region to increase the gate width.

In the case of single crystal Si, (W / L) _p = 2 (W / L)
L) If _n , β _p / β _n = 0.8.

According to the output buffer structure of the present invention, the p-channel FET requires an area for element formation as compared with the n-channel FET, but has a smaller area as compared with a normal output buffer.

As described above, according to the present invention, the switch threshold voltage Vinv ≠ Vdd / 2 of the inverter is asymmetric,
As a result, a shift voltage ΔV based on the capacitance component of the TFT is compensated by applying a bias that fluctuates from the input to the output.

FIG. 4 shows how the shift voltage of the source signal of the TFT is offset by the output signal output from the output buffer of the present invention to the drain line of the liquid crystal panel.

First, the output buffer of the present invention outputs a large polygonal output signal 32 as the video signal 31 indicated by the dotted line is closer to 0 V (FIG. 4A).

Next, when the anisotropy Δε of the dielectric constant of the liquid crystal is positive, the voltage drop value of the polygonal shift voltage 14 increases as it approaches 0 V (FIG. 4B).

Therefore, when the output signal of the output buffer and the shift voltage ΔV are set symmetrically with respect to the video signal in the vertical axis direction, the source signal 13 of the TFT completely matches the video signal and becomes linear (see FIG. 4c).

As a result, this configuration enables faithful reproduction of a video signal and AC driving of the liquid crystal display device without changing the potential of the counter electrode.

For example, in the present invention,
It is not necessary to shift the potential of the common electrode after the video signal is set to have different positive and negative amplification factors as described in Japanese Patent Publication No. 29-29.

FIG. 5 shows a curved input / output diagram of the output buffer which performs the operation of FIG. 2f with the anisotropy of the dielectric constant of the liquid crystal being positive, the switch point Vinv being 0 V of the input signal.

In FIG. 5, the dotted line indicates the characteristic of the video signal 31, the broken line indicates the characteristic of the output signal 32 of the output buffer, and the dashed line indicates the source signal 1 which is substantially the voltage applied to the liquid crystal.
This is the characteristic of No. 3.

The bias voltage, which increases as the magnitude of the input signal approaches 0 V, compensates for the shift voltage ΔV, which increases as the magnitude of the input signal approaches 0 V, so that the characteristic line of the video signal and the characteristic line of the source signal are changed. It is clear that the original video signal is reproduced faithfully.

Here, CRT is I = KEγ (gamma γ
= 2.5 to 3) (Nippon Broadcasting Corporation, NHK Color Television Textbook, pp. 235-236, 1983).

It is also known that the liquid crystal display device has an S-shaped curve in light transmittance with respect to the voltage applied to the liquid crystal. However, the output signal of the output buffer of the present invention is used as a display data signal. On the other hand, since it is easy to make a curve, inverse gamma correction of the CRT video signal and saturation correction of the liquid crystal display device can be performed at the same time.

For example, when the display data signal is set to one polarity (also referred to as one polarity) and the output of the output buffer is suppressed by a large signal, the contrast of the liquid crystal display device can be improved.

FIG. 6 is an explanatory diagram of the effect that occurs when the output of the output buffer is suppressed on the large signal side in the liquid crystal display device.

When the pixel voltage is 0, N is less likely to transmit light.
In the case of the B-type liquid crystal panel, the light transmittance for a video signal draws an S-shaped curve.

As shown in the figure, the light transmittance of the entire screen of the liquid crystal panel is high, as in the case of white saturation, and the state in which the screen is difficult to see is considered to be concentrated between the white circle and the white square in FIG. If β _p = β _n / 2 and the output of the driver is suppressed on the high output side, the light transmittance moves from a black circle to a black square.

Then, as is clear from FIG. 6, the local contrast of the liquid crystal display device can be improved.

FIG. 7 shows waveform diagrams of various signals applied from the output buffer of the present invention to the liquid crystal panel.

As shown in FIG. 7, the average value of the output signal 32 applied to the drain line of the liquid crystal panel is kept higher than the potential 11 of the common electrode.

The source signal 13 does not drop so much for a large output signal, but drops greatly for a small output signal.

On the other hand, the output portion of the output buffer used in the present invention has a falling edge connected to Vdd on the inner circumference,
The rise connected to the ND may be arranged on the outer periphery.

FIG. 8 is a plan view of the output section of the output buffer according to the present invention.

In FIG. 8, a long p-channel FET 33 of a p-channel FET is arranged outside the rising 22 and a short n-channel 34 of an n-channel FET inside the falling 21.

With this arrangement, the center point of the bump is set to O
N-channel FE connected at point O and the falling edge
The distance Rd to the point T is the distance R between the point O and the p-channel FET connected to the rising edge outside the n-channel FET.
smaller than u.

Then, since the channel of each FET is formed around the fall or rise, the distance between the FETs of the same conductivity type can be made proportional to the distance from the center point of the bump. Rd = (W /
L) _p / (W / L) _n (where (W / L) _p > (W /
The effect that the output buffer designed in L) _n ) can be filled in the plane at high density is obtained.

When the number of inverters in the output buffer is further increased, the n-channel FET and the p-channel FET are radially connected to the center point O of the bump.

The structure of the present invention is a single crystal CMOS inverter.
Data output buffer _p/ Β_n= 1 to 0.5
≤β_p/ Β_nIt can be obtained by setting ≤ about 0.9,
From the relationship β = μ · C · (W / L), polycrystalline semiconductors and
Inversion layer mobility μ (for example,
Μ for crystalline silicon_n= 70cm^Two/ V / s, μ_p=
40cm^Two/ V / s), even when the insulation layer capacitance C is small.
Applicable.

[0132]

Since the input / output characteristics of the output buffer closest to the signal lines of the liquid crystal display panel are adjusted so that the shift voltage due to the capacitance is reduced, various optimum bias voltages are supplied to the liquid crystal display panel. Thus, flicker and afterimages of the liquid crystal display device can be reduced, and reliability and display quality can be improved.

[Brief description of the drawings]

FIG. 1 is an input / output voltage characteristic diagram of an output buffer according to the present invention.

FIG. 2 is a voltage characteristic diagram of an FET in an output buffer according to the present invention.

FIG. 3 is a mask diagram of an output buffer according to the present invention.

FIG. 4 is an explanatory diagram of cancellation of a shift voltage of an output buffer according to the present invention.

FIG. 5 is a curve of input / output voltage characteristics of the output buffer of the present invention.

FIG. 6 is an optical characteristic diagram of a liquid crystal panel using the output buffer of the present invention.

FIG. 7 is a signal waveform diagram of a liquid crystal panel using the output buffer of the present invention.

FIG. 8 is a layout diagram of an output unit of the output buffer according to the present invention.

FIG. 9 is a circuit diagram of a drain driver.

FIG. 10 is a signal waveform diagram of a liquid crystal panel.

FIG. 11 is an equivalent circuit diagram of a liquid crystal panel.

FIG. 12 is a characteristic diagram of a shift voltage.

FIG. 13 is a mask diagram of an output buffer.

FIG. 14 is a circuit diagram of a non-inverting output buffer.

FIG. 15 is a layout diagram of an output unit of an output buffer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Drain driver 2 Shift register 3 Sample hold 4 Output buffer 5 Liquid crystal panel 6 Drain line 7 Liquid crystal 8 Gate line 9 TFT 10 Gate signal 11 Counter electrode potential 12 Drain signal 13 Source signal 14 Shift voltage 15 Source 16 Gate 17 Counter electrode 18 Auxiliary Capacitance electrode 19 GND 20 Vdd 21 Falling 22 Rising 23 Enhancement FET 24 Transmission gate 25 Connection 26 Bump 27 Bias voltage 28 P characteristic 29 n characteristic 30 Input / output characteristic 31 Video signal 32 Output signal 33 p channel 34 n channel

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-155380 (JP, A) JP-A-2-231879 (JP, A) JP-A-5-165435 (JP, A) JP-A-5-165435 64103 (JP, A) JP-A-4-257892 (JP, A) JP-A-5-19724 (JP, A) JP-A-1-167794 (JP, A) JP-A-5-45668 (JP, A) JP-A-3-280676 (JP, A) JP-A-3-89393 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/133 550 G09G 3/36

Claims (3)

(57) [Claims] 1. A video signal circuit for generating a video signal, a shift register or a decoder for generating a shift pulse, a sample and hold for sampling a video signal by the shift pulse to generate a display data signal, and inputting a display data signal. A drive circuit for a liquid crystal display device, comprising: an output buffer for generating an output signal asymmetric with respect to a display data signal; and an active matrix type liquid crystal panel for inputting the output signal. 2. The driving circuit for a liquid crystal display device according to claim 1, wherein the output characteristics of the output buffer have a gain that varies according to the magnitude of the video signal. 3. A driving circuit for a liquid crystal display device according to claim 1, wherein the output characteristic of the output buffer has a constant gain greater than 1.