JP3230407B2 - PLL circuit module - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit module, and more particularly, to a transmission PLL circuit for obtaining a transmission signal and a reception PLL for obtaining a reception processing signal.
The present invention relates to a PLL circuit module improved so that interference between oscillation circuits of an L circuit can be suppressed.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional PLL (Phase Locked).
FIG. 3 is a configuration diagram illustrating an example of a loop (phase locked loop) circuit module. This type of PLL circuit module is used for mobile phones, mobile communication devices, and the like. The PLL circuit module 500 includes a PLL IC 31 in which a phase comparator, a counter, a charge pump, and the like are integrated into one chip,
F (Low Pass Filter) 32 and VCO (Voltage C)
A transmission PLL circuit 30 comprising an ontorolled oscillator (voltage controlled oscillator) 33 and a PLL I
The receiving PLL circuit 20 including the C21, the LPF 22, and the VCO 23 is arranged on the same substrate (for example, a glass epoxy substrate).

In the transmission PLL circuit 30, P
When the reference signal So is externally applied, the LL IC 31 divides the frequency of the feedback signal from the VCO 33 by a built-in counter (not shown) and outputs an error voltage corresponding to the phase difference with the reference signal So. . The reference signal S
The frequency of o is, for example, about 10 MHz to 20 MHz, and 12.8 MHz or 15.36 MHz is used. Then, the LPF 32 outputs a low frequency component of the error voltage as a control voltage. The VCO 33 directly modulates according to the control voltage and a modulation signal S1 given from the outside, and outputs a transmission signal Sa. This transmission signal Sa
Is, for example, 925 MHz. afterwards,
The transmission signal Sa is amplified by an external power amplifier PA and becomes a transmission signal Stx, which is supplied to an antenna (not shown). On the other hand, in the receiving PLL circuit 20, the PLL IC 21 receives the reference signal So (in general, the reference signal So is commonly used in a module).
A feedback signal from the VCO 23 is divided by a built-in counter (not shown), and an error voltage corresponding to a phase difference from the reference signal So is output. Then, LPF22
Outputs a low frequency component of the error voltage as a control voltage. The VCO 23 receives a signal for reception processing at a frequency corresponding to the control voltage (for example, a signal necessary for controlling the reception frequency) S
Output rx to the outside. The frequency frx of the reception processing signal Srx is, for example, 836 MHz.

[0004]

In the conventional PLL circuit module 500, as shown in the above numerical examples,
The transmission signal Sa and the reception processing signal Srx have high frequencies,
Their frequency difference is generally relatively small (8 in the above example).
9 MHz), the frequency of the oscillation system of the transmission PLL circuit 30 and the frequency of the oscillation system of the reception PLL circuit 20 are close to each other. Therefore, as shown in FIG. 3 , there is a problem that interference I between the oscillation systems of the transmission PLL circuit 30 and the reception PLL circuit 20 is likely to occur. When the transmission signal Stx amplified by the power amplifier PA jumps into the oscillation system, a wraparound K occurs, the oscillation system of the transmission PLL circuit 30 and the transmission signal Stx have the same frequency and a phase shift. There is a problem that fog such as deterioration of noise characteristics and fluctuation occurs. This problem becomes more significant as the size of the module is reduced.

Accordingly, a first object of the present invention is to provide a PLL circuit module capable of suppressing interference between the oscillation systems of a transmission PLL circuit and a reception PLL circuit.
A second object of the present invention is to provide a PLL circuit module that can reduce fog on an oscillation system of a transmission PLL circuit.

[0006]

According to a first aspect, the present invention provides a PLL IC (11) and a low-pass filter (1).
2) and a transmission PL including a voltage-controlled oscillator (13)
L circuit (10) and IC for PLL (21),
Low-pass filter (22) and voltage-controlled oscillator (23)
PLL circuit module (20) comprising a receiving PLL circuit (20) provided on the same substrate and outputting a transmission signal (Sa) and a reception processing signal (Srx) from each of the PLL circuits (10) and (20). In the transmission PLL
In the circuit (10), 1 / n (n) of the transmission signal (Sa)
≧ 2), the oscillation signal (Ha) is multiplied n times by the multiplication circuit (1) to obtain a transmission signal (Sa), and the reception PLL circuit (20) ,
A PLL circuit module (100) characterized by outputting an oscillation signal having the frequency of the reception processing signal (Srx) and using the oscillation signal as a reception processing signal (Srx).

In a second aspect, the present invention relates to a PLL I
C (31), a transmission PLL circuit (30) including a low-pass filter (32), and a voltage-controlled oscillator (33), and a PLL IC (41), a low-pass filter (42), and a voltage-controlled oscillator. (43) are configured on the same substrate, and the PLL circuits (30) and (40) output the transmission signal (Sa) and the reception processing signal (Srx), respectively. In the PLL circuit module, the transmission PLL circuit (10) outputs an oscillation signal having the frequency of the transmission signal (Sa), and uses the oscillation signal as a transmission signal (Sa). , Its reception processing signal (Sr
x), an oscillation signal (Hb) having a frequency of 1 / m (m ≧ 2) is output, and the oscillation signal (Hb) is multiplied m times by a multiplication circuit (2) to generate a reception processing signal (Srx). A PLL circuit module (200) is provided.

[0008]

The PLL circuit module according to the first aspect (10)
0), the transmission PLL circuit (10) transmits the transmission signal (S
An oscillation signal (Ha) having a frequency of 1 / n of the frequency a) is output, and the oscillation signal (Ha) is multiplied n times by a multiplication circuit (1) to obtain a transmission signal (Sa). Therefore, the frequency difference between the oscillation system of the transmission PLL circuit (10) and the oscillation system of the reception PLL circuit (20) increases, and interference between the oscillation systems can be suppressed. Further, the frequency of the transmission signal (Sa) amplified by the power amplifier is much higher than the frequency of the oscillation system of the transmission PLL circuit (10), so that fog can be reduced.

In the PLL circuit module (200) of the second aspect, the receiving PLL circuit (40) has an oscillation signal (Hb) having a frequency of 1 / m of the reception processing signal (Srx).
And the oscillation signal (Hb) is multiplied by m in a multiplication circuit (2).
The signal is multiplied by two times to obtain a reception processing signal (Srx). Therefore, the oscillation system of the transmission PLL circuit (30) and the reception PL
The frequency difference between the L circuit (40) and the oscillation system increases, and interference between the oscillation systems can be suppressed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in more detail with reference to the embodiments shown in the drawings. It should be noted that the present invention is not limited by this.

FIG. 1 is a block diagram showing a PLL circuit module according to a first embodiment of the present invention. This type of PLL circuit module is used for, for example, a mobile phone, a mobile communication device, and the like. The PLL circuit module 100 includes a transmission PLL circuit 10 including a PLL IC 11, an LPF 12, and a VCO 13 in which a phase comparator, a counter, a charge pump, and the like are integrated into one chip, and outputs the output of the transmission PLL circuit 10 to n. A multiplying circuit 1 for multiplying by a factor of 2 (n ≧ 2) and a receiving PLL circuit 20 composed of the same PLL IC 21, LPF 22, and VCO 23 as described above are arranged on the same substrate (for example, a glass epoxy substrate). It is configured. However, the transmission PLL circuit 10 outputs an oscillation signal Ha having a frequency fa / n of 1 / n of the frequency fa of the transmission signal Sa. Note that in order to simplify the configuration of the multiplication circuit 1, n
= 2 or n = 3.

Now, in the transmission PLL circuit 10, P
When the reference signal So is externally applied, the LL IC 11 divides the frequency of the feedback signal from the VCO 13 by a built-in counter (not shown) and outputs an error voltage corresponding to the phase difference with the reference signal So. . The reference signal S
The frequency of o is, for example, about 10 MHz to 20 MHz, and 12.8 MHz or 15.36 MHz is used. Then, the LPF 12 outputs a low frequency component of the error voltage as a control voltage. The VCO 13 performs direct modulation according to the control voltage and a modulation signal S1 provided from the outside, and outputs an oscillation signal Ha. This oscillation signal Ha
Is fa / n, so that the frequency division ratio of the counter of the PLL IC 11 is the same as that of the conventional PLL circuit module 500 (FIG.
3 ) is 1 / n times the frequency division ratio of the PLL IC 31 of FIG. Next, the multiplying circuit 1 multiplies the oscillation signal Ha by n times and outputs it as a transmission signal Sa. The frequency fa of the transmission signal Sa is, for example, 925 MHz. Thereafter, the transmission signal Sa is amplified by an external power amplifier PA to become a transmission signal Stx, which is supplied to an antenna (not shown).

On the other hand, in the receiving PLL circuit 20, P
When the reference signal So is added to the LL IC 21 (generally, the reference signal So is commonly used in the module), the VCO 23 is provided by a built-in counter (not shown).
From the feedback signal from the reference signal So
And outputs an error voltage corresponding to the phase difference between. Then L
The PF 22 outputs a low frequency component of the error voltage as a control voltage. The VCO 23 outputs an oscillation signal having a frequency corresponding to the control voltage to the outside as a reception processing signal Srx required for reception. The frequency frx of the reception processing signal Srx is, for example, 836 MHz. The VC
It is convenient to output the O23 oscillation signal without passing through the multiplier circuit from the viewpoint of a high C / N (Carrier To Noise Ratio).

The PLL circuit module 1 of the first embodiment
According to 00, the transmission PLL circuit 10 outputs an oscillation signal Ha having a frequency fa / n of 1 / n of the frequency fa of the transmission signal Sa, and multiplies the oscillation signal Ha by n times by the multiplication circuit 1 for transmission. Let it be a signal Sa. Therefore, it is possible to increase the frequency difference between the oscillation system of the transmission PLL circuit 10 and the oscillation system of the reception PLL circuit 20, thereby suppressing interference between the oscillation systems. For example, in the above numerical example, if n = 2, the frequency of the oscillation system of the receiving PLL circuit 20 is 836M
Hz, the frequency of the oscillation system of the transmission PLL circuit 10 is 462.5 MHz, so that interference between the oscillation systems can be effectively suppressed. The frequency (fa) of the transmission signal Stx amplified by the power amplifier PA is equal to the transmission PL.
Since the frequency is much higher than the frequency of the oscillation system of the L circuit 10, fog can be reduced.

Second Embodiment FIG. 2 is a block diagram showing a PLL circuit module according to a second embodiment of the present invention. This type of PLL circuit module is used for, for example, a mobile phone, a mobile communication device, and the like. The PLL circuit module 200 includes a PLL IC 31 including a phase comparator, a counter, a charge pump, and the like on one chip, a transmission PLL circuit 30 including an LPF 32 and a VCO 33, and a PLL IC 41 similar to the above.
, LPF42, and VCO43 for receiving PLL
The circuit 40 and a multiplying circuit 2 for multiplying the output of the receiving PLL circuit 40 by m (m ≧ 2) are arranged on the same substrate (for example, a glass epoxy substrate). However, the reception PLL circuit 40 outputs an oscillation signal Hb having a frequency frx / m that is 1 / m of the frequency frx of the reception processing signal (for example, a signal necessary for controlling the reception frequency) Srx. In addition, for the above-mentioned reason, m = 2 or m =
It is preferably 3.

Now, in the transmission PLL circuit 30, P
When the reference signal So is externally applied, the LL IC 31 divides the frequency of the feedback signal from the VCO 33 by a built-in counter (not shown) and outputs an error voltage corresponding to the phase difference with the reference signal So. . The reference signal S
The frequency of o is, for example, about 10 MHz to 20 MHz, and 12.8 MHz or 15.36 MHz is used. Then, the LPF 32 outputs a low frequency component of the error voltage as a control voltage. The VCO 33 directly modulates according to the control voltage and a modulation signal S1 given from the outside, and outputs a transmission signal Sa. This transmission signal Sa
Is, for example, 925 MHz. afterwards,
The transmission signal Sa is amplified by an external power amplifier PA and becomes a transmission signal Stx, which is supplied to an antenna (not shown).

On the other hand, in the receiving PLL circuit 40, P
The reference signal So is added to the LL IC 41 (generally, the reference signal So is commonly used in a module).
And a built-in counter (not shown) divides the frequency of the feedback signal from the VCO 43 and outputs an error voltage corresponding to the phase difference from the reference signal So. Then, LPF
Reference numeral 42 outputs the low-frequency component of the error voltage as a control voltage. The VCO 43 outputs an oscillation signal Hb having a frequency according to the control voltage. Since the frequency of the oscillation signal Hb is frx / m, the frequency division ratio of the counter of the PLL IC 41 is the same as that of the conventional PLL circuit module 500 (see FIG. 3 ).
1 / m times the frequency division ratio of the PLL IC 21 of FIG.
Next, the multiplying circuit 2 multiplies the oscillation signal Hb by m times and outputs it as a reception processing signal Srx. The frequency frx of the reception processing signal Srx is, for example, 836 MHz.

The PLL circuit module 2 of the second embodiment.
According to 00, the receiving PLL circuit 40 outputs an oscillation signal Hb having a frequency frx / m, which is 1 / m of the frequency frx of the reception processing signal Srx, and multiplies the oscillation signal Hb by a factor of m by the multiplier 2. As a reception processing signal Srx. Therefore, it is possible to increase the frequency difference between the oscillation system of the transmission PLL circuit 30 and the oscillation system of the reception PLL circuit 40, thereby suppressing interference between the oscillation systems. For example, in the above numerical example, if n = 2, the frequency of the oscillation system of the transmission PLL circuit 30 is 925 MHz, while the frequency of the reception PLL circuit 30 is 925 MHz.
Since the frequency of the oscillation system of the L circuit 40 is 418 MHz, interference between the oscillation systems can be effectively suppressed.

[0019]

According to the PLL circuit module of the present invention, by increasing the frequency difference between the oscillation circuits of the transmission PLL circuit and the reception PLL circuit or by lowering the frequencies of both oscillation systems, the oscillation circuit mutual oscillation is reduced. Interference can be suppressed. For this reason,
This is convenient for miniaturization. Further, it is possible to effectively reduce the fog of the transmission signal to the oscillation system, thereby preventing the deterioration of the phase noise characteristic and the occurrence of fluctuation. In particular, mobile phones,
It is useful as a PLL circuit module used for a mobile communication device or the like.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a PLL circuit module according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a PLL circuit module according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram showing a conventional PLL circuit module.

[Explanation of symbols]

 100,200 PLL circuit module 1,2 Multiplier circuit 10,30 PLL circuit for transmission 11,21,31,41 IC for PLL 12,22,32,42 LPF 13,23,33,43 VCO 20,40 PLL for reception Circuit Ha, Hb Oscillation signal Sa, Stx Transmission signal Srx Reception processing signal So Reference signal S1 Modulation signal

──────────────────────────────────────────────────続 き Continuation of the front page (56) References Special Tables Hei 8-506235 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04B 1/10 H03L 7/18 H04B 1 / 04 H04B 1/50

Claims (2)

(57) [Claims] A transmission PLL circuit (10) including a PLL IC (11), a low-pass filter (12), and a voltage controlled oscillator (13), and a PLL IC (2).
1) A receiving PLL circuit (20) including a low-pass filter (22) and a voltage controlled oscillator (23) is formed on the same substrate, and a transmission signal is transmitted from each of the PLL circuits (10) and (20). (Sa) and the reception processing signal (Sr
x), the transmission PLL circuit (10) transmits the transmission signal (S
a) output an oscillation signal (Ha) having a frequency of 1 / n (n ≧ 2), and multiply the oscillation signal (Ha) n times by a multiplication circuit (1) to obtain a transmission signal (Sa); The receiving PLL circuit (20) outputs an oscillation signal having the frequency of the reception processing signal (Srx) and uses the oscillation signal as a reception processing signal (Srx). . 2. A transmission PLL circuit (30) including a PLL IC (31), a low-pass filter (32), and a voltage controlled oscillator (33).
1), a receiving PLL circuit (40) including a low-pass filter (42) and a voltage-controlled oscillator (43) is formed on the same substrate, and a transmission signal is transmitted from each of the PLL circuits (30) and (40). (Sa) and the reception processing signal (Sr
x), the transmission PLL circuit (10) transmits the transmission signal (S
a) output an oscillation signal having the frequency, and use the oscillation signal as a transmission signal (Sa). The reception PLL circuit (40) outputs 1 / m (m ≧ 2) of the reception processing signal (Srx). A PLL circuit module (200), which outputs an oscillation signal (Hb) having a frequency, and multiplies the oscillation signal (Hb) m times by a multiplier circuit (2) to obtain a reception processing signal (Srx). .