JP3230769B2 - Fading simulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for evaluating the reception performance of a digital mobile communication system or the like, and is similar to a signal similar to a signal that has undergone Rayleigh scattering, Doppler shift, or fading. To a fading simulator that generates in real time.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional fading simulator. The in-phase signal I (t) and the quadrature signal Q (t) are applied to a quadrature modulator 11, and the modulation output is converted (divided) into a real part and an imaginary part by a coordinate converter 12 that converts polar coordinates into quadrature coordinates. ) Is done. These converted real and imaginary parts are supplied to multiplying DA converters 15 and 16 through digital low-pass filters 13 and 14, respectively. The output voltage of the variable DC power supply 17 is applied to the reference voltage sources of the DA converters 15 and 16 and is multiplied by the DC voltage _VA .

The outputs of the DA converters 15 and 16 are supplied to multipliers 18 and 19, respectively, and output from a sine wave oscillator 21.
The output of the carrier of frequency f _A from
And supplied to a multiplier 19 through a 90-degree phase shift circuit 22. The outputs of the multipliers 18 and 19 are added by an adder 23, and the added output, that is, the quadrature modulation output is randomized by a multiplier 24. Noise generator 25
A, the noise of which is adjusted to an appropriate level by the attenuator 26
(T). The signal multiplied by the noise is attenuated by G _{A in the} attenuator 27, and the attenuated output is delayed by t _A by the variable delay means 28 to be multiplied by the multiplier 29.
And supplied to a multiplier 32 through a phase shifter 31. The signal of the frequency f ₁ is supplied from the sine oscillator 33 to the multiplier 29 and also supplied to the multiplier 32 through the 90-degree phase shifter 34. Outputs of the multipliers 29 and 32 are added by an adder 35.

On the other hand, the output of the adder 23 is branched and passed through a fixed contact F of a changeover switch 36 to a multiplier 37.
Is also supplied. The multiplier 37 receives the noise from the noise generator 25 through the attenuator 38 as noise B (t). The output of the multiplier 37 is attenuated by G _B by the attenuator 39, and the attenuated output is delayed by t _B by the variable delay means 41 and supplied to the multiplier 42. The output of the oscillator 43 that generates the sine wave of the frequency f ₂ is supplied to the multiplier 42 and also supplied to the multiplier 45 through the 90-degree phase shifter 44, and the output of the delay means 41 is supplied to the multiplier 45 through the phase shifter 46. Supplied.
Outputs of the multipliers 42 and 45 are added by an adder 47. Each output of the adder 35 and 47 are added by the adder 48, the added output is outputted to the output terminal 51 receives attenuated by G _C in the attenuator 49.

The in-phase signal I '(t) and the quadrature signal Q' (t) quadrature-modulate the carrier in the quadrature modulator 52, and the modulation output is converted into a real part and an imaginary part in the coordinate converter 53. These real and imaginary parts are supplied to multiplying DA converters 56 and 57 through digital low-pass filters 54 and 55, respectively. DA converter 5
Is V _B is multiplied from the variable power supply 58 is voltage V _B is applied to the reference power supply terminal to 6,57. DA converters 56 and 5
7 are supplied to multipliers 59 and 61, respectively.
The carrier having the frequency f _B from the oscillator 62 is supplied to the multiplier 59 and is also supplied to the multiplier 6 through the 90-degree phase shifter 63.
1 is supplied. The output of the multipliers 59 and 61 is the adder 6
4, and the added output is supplied to the multiplier 37 through the fixed contact I side of the changeover switch 36.

In communication between a mobile station and a fixed or mobile station, a direct wave and a reflected wave are received simultaneously, and the level of the reflected wave fluctuates and a plurality of reflected waves are mainly received. For this reason, the received signal has a variable level and phase. Further, the reception frequency fluctuates due to a so-called Doppler shift due to relative movement between the mobile station and the fixed station. To simulate these fluctuation states (fading simulation), the changeover switch 36 is connected to the fixed contact F side. At this time, the output signal obtained at the output terminal 51 is represented by the following equation.

G _C · [G _A · A (t) · cos ・ 2π
(F _A + f ₁ ) · (t−t _A ) + θ _A (t)｝ · V _A +
_{G B · B (t) ·} cos {2π (f A + f 2) · (t-
t _B ) + θ _A (t)｝ · V _A ] where A (t) is Rayleigh scattering of the first path of the radio wave, and B (t) is equivalent to Rayleigh scattering of the second path of the radio wave. The attenuations G _A and G _B are the attenuations of the first and second passages, respectively. f _A is the carrier frequency, f ₁ , f
₂ is the Doppler shift frequency in the first and second passages, respectively. Θ _A (t) is transmission information. Further, t _A and t _B are time delays of the first and second passages, respectively. Therefore, the attenuation of each of these parts or the delay means 2
By changing the delay amounts t _A , t _{B and the} frequencies f ₁ , f _2, etc. of 8, 41, it is possible to simulate various states, that is, states that have actually undergone fading.

On the other hand, the interference between adjacent channels is simulated.
Switch 36 to the fixed contact I side.
You. The output of the output terminal 51 in this state is expressed by the following equation.
It is. G_C・ [G_AA (t) · cos ｛2π (f_A+ F₁)
・ (Tt_A) + Θ_A(T)｝ · V_A+ G_B・ B (t)
・ Cos ｛2π (f_B+ F_Two) ・ (Tt_B) + Θ
_B(T)｝ · V_BWhere θ_B(T) is transmission information on the channel B side. f
_BIs the carrier frequency on the channel B side. In this case adjacent
The carrier frequency between channels is f_A+ F ₁And f_B
+ F_TwoAnd the time or phase is late.
The frequency difference is adjusted by f
₁, F_Two, F_A, F_BChanged by the level
G_A, G_BIs changed by

[0009]

Conventionally, variable delay means 28 and 41 have been used to change the difference between the two paths. However, in order to obtain these delay times t _A and t _B , usually, a so-called line is used. Since the delay time of the cable is used, the delay time changes according to the temperature fluctuation, and the delay distortion is caused by the frequency, and it is difficult to change the delay time over a wide range with higher resolution.

A number of high frequency balanced modulators or multipliers 18, 19, 24, 29, 32, 37, 42, 4
5, 59, 61 are used, and more high frequency phase shifters are used, so that it is difficult to adjust the frequency. Moreover, two systems are used and the configuration is complicated.

[0011]

According to the present invention, the transmission code is stepwise delayed from the code delay means.
The first real part and the first imaginary part, the second real part and the second imaginary part are converted by the first and second coordinate exchange means for each code of the two delayed outputs, and the first real part and the first imaginary part are The cosine wave output and the sine wave output from the first digital synthesizer are multiplied by first and second multiplying means, respectively. The noise is applied and the signal is converted to an analog signal. On the other hand, the second real part and the second imaginary part are obtained by multiplying the cosine wave output and the sine wave output from the second digital synthesizer by third and fourth multiplication means, respectively, and these third and fourth multiplication calculation powers are the third and fourth multiplication powers. The above-mentioned noise is multiplied by the quadrature type DA converter and converted into an analog signal. The outputs of the first and third DA converters are added by the first adder, and the second, third and fourth DA converters are added.
The outputs of the conversion means are added by the second addition means, and the outputs of the first and second addition means are orthogonally modulated by the orthogonal modulation means.

[0012]

FIG. 1 shows an embodiment of the present invention. The transmission information θ (t) from the quadrature modulator 71 is supplied to a code delay unit 72, and the code unit, that is, a stepwise delay is performed.
The code delay means 72 is, for example, a shift register or a FIFO.
A memory or the like is used. Also, as the quadrature modulator 71,
The data generation clock from the frequency divider 73 is
The divided output is counted by an address counter 75, and the in-phase memory 76 and the quadrature memory 77 are read out using the count value of the address counter 75 as an address, and the in-phase signal I is (T) and quadrature signal Q
(T) is output. These two outputs are supplied to the modulator 71 through the changeover switches 78 and 79, respectively, and are modulated at the carrier wavelength, for example, π / 4DQPSK. Switch 7
8, 79 are switched when an in-phase signal and a quadrature signal are input from the outside.

The code delay means 72 outputs a signal to which a different delay has been given for each code unit or to which the same delay has been given. When the code delay unit 72 is a shift register, for example, outputs from different taps (shift stages) or outputs from the same tap (shift stage) are extracted as code transmission information θ _A (t) and θ _B (t), respectively. Are supplied to the coordinate conversion means 82 and 83. Each of the input codes is converted into polar coordinates and orthogonal coordinates by the coordinate conversion means 82 and 83, and a real part and an imaginary part are respectively output. The real part and the imaginary part from the coordinate transformation means 82 are respectively converted to the FIR digital low-pass filter 8 if necessary.
4, 85 to the multipliers 86, 87. The real and imaginary parts from the coordinate conversion means 83 are supplied to multipliers 91 and 92 through FIR digital low-pass filters 88 and 89, respectively, as needed.

On the other hand, digital synthesizers 93 and 94 are provided. The digital synthesizers 93 and 94 can change the phase and frequency, respectively, and are configured as shown in FIG. 2A, for example. That is, the output of the adder 97 is latched in the latch circuit 96 by one output of which the frequency f _R from the toggle flip-flop 95 is halved. The adder 97 adds the output of the latch circuit 96 and the frequency data k _f. The output of the latch circuit 96 is added to the phase data kθ by the adder circuit 98, and the output thereof is given a 0-degree phase or a 90-degree phase shift in the phase shift circuit 99, and is output to the sine wave memory 101 as a read address. Supplied. The sine wave memory 101 stores the level of each sample point of the sine waveform, and the read digital sine wave signal is stored in the latch circuit 96.
Are latched in the latch circuit 102 by a latch command to the latch circuit 103, and latched by the latch circuit 103 by a signal 180 degrees out of phase with the latch command. The output of the latch circuit 102 becomes a digital sine wave output, and the output of the latch circuit 103 is latched by the latch circuit 104 simultaneously with the latch of the latch circuit 96 .
4 yields a digital cosine wave output. Since the frequency data k _f is cumulatively added for each of the frequency f _R / 2 clock, the frequency becomes higher as the frequency data k _f is large, the frequency becomes lower as the frequency data k _f is small.
Since the phase shift circuit 99 outputs the data as it is or outputs it with a phase shift of 90 degrees, as shown in FIG. 2B, the most significant bit and the next bit of the input data are passed as they are, or they are excluded. It is only necessary to switch whether the logical OR is taken as the most significant bit and the inverted version of the second most significant bit is output as the second most significant bit. Thus, the frequency is f _R × kf ÷
A sine wave output and a cosine wave output having 2 ^{L + 1} and a phase θ of 2π × kθ ÷ 2 ^L are obtained. f _R is the frequency of the clock driving the flip-flop 95.

Returning to the description of FIG.
Frequency f₁+ Fa is set, and phase θa is set
As a result, the cosine wave output cos ｛2π (f₁+ F
a) t + θa｝ is output and supplied to the multiplier 86,
Sine wave output sin ｛2π (f ₁+ Fa) · t + θa｝
Is output and supplied to the multiplier 87. On the other hand synthesis
Frequency 94 for the user 94₁+ Fb is set and the phase
θb is output, and its cosine wave output cos ｛2π (f₁+
fb) · t + θb} is supplied to the multiplier 91 to output a sine wave
Force sin ｛2π (f₁+ Fb) · t + θb} is the multiplier 9
2 is supplied. The outputs of the multipliers 86 and 87 are respectively
The signals are supplied to multiplying DA converters 105 and 106,
The outputs of the converters 91 and 92 are respectively multiplied DA converters 10
7, 108. On the other hand, the random noise generator 10
9, random noise is generated, and the noise is
After being attenuated by the attenuator 111,
Is added to the DC voltage by the adding circuit 113, and the addition is performed.
The output of the circuit 113 is multiplied as the Rayleigh noise A (t).
It is supplied to each reference power supply terminal of the DA converters 105 and 106.
Multiplied by the input digital signal and
The digital signal is converted to an analog signal. Similarly noise generation
Noise from the generator 109 is added to the adder 1 through the attenuator 114.
15 and the output DC voltage of the variable DC power supply 116
Are added, and the output from the adder 115 is the Rayleigh noise B
(T) is the reference voltage of the multiplier DA converters 107 and 108.
Supplied to the source terminal and multiplied by the input digital signal.
And convert the digital signal to an analog signal.
Is replaced.

[0016] Each output of the DA converter 105 is attenuated by Ga, respectively, in each attenuator 117, 118, and each output of from DA converter 107, 108 are attenuated by the respective G _B In the attenuator 119, 121 You. The outputs of the attenuators 117 and 119 are added in an adder 122 and supplied to a multiplier 123.
Outputs 18 and 121 are added by an adder 124 and supplied to a multiplier 125.

The signal from the reference signal generator 126 has a frequency f _R and is supplied as a clock to each of the synthesizers 93 and 94, and its output is a frequency divider 127.
, Is supplied to the frequency divider 73, and is also supplied as a shift clock to the code delay unit 72, and is supplied to each unit as a clock for other digital processing. Further, the output of the reference signal generator 126 is supplied to a phase locked loop (PLL) 128 as a reference signal, and the PLL 128 has a carrier frequency f _0.
−f ₁ is set and input, and the frequency f ₀ synchronized with the reference signal
The −f ₁ signal cos {2π (f ₀ −f ₁ ) · t} is output and supplied to the multiplier 123 as a carrier signal and to the multiplier 125 through the 90-degree phase shifter 129. The output of the multipliers 123 and 125 is
, And the added output is attenuated by the attenuator 132 and output to the output terminal 133. Multipliers 123, 12
5, the phase shifter 129 and the adder 131 are provided with a quadrature modulation circuit 134.
Is composed. In order to set the output carrier frequency of the PLL 128 to f ₀ −f ₁ , it is necessary to increase or decrease the carrier frequency f ₀ of the output signal of the output terminal 133, that is, to generate a negative frequency in the synthesizers 93 and 94. because it can not, as a high frequency by f _1,
On the other hand, the positive and negative frequencies fa and fb can be freely selected, so that the frequency of the output carrier in the quadrature modulation circuit 13 is positive or negative with respect to the center f _0.
a and fb can be changed.

In this configuration, if a shift register is used for the code delay means 72, the shift frequency is f _d, and the shift stages from which the output is taken out are na and nb, they are supplied to coordinate conversion means 82 and 83. The code information is θ _A (t) = θ (t−na / fd) and θ _B (t), respectively.
= Θ (t-nb / fd). Therefore, the signal output from the terminal 133 is as follows.

Gc · [Ga · A (t) · cos ｛2π (f ₀ + fa) · t + θa + θ (t−na / fd)} + Gb · B (t) · cos ｛2π (f ₀ + fb) · t + θb + θ ( t-nb / fd)｝] In the case of fading simulation, code delay means 7
2, two transmission codes θ
_A (t) and θ _B (t) or the transmission code θ
_The delay amount is slightly shifted while _A (t) and θ _B (t) maintain the correlation. Rayleigh scattering for two radio wave paths is given as A (t) and B (t), and each Doppler shift in the first radio wave path and the second radio wave path is f
Small values are given as a and fb, respectively. Part 2
The phase difference between the two radio paths is digital synthesizer 93,
The Rayleigh noise is determined by A (t) and B (t), and the amount of attenuation is changed by the attenuators 117 and 119. The delay time of the first radio wave path is ｛(na / fd) −θa / 2π (f ₀
+ Fa)}, and the time delay of the second radio path is given by {(nb / fd) −θb / 2π (f ₀ + fb)}. By doing so, it is possible to control each section and obtain a signal having a fading effect as in the prior art.

When an interference signal between adjacent channels is obtained, the two signals θ _A (t) and θ _B (t) output from the code delay means 72 are delayed from each other so that there is no correlation. In order to increase the difference in the amount and to obtain the frequency difference between the channels in that state, the synthesizer 93,
A part fa and fb of the set frequency of 94 are sufficiently separated from each other. Also in this case, it is possible to simulate an interference signal between adjacent channels as in the conventional case.

In the above description, the coordinate conversion means 82, filters 84 and 85, multipliers 86 and 87, and DA converter 10
5, 106, attenuator 111, adder 113, attenuator 11
By providing a plurality of pairs of the power supply 7 and the power supply 112, a simulation of multipath fading and an interference simulation between many other channels can be performed. In the above description, the fading simulation is performed on the π / 4DQPSK modulated signal. However, by changing the modulator 71, it is possible to simulate fading for another communication system and simulation of interference between adjacent channels.

[0022]

As described above, according to the present invention, the difference between the two paths and the difference between the signal paths of adjacent channel interference are determined by the difference between the delay in the code delay means 72 and the set phase in the frequency synthesizers 93 and 94. Since it is made digitally using the difference etc., it is not affected by fluctuations in ambient temperature because it does not use a delay line as in the past, it is stable against temperature and frequency changes continuously and over a wide range. It is possible to perform transmission delay simulation without distortion. In addition, since the processing of Rayleigh scattering and Doppler shift is realized digitally at a relatively low frequency,
The balance modulator and the phase shifter at a high frequency need only be the quadrature modulation circuit 134 at the final stage, so that the adjustment to the frequency is easy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2A is a block diagram illustrating an example of a digital synthesizer, and FIG. 2B is a block diagram illustrating a phase shift circuit 99 thereof.

FIG. 3 is a block diagram showing a conventional fading simulator.

Claims (1)

(57) [Claims] The present invention realizes a step delay of a transmission code , and
Second frequency to determine the code delay means for Ru timed delay of the passage, the first frequency data, the Doppler shift
Data and the first phase data are input and the first cosine wave
A first digital synth that outputs a signal and a first sine wave signal
Sizer, first frequency data, third frequency to determine Doppler shift
Data and the second phase data are input and the second cosine wave
A second digital synth that outputs a signal and a second sine wave signal
Receiving different step delays from the sizer and the code delay means.
First imaginary part and the first real part for each digit two code output, and the first and second coordinate transformation means, said first real and first imaginary obtaining second real and second imaginary part, respectively First and second multiplying means for multiplying the first digital synthesizer by a cosine wave output and a sine wave output, respectively; and the second real part and the second imaginary part by the second digital synthesizer. third and fourth multiplying means for multiplying the cosine wave output and the sine wave output of the user, respectively, and multiplying the output of the first and second multiplying means by noise, respectively, and converting the output to an analog signal. , Second DA
Converting means, the third and fourth multiplying means multiply the noise different from the noise respectively, and convert the analog signal into a third,
A fourth DA converter, and the first, a first addition means for adding the output of the third DA converting means, the second, the second adding means for adding the output of the fourth DA converter, a Four frequency data and the first frequency data are input.
An oscillator for generating a cosine wave having a frequency of the difference between them, and an output of the first adding means and the second adding means,
And a modulating means for quadrature modulating the frequency outputted by the fading simulator.