JP3236156B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device operating at a low power supply voltage.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a conventional semiconductor memory device. In the figure, A is a first memory block,
B to N are second to N-th memory blocks, which have a common configuration. Hereinafter, the configuration of the first memory block A will be described.

In the first memory block A, 1 is a word line, 3 is a memory cell, BIT1 and XBIT1 are bit lines, 2 is a transistor connecting the bit lines BIT1, XBIT1 and the memory cell 3, and 4 is a sense amplifier. , 5, and 6 are N-channel sense transistors in the sense amplifier 4, 7, 8 are P-channel sense transistors in the sense amplifier 4, 9 is an N-channel transistor having a large current supply capability, and 10 is a P-channel transistor having a large current supply capability. , DA1, XDA1 are data lines,
11 and 12 are transistors for connecting the bit lines BIT1 and XBIT1 to the data lines DA1 and XDA1, Y1 is a column selection signal for driving the transistors 11 and 12, 13
Is a read amplifier, 14 is a write amplifier, SAN is a sense amplifier drive signal for driving N-channel sense transistors 5 and 6, SAP is a sense amplifier drive signal for driving P-channel sense transistors 7 and 8, SE
N1 is a sense amplifier driver input signal for driving the N-channel transistor 9, SEP2 is a sense amplifier driver input signal for driving the P-channel transistor 10,
GON is a control signal for generating a column selection signal Y1.

The operation of the conventional semiconductor memory device having the above configuration will be described below.

When the potential of the word line 1 rises and reaches a certain level or more, the transistor 2 is activated, the data stored in the memory cell 3 is transferred to the bit line BIT1, and the bit line BIT1 and the bit line XBIT1 Causes a slight potential difference.

The potential difference between the bit line pair BIT1 and XBIT1 is amplified by sense amplifier drive signals SAN and SAP connected to the sense amplifier 4 to perform a read operation. At this time, since the sense amplifier group including the plurality of sense amplifiers 4 of the memory blocks A to N operates simultaneously, a large instantaneous current occurs, and a large voltage drop occurs due to the wiring resistance of the sense amplifier drive signals SAN and SAP. Therefore, the gates of the sense transistors 5 to 8
The source-to-source voltage is reduced, which adversely affects the speeding up of the amplification operation. To solve this problem, conventionally, the speed of the amplification operation has been increased by adjusting the operation timing of the sense amplifier drive signals SAN and SAP.

As for the operation timing of the sense amplifier drive signal, first, the case where the N-channel sense transistors 5 and 6 are operated first will be described.

FIG. 6A shows a timing chart.
By driving the sense amplifier drive signal SAN of the N-channel sense transistors 5 and 6 with the drive signal SEN1, the potential of the low-level bit line is lowered, and then the sense amplifier drive signal SAP of the P-channel sense transistors 7 and 8 Is driven by the drive signal SEP2 to raise the potential of the bit line on the high level side, thereby performing the amplification operation.

Second, the case where the P-channel sense transistors 7, 8 are operated first will be described. FIG. 7A shows a timing chart. By driving the sense amplifier drive signal SAP of the P-channel sense transistors 7 and 8 with the drive signal SEP2, the potential of the bit line pair serving as the gate potential of the sense transistor is increased in advance, and then the N-channel sense transistors 5 and 6 are driven. Of the sense amplifier drive signal SAN
By driving with EN1, the potential of the bit line on the low level side is dropped at a high speed to perform the amplification operation.

The data on the bit line pair amplified by the sense amplifier 4 is transferred to the data line pair DA1 and XDA1 when the column selection signal Y1 goes high, and is amplified by the read amplifier 13. The column decoder output signal goes high only for the selected column address. The column selection signal Y1 is determined by the column decoder output signal and the control signal GON. The selection signal Y1 is at a high level, and the bit line pair and the data line pair are connected.

Next, a data write operation will be described. Data line pair DA1, amplified by write amplifier 14
The data of XDA1 is transferred to the bit line pair BIT1 and XBIT1 when the column selection signal Y1 goes high, and is amplified by the sense amplifier 4. At this time, since the potential of the word line 1 has already risen and the transistor 2 has been activated, the data of the bit line BIT1 is transferred to the memory cell 3, and the data is written to the memory cell 3.

[0012]

In recent years, in order to realize low power consumption in systems and sets,
There is an increasing demand for a semiconductor memory device that operates at a high speed with a low power supply voltage of 3.3 V or less.

However, the conventional 5
When the conventional semiconductor memory device as shown in FIG. 5 which operates at a high speed with a power supply voltage of V is operated at a low voltage, the following is obtained.

First, the case where the N-channel sense transistors 5 and 6 are operated first will be described. FIG. 6B shows a timing chart. Even if the potential of the bit line pair which becomes the gate potential of the sense transistor drops and the P-channel sense transistors 7 and 8 operate, the P-channel sense transistors 7 and 8 are generally Since the threshold value is high and the current supply capability is small, it takes time to raise the potential of the bit line on the high level side with the shift to a low-voltage power supply.
Amplifying operation is delayed.

Second, the case where the P-channel sense transistors 7 and 8 are operated first will be described. FIG. 7B shows a timing chart. Also in this case, it takes time to raise the bit line potential on the high level side with the reduction in the power supply voltage, so that the bit line potential on the high level side is reduced by the operation start time of the N-channel sense transistors 5 and 6. It cannot be sufficiently increased, and therefore, the amplification operation of the sense amplifier 4 for amplifying the potential difference between the bit line pair is delayed.

Third, a case where the N-channel sense transistors 5, 6 and the P-channel sense transistors 7, 8 are operated simultaneously will be described. In this case,
Since a through current flows between the grounds and the potential of the ground rises, it is delayed to lower the bit line potential on the low level side, and the amplification operation of the sense amplifier 4 is delayed.

As described above, the amplifying operation of the sense amplifier is delayed, which adversely affects the high-speed operation at a low voltage.

Also, at the time of data reading, the bit line and the data line are connected, so that the driving load connected to the sense amplifier 4 increases, the current consumption at the time of data reading increases, and the power consumption is reduced. , And speeding up.

Further, when the voltage is lowered, there is a disadvantage that the data line amplifying operation is slowed down at the time of data writing due to the lowering of the voltage.

[0020] The present invention has been made in view of the above problems, its object is to provide a semi-conductor memory device for high-speed operation at a low power supply voltage.

[0021]

In order to achieve the above object, according to the present invention, after performing initial amplification for lowering the potential of the low-level bit line while maintaining the potential of the high-level bit line, By adopting a configuration capable of raising the potential of the bit line on the high level side, the amplification operation of the bit line is performed at high speed .

That is , in the semiconductor memory device according to the first aspect of the present invention, an N-channel sense amplifier group and a P-channel sense amplifier group for amplifying a potential difference between a pair of bit lines, and a current supply capability for driving the N-channel sense amplifier group. Sense amplifier drive signal generation circuit constituted by an N-channel transistor having a large current, and second sense amplifier drive signal generation circuit constituted by a P-channel transistor having a small current supply capability for driving the P-channel sense amplifier group And a third sense amplifier drive signal generation circuit composed of a P-channel transistor having a large current supply capability, and the first and second sense amplifier drive signal generation circuits are activated almost simultaneously to reduce the potential difference between the bit lines. After the initial amplification, the third sense amplifier drive signal is generated. A configuration in which a control circuit for activating the road.

[0023]

According to the above-mentioned structure, according to the first aspect of the present invention,
By activating the first and second sense amplifier drive signal generation circuits almost simultaneously, the P-channel sense amplifier group is driven by P-channel transistors having a small current supply capability, and the potential of the high-level bit line is lowered. The N-channel sense amplifier group is driven by an N-channel transistor having a large current supply capability while maintaining the potential not to lower the potential of the low-level bit line, thereby performing initial amplification. Thereafter, by activating the third sense amplifier drive signal generation circuit, the P-channel sense amplifier group is driven by the P-channel transistors having a large current supply capability, and the potential of the high-level bit line is increased. As a result, the instantaneous current during sense amplifier operation is effectively suppressed, row cracking amplifying operation of the bit line at a high speed
You.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the semiconductor memory device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a semiconductor memory device according to the present invention. In the figure, A is a first memory block, and B to N are second to Nth memory blocks, which have a common configuration. Hereinafter, the configuration of the first memory block A will be described.

In the first memory block A, 1
Is a word line, 3 is a memory cell, BIT1, XBIT1
Is a bit line, 2 is a transistor connecting the bit lines BIT1 and XBIT1 and the memory cell 3, 4 is a sense amplifier, 5 and 6 are N-channel sense transistors in the sense amplifier 4, and 7 and 8 are P transistors in the sense amplifier 4. Channel sense transistors, DA1 and XDA1 are data lines, 1
1 and 12 are bit lines BIT1 and XBIT1 and data line D
A1 and XDA1 are connected to the transistor, Y1 is a column selection signal for driving the transistors 11 and 12, 13 is a read amplifier, and 14 is a write amplifier.

Reference numeral 30 denotes a first sense amplifier drive signal generation circuit comprising an N-channel transistor 9 having a large current supply capability, and is driven by a sense amplifier driver input signal SEN1 to generate a sense amplifier drive signal SAN. , The two N-channel sense transistors 5 and 6 of the sense amplifier 4 are driven.

Reference numeral 31 denotes a second sense amplifier drive signal generating circuit comprising a P-channel transistor 15 having a small current supply capability, and is driven by a sense amplifier driver input signal SEP1 to generate a sense amplifier drive signal SAP. , The two P-channel sense transistors 7 and 8 of the sense amplifier 4 are driven.

Further, reference numeral 32 denotes a third sense amplifier drive signal generation circuit comprising a P-channel transistor 10 having a large current supply capability, and is driven by a sense amplifier driver input signal SEP2 to generate a sense amplifier drive signal SAP. , The two P-channel sense transistors 7 and 8 of the sense amplifier 4 are driven.

Numeral 35 denotes a control circuit, which is the three types of sense amplifier driver input signals SEN1, SEP1, and SE.
3A. Specifically, as shown in FIG. 3A, a sense amplifier driver input signal SEN1 and SEP1 are simultaneously generated to generate the first and second sense amplifier drive signals. The circuits 30 and 31 are activated almost simultaneously, and thereafter, the sense amplifier driver input signal SE
It has a function of generating P2 and activating the third sense amplifier drive signal generation circuit 32.

GON and GOFF are control signals for controlling the column selection signal Y1 and are input to the AND circuit 40. The AND circuit 40, as shown in FIG.
The generation of the control signal GON generates the column selection signal Y1, while the generation of another control signal GOFF stops the generation of the column selection signal Y1. The control signal GOFF
Occurs in synchronization with the amplification operation start signal of the read amplifier 13 (becomes high level). A control circuit for inactivating the transistors 11 and 12 connecting the bit line and the data line in synchronization with the time when the read amplifier 13 starts amplifying the data line by the control signal GOFF and the AND circuit 40 41.

A data line pull-up circuit 16 comprises P-channel transistors 20 and 21 arranged on data lines DA1 and XDA1, as shown in FIG. 2A, for example. , Which are controlled by a control signal PUG.

The data line pull-up circuit 16 corresponds to FIG.
As shown in (b), instead of the configuration shown in (a), two Ns for supplying a power supply voltage to the data lines DA1 and XDA1 are used.
It can be composed of channel transistors 22 and 23, which are controlled by the power supply voltage.

A data write sense amplifier 17 lowers the potential of the low-level data line.
The circuit includes two N-channel transistors 25 and 26 for amplifying the data lines DA1 and XDA1, and an N-channel transistor 24 for controlling these transistors. The control transistor 24 is controlled by a sense amplifier driver input signal SAB. And a sense amplifier drive signal SAB1 for driving the two transistors 25 and 26.

FIG. 3A is a timing chart of the sense amplifier operation at a low voltage in the circuit of the present embodiment.
FIG. 3B shows the column selection signal Y in the circuit of the present embodiment.
6 is a timing chart of the occurrence of a 1;

FIG. 4 is a timing chart of the control signals PUG and SAB.

Next, the operation of the circuit of FIG. 1 will be described.

When the potential of the word line 1 rises and reaches a certain level or more, the transistor 2 is activated, the data stored in the memory cell 3 is transferred to the bit line BIT1, and the bit line BIT1 and the bit line XBIT1 Causes a slight potential difference.

Next, a bit line pair BIT1, XBIT1
Is amplified by the sense amplifier drive signals SAN and SAP connected to the sense amplifier 4 to perform a read operation.

The sense amplifier drive signals SAN, S
The operation timing of the AP will be described. As shown in FIG. 3A, first, the first sense amplifier drive signal generation circuit 30 is activated by the signal SEN1, and at the same time, the second sense amplifier drive signal generation circuit 31 is activated by the signal SEP1. N with large current supply capacity
The activation of the channel transistor 9 drives the sense amplifier drive signal SAN of the N-channel sense transistors 5 and 6 in the sense amplifier 4, and the activation of the P-channel transistor 15 having a small current supply capability activates the sense amplifier 4 The sense amplifier drive signal SAP of the P-channel sense transistors 7 and 8 is driven. As a result, the potential of the low-level bit line is rapidly dropped by the N-channel sense transistors 5 and 6, and the potential of the high-level bit line is not dropped by driving the P-channel transistor 15 having a small current supply capability. So that it is kept.

Thereafter, the P-channel transistor 10 of the third sense amplifier drive signal generating circuit 32 having a large current supply capability is operated by the drive signal SEP2 to sense the P-channel sense transistors 7 and 8 in the sense amplifier 4. Drive the amplifier drive signal SAP,
The potential of the bit line on the high level side is rapidly increased.

According to the operation timing described above, the potential of the high-level bit line drops during the initial amplification due to the activation of the first sense amplifier drive signal generation circuit 30 and the second sense amplifier drive signal generation circuit 31. Therefore, the potential difference between the pair of bit lines also increases, and when the third sense amplifier drive signal generation circuit 32 is activated, the potential of the bit line on the high level side rises at high speed. , It is possible to perform the amplification operation at high speed.

Next, the P-channel transistor 15 of the second sense amplifier drive signal generating circuit 31 having a small current supply capability will be described.

In this embodiment, a P-channel transistor 15 having a small current supply capability is connected to a word line lining region (in order to reduce the resistance value of the word line, a polysilicon line and a metal line forming a gate are connected in parallel to a memory cell array. Area where several or more connections are made). By arranging in the word line lining region, the P-channel transistor 15 can be added without changing the chip area, and by dispersing and arranging near the sense amplifier 4, the resistance of the signal line of the sense amplifier drive signal SAP can be reduced. Therefore, there is an effect that the potential of the signal SAP is prevented from fluctuating and the potential of the bit line on the high level side is held.

Next, the relationship between the P-channel transistor 15 having a small current supply capability and the P-channel transistor 10 having a large current supply capability will be described.

If the current supply capability of the P-channel transistor 15 having a small current supply capability is too small, the potential of the bit line cannot be maintained. On the other hand, if the current supply capability is too large, a through current flows between the power supply and the ground. The current consumption increases. Accordingly, when the transistor size of the P-channel transistor 15 having a small current supply capability is A and the transistor size of the P-channel transistor 10 having a large current supply capability is B, a through current does not flow while maintaining the potential of the bit line on the high level side. To do so,
It is preferable to have a relationship of (1/20) B ≦ A ≦ (1/2) B. In this embodiment, A = (1/11) B.

The data of the bit line pair amplified by the sense amplifier 4 is transferred to the data line pair DA1 and XDA1 when the column selection signal Y1 goes high, and is amplified by the read amplifier 13. At this time, the column selection signal Y1 goes high when the control signal GON changes from a low level to a high level, and the bit line pair and the data line pair are connected. Thereafter, when the control signal GOFF synchronized with the amplification operation start signal of the read amplifier 13 becomes high level, the column selection signal Y1 becomes low level, and the bit line pair and the data line pair are disconnected. With this configuration, in this embodiment, when reading data, the bit line and the data line are disconnected in synchronization with the time when the read amplifier starts amplifying the data line, so that the load on the sense amplifier is only the bit line. The driving load of the sense amplifier 4 at the time of data reading is greatly reduced as compared with the case where the bit line and the data line are connected as a load as in the related art.

The case where the circuit shown in FIG. 2A is connected to the data line as the data line pull-up circuit 16 will be described. As shown in FIG. 4, when reading data,
By setting the control signal PUG to a low level, the P-channel transistors 20 and 21 are activated, a power supply voltage is supplied to the data line pair, and the potential amplitude of the data line pair is reduced to a potential difference required for data amplification of the read amplifier 13. Keep it.
Therefore, the subsequent precharge operation of the data line pair can be speeded up.

The case where the circuit shown in FIG. 2B is connected as the data line pull-up circuit 16 will be described.
When the amplification of the data line is started and the low-level voltage becomes equal to or lower than (power supply voltage-threshold voltage of N-channel transistors 22 and 23), the low-level N-channel transistor 22 or 23 is activated. Then, a constant voltage which is a potential of (power supply voltage-threshold voltage of N-channel transistors 22 and 23) is supplied to the data line, and the potential amplitude of the data line pair is kept at a potential difference required for data amplification of the read amplifier 13. deep. Therefore, the speed of the precharge operation of the data line pair can be increased.

Next, the case where the data write sense amplifier 17 composed of only the N-channel transistors 24, 25 and 26 is connected to the data line will be described. As shown in FIG. 4, at the time of writing data, the control signal PUG is set to the high level to disconnect the power supply from the data lines DA1 and XDA1, and the control signal SAB is set to the high level.
The SAB1 is connected to the ground, and the data write sense amplifier 17 is driven. With this configuration, the potential of the data line on the low level side can be dropped at a high speed, the operation of amplifying the data line is accelerated, and the operation of writing to the memory cell 3 is accelerated.

Although the present embodiment has been described using the P-channel transistor 15 having a small current supply capability, the same effect can be obtained by using a high load resistance instead.

[0052]

As described above, according to the first and third aspects of the present invention, the instantaneous current during the operation of the sense amplifier is suppressed by adjusting the operation timing of the sense amplifier drive signal, and the potential of the bit line is reduced. Can be speeded up.

According to the second aspect of the present invention, since the word line lining area between the memory cell blocks is used, it is possible to suppress an increase in the chip area, and to change the potential of the sense amplifier drive signal SAP. by suppressing, can in holding the potential of the high-level side bit line constant
You.

As described above , a semiconductor memory device capable of high-speed operation at low voltage operation can be provided, and the effect is large.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing an example of an internal configuration of a data line pull-up circuit.

FIG. 3 is a timing chart of a sensing operation in the present invention.

FIG. 4 is a timing chart of a control signal according to the present invention.

FIG. 5 is a block diagram of a conventional semiconductor memory device.

FIG. 6 is a timing chart of a sensing operation when an N-channel transistor is driven first under a normal power supply voltage and a low power supply voltage in a conventional circuit.

FIG. 7 is a timing chart of a sensing operation when a P-channel transistor is driven first under a normal power supply voltage and a low power supply voltage in a conventional circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Word line 2 N-channel transistor 3 Memory cell 4 Sense amplifier 9 N-channel transistor with large current supply capability 10 P-channel transistor with large current supply capability 15 P-channel transistor with small current supply capability 16 Data line pull-up circuit 17 For data writing Sense amplifier BIT1, XBIT1 Bit line DA1, XDA1 Data line 30 First sense amplifier drive signal generation circuit 31 Second sense amplifier drive signal generation circuit 32 Third sense amplifier drive signal generation circuit 35 Control circuit

Continuation of the front page (72) Inventor Wataru Abe 1-1, Sachimachi, Takatsuki-shi, Osaka Inside Matsushita Electronics Corporation (56) References JP-A-60-136993 (JP, A) JP-A-3-16082 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 11/40-11/4099

Claims (3)

(57) [Claims] 1. A first circuit comprising an N-channel sense amplifier group and a P-channel sense amplifier group for amplifying a potential difference between a pair of bit lines, and an N-channel transistor having a large current supply capability for driving the N-channel sense amplifier group.
And a second P-channel transistor having a small current supply capability for driving the P-channel sense amplifier group.
, A third sense amplifier drive signal generation circuit composed of a P-channel transistor having a large current supply capability, and the first and second sense amplifier drive signal generation circuits are activated almost simultaneously. And a control circuit for activating the third sense amplifier drive signal generation circuit after the initial amplification of the potential difference of the bit line. 2. The semiconductor memory device according to claim 1, wherein a part of the transistors constituting the second sense amplifier drive signal generating circuit are distributed in a word line lining area between the memory cell blocks. . 3. The transistor size of the P-channel transistor having a small current supply capability constituting the second sense amplifier drive signal generation circuit is A, and the P-channel transistor having a large current supply capability constituting the third sense amplifier drive signal generation circuit is provided. Assuming that the transistor size of the transistor is B, both sizes A and B are (1/20) B ≦ A ≦ (1/2)
3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device has a relationship of B.