JP3236459B2 - Error handling device in common bus data transfer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for performing data transfer using a common bus, and more particularly, to an apparatus for processing an abnormality that occurs when data transfer is performed while continuously using the common bus. .

[0002]

2. Description of the Related Art In recent years, a database has been developed in an information processing apparatus, and there is an increasing need for an information processing apparatus having a configuration in which a plurality of users access common data. There is a method of accessing a common resource via a bus.

FIG. 14 shows an overall configuration of a conventional system using a common bus. In FIG. 14, common resources 602
, Each of the plurality of common bus access boards 601-1 to 601-N connected to the common bus 603 issues a common bus access request, and performs arbitration so that the user of the common bus does not play. The common bus access board 601 that has obtained the right to use the common bus is
To access the common resource 602 via.

FIG. 15 is a diagram showing a configuration of a conventional common bus access board. Common bus access board 601
Is composed of a processor 604, a bus control unit 605, and a memory 606. The bus control unit 605 also arbitrates access from another common bus access board 601 in response to a common bus access request signal from the processor 604, and transfers data for controlling the data transfer to the common bus 603. A control unit 608 and an abnormality detection unit 609 for detecting an abnormality on the common bus 603
Consists of

FIG. 16 shows a part of the configuration of the transfer control unit 608 and the abnormality detection unit 609. Transfer control unit 60
8 starts the bus transfer when the logical product AND 704 of the access request signal from the processor 604 and the arbitration: win signal from the bus access arbitration unit 607 becomes “1”.
Further, the abnormality detection unit 609 includes a bus access arbitration unit 607.
AND7 of the output of the logical sum OR 701 of the bus occupying signal from the controller and the bus transferring signal from the transfer control unit 608 and the bus abnormality signal generated in the abnormality detecting unit 609
02 is input to a set of flip-flops FF703, and the output of FF703 is output to the processor as an abnormality occurrence signal. The processor 604 includes an abnormality detection unit 609
After the bus abnormality is recognized by the abnormality occurrence signal from the CPU and the abnormality processing is performed, the abnormality occurrence signal is cleared by outputting "1" to the processor abnormality cancellation signal.

FIG. 17 is a timing chart showing the normal end of continuous occupation of the common bus in the related art. This will be described below using numbers to indicate timings described in the timing chart. First, when the processor 604 sets the bus occupation request signal and the access request signal to active “1”, the bus access arbitration unit 607 performs arbitration on the common bus 603 and performs transfer control when the right to use the common bus 603 is acquired. The unit 608 starts the bus transfer. Bus access arbitration unit 60
When a right to use the common bus 603 is acquired, the bus 7 makes the bus exclusive signal active "1". The transfer control unit 6
In the step 08, when the bus exclusive signal becomes active "1", the bus transfer signal becomes active "1" to start the first bus transfer. When the first bus transfer ends, the transfer control unit 608
The bus transfer signal is set to inactive "0", and the transfer end signal is set to active "1".
To the end of transfer. At this time, since the processor 604 performs the bus transfer again, the bus occupation request signal from the processor 604 is held at active “1”. The bus access arbitration unit 607 keeps the bus occupation signal active at “1” and notifies the other common bus access boards 601 that the bus is occupied. The right to use is retained. When recognizing the end of the transfer, the processor 604 sets the access request signal to inactive "0" and ends the first transfer. When the first transfer is completed, the processor 604 prepares the next data, sets the access request signal to active "1", performs bus transfer, and performs the above operation. During this time,
The processor 604 keeps the bus exclusive request signal active “1”. When the access requiring exclusive use of the common bus 603 ends, the processor 604 sets the bus exclusive use request signal to inactive “0”. When the bus exclusive request signal becomes inactive “0”, the bus access arbitration unit 607
Sets the bus exclusive signal to inactive "0" to release the continuous exclusive use of the common bus 603.

FIG. 18 is a timing chart showing a conventional abnormal termination of continuous occupation of a common bus. This will be described below using numbers to indicate timings described in the timing chart. First, when the processor 604 sets the bus occupation request signal and the access request signal to active “1”, the bus access arbitration unit 607 performs arbitration on the common bus 603 and performs transfer control when the right to use the common bus 603 is acquired. The unit 608 starts the bus transfer. Bus access arbitration unit 60
When a right to use the common bus 603 is acquired, the bus 7 makes the bus exclusive signal active "1". The transfer control unit 6
In the step 08, when the bus exclusive signal becomes active "1", the bus transfer signal becomes active "1" to start the first bus transfer. When the bus transfer signal is in the active state “1” and an abnormality occurs on the common bus 603, the abnormality detection unit 609 detects the abnormality and sets the bus abnormality signal to active “1”.
When the bus abnormality signal becomes active “1”,
The bus access arbitration unit 607 sets the bus exclusive signal to inactive “0”, and the transfer control unit 608 releases the bus by setting the bus transfer signal to inactive “0”. The abnormality detection unit 609 sets the abnormality occurrence signal to active “1” to the processor 604, and
Activates the transfer end signal to "1" to notify the processor 604 that an error has occurred on the common bus 603 and the bus transfer has been completed. The processor 604 detects that the abnormality occurrence signal and the transfer end signal become active “1” at the same time, recognizes that an abnormality has occurred on the common bus 603, and performs abnormality processing. The abnormality processing signal becomes active "1" upon detecting that the abnormality occurrence signal and the transfer end signal become active "1" at the same time, and becomes inactive "0" upon completion of the abnormality processing by the processor 604. After terminating the abnormal processing, the processor 604 sets the processor abnormal release signal to active “1”, thereby setting the abnormal occurrence signal to inactive “0”.

FIG. 19 is another example of a conventional timing chart showing an abnormal termination of continuous exclusive use of the common bus. This will be described below using numbers to indicate timings described in the timing chart. After the access to the first common bus 603 is completed,
If an error occurs on the common bus 603 until the next access to the common bus 603 is performed while the bus occupancy signal is in the active “1” state, the abnormality detection unit 609 detects the error and the bus occupation is performed. The middle signal is inactive “0”
Then, the continuous exclusive use of the common bus 603 is released. The abnormality detection unit 609 sets the abnormality occurrence signal to active “1” to notify the processor 604 that an abnormality has occurred on the common bus 603.
Does not recognize the occurrence of an abnormality on the common bus 603 because the bus is not being transferred. This is because the processor 604 detects that both the abnormality occurrence signal from the abnormality detection unit 609 and the transfer end signal from the transfer control unit 608 become active “1” and performs the abnormality processing. The processor 604 sets the access request signal to active “1” for the next access to the common bus 603, so that the bus access arbitration unit 607 arbitrates the common bus 603 again. When the access to the common bus 603 becomes possible, the transfer control unit 608 sets the bus transfer signal to active “1”, and sets the transfer control unit 608 to “1”.
Makes access to the common bus 603 again. When the transfer end signal from the transfer control unit 608 becomes active “1”, the processor 604
03, and recognizes that an abnormality has occurred, and performs abnormality processing.

FIG. 20 is another example of a conventional timing chart showing an abnormal termination of continuous exclusive use of the common bus. This will be described below using numbers to indicate timings described in the timing chart. Immediately after the second access to the common bus 603 ends normally, if an abnormality occurs on the common bus 603, the abnormality detection unit 609 detects the abnormality, sets the bus exclusive signal to inactive "0", and sets the common bus 603 to inactive. To release the continuation of proprietary. After ending the second access to the common bus 603, the processor 604 sets the bus occupation request signal to inactive "0" to end the bus transfer. Abnormality detector 6
09 sets the abnormality occurrence signal to active “1” and notifies the processor 604 that an abnormality has occurred on the common bus 603. However, since the processor 604 is not performing the bus transfer, an abnormality has occurred on the common bus 603. Do not recognize When the processor 604 needs to access the common bus 603, it sets the access request signal to active “1”.
Accordingly, the arbitration of the common bus 603 by the bus access arbitration unit 607 is performed again. However, since the access is performed only once, the bus occupation request signal is kept inactive "0". When the access to the common bus 603 becomes possible, the bus access arbitration unit 607 changes the bus exclusive signal to active “1”, and sets the transfer control unit 60 to “1”.
8 accesses the common bus 603 again. When the transfer end signal from the transfer control unit 608 becomes active “1”, the processor 604
03, and recognizes that an abnormality has occurred, and performs abnormality processing.

[0010]

The above-mentioned prior art has the following problems. The processor 604 validates the status such as address and data for accessing the common bus 603 while the access request signal is active “1”, but performs another processing when the access request signal is inactive “0”. May have done. Therefore, as shown in FIG. 19, the abnormality occurrence signal becomes active “1” between the access requests from the processor 604 (when the access request signal is inactive “0”), so that the abnormality detection unit 609
When trying to retain the status of the processor 604 at the time of occurrence of an abnormality, the status other than when the common bus 603 is accessed is retained. Since this status is used when re-accessing the common bus 603 after the occurrence of an abnormality, it becomes impossible to determine where the processor 604 re-accesses the shared resource 602. When an abnormality occurs on the common bus 603 at the timing shown in FIG. 19, the bus access arbitration unit 607 releases the continuous exclusive use of the common bus 603, but the processor 604 activates the bus exclusive use request signal without recognizing the occurrence of the abnormality. Since the access request signal is set to active “1” with “1”, the bus arbitration unit 607 performs bus arbitration again. The processor 604 recognizes that the second bus transfer is in a state where the bus is occupied continuously from the first bus transfer. However, since the bus occupation has been released once, useless data It may be a transfer. This poses a problem in the case where the width of the data bus between the common bus 603 and the common resource 602 is different, for example, in the case of lock transfer described later. As shown in FIG. 20, the transfer requiring continuous occupation of the bus ends normally, the processor 604 sets the bus occupation request signal to inactive "0", and recognizes the end of the bus occupation transfer. If an error occurs on the common bus 603 before the signal changes from active “1” to inactive “0”, the data transfer that the processor 604 needs to occupy the common bus 603 normally ends normally. However, at the end of the next bus transfer, the occurrence of an abnormality is notified to the processor 604, and the processor 6
No. 04 performs an unusual abnormality process.

According to the present invention, even if an error occurs on the common bus, unnecessary transfer to the common bus and unnecessary notification of the error to the processor are reduced, and an accurate status is notified to the processor. It is an object of the present invention to provide a possible error handling device in a common bus data transfer.

[0012]

Means for Solving the Problems Bus access arbitration means 1
When the processor 101 performs data transfer using the common bus 107, the processor 02 arbitrates with an access request from another processor to acquire the right to use the common bus.

While the bus access arbitration means 102 has acquired the right to use the common bus 107, the transfer control means 103 controls the processor 101 for the common bus 107.
Control of data transfer from the server.

The abnormality occurrence holding means 105 holds that an abnormality has occurred on the common bus 107 while the transfer control means 103 is executing data transfer to the common bus 107. In the first to third embodiments, the flip-flop 305 in FIG. 3 has this function.

The abnormality occurrence notifying means 104 determines whether or not to notify the processor 107 of the occurrence of an abnormality according to the state of the abnormality occurrence holding means 105 when the processor 101 requests access to the common bus 107. In the first to third embodiments, the flip-flop 307 in FIG. 3 has this function. The abnormality occurrence holding means 105 clears the abnormality occurrence holding when the abnormality occurrence notifying means 104 notifies the processor 101 of the abnormality, or when the processor 101 releases the exclusive use of the common bus 107. It is composed of

The status holding means 106 holds the status output to the common bus 107 when the abnormality occurrence notifying means 104 notifies the processor 101 of the occurrence of an abnormality.

The bus access arbitration means 10 described above
2 is that the abnormality occurrence holding means 105 is the common bus 10
7 may be configured to release the exclusive use of the common bus 107 when an abnormality is detected on the common bus 107.

Further, the transfer control means 103 described above, after the abnormality occurrence notifying means 104 notifies the processor 101 of the occurrence of the abnormality,
Until the end of the abnormal processing, the processor 101
In response to a request for access to the common bus 107 from the CPU, only the transfer end notification may be sent to the processor 107 without actually accessing the common bus 107.

[0019]

[0020]

The principle of the present invention will be described below with reference to the block diagram of FIG. When the processor 101 accesses the common resource via the common bus 107 and occupies the common bus 107 exclusively, the processor 101 outputs an access request and a bus occupation request to the bus access arbitration unit 102. The bus access arbitration unit 102 arbitrates with an access request from another processor connected to the common bus 107, and when the right to use the common bus 107 is acquired, access to the common bus 107 is started.

The bus access arbitration means 102 is the common bus 1
When the right to use 07 is acquired, the transfer control means 103 controls data transfer in response to an access request from the processor 101.

Further, the abnormality occurrence holding means 105 monitors the common bus 107, and holds the information when an abnormality occurs. The abnormality occurrence notifying unit 104 notifies the processor 101 of the occurrence of the abnormality when receiving an access request from the processor 101 while the abnormality occurrence holding unit 105 holds the abnormality on the common bus 107, and at the same time, holds the status. The means 106 holds the status (information such as address and data) output to the common bus 107. Therefore, the status holding means 106 always holds the status while the common bus 107 is being accessed, and the correct status is held.

The abnormality occurrence notifying means 104 is
1 from the notification of the abnormality to the processor 101, the transfer control means 103 actually responds to the access request from the
07 is not accessed and only the transfer end notification is sent to the processor 101. Therefore, unnecessary access to the common bus 107 until the end of the abnormal processing is eliminated.

Further, when there is an access request from the processor 101 after the abnormality occurrence holding means 105 has cleared the holding of the abnormality on the common bus 107, the abnormality occurrence notifying means 104 And the status holding means 106 does not hold the status output to the common bus 107.

The reason that the abnormality occurrence holding means 105 clears the holding of the abnormality is that the abnormality occurrence notifying means 104
This is performed when an abnormality is notified to the CPU 101 or when the processor 101 releases the exclusive use of the common bus 107.

[0026]

FIG. 2 is a diagram showing the configuration of a first embodiment of the present invention. The common bus access board 201 includes a processor 202, a bus control unit 203, and a memory 204. Further, the bus control unit 203 arbitrates access from another common bus access board 201 in response to an access request signal to the common bus 208 from the processor 202, and controls data transfer to the common bus 208. A transfer control unit 206 for performing the operation, and an abnormality detection unit 207 for detecting an abnormality on the common bus 208.

FIG. 3 shows a part of the configuration of the transfer control unit 206 and the abnormality detection unit 207. Transfer control unit 206
Is the logical product A of the access request signal from the processor 202, the arbitration from the bus access arbitration unit 205: the winning signal, and the inverted signal of the abnormality occurrence signal from the abnormality detection unit 207.
When the ND 308 becomes "1", the bus transfer is started.

Further, the abnormality detecting unit 207 receives the bus exclusive signal from the bus access arbitrating unit 205 and the transfer control unit 20.
6 and the output of the logical product AND 302 of the output of the logical sum OR 301 with the bus transfer signal and the bus error signal generated in the error detection unit 207 is output to the flip-flop FF30.
5 and the output of the FF 305 is input to the AND 306 as an abnormality holding signal. When the access request signal from the processor 202 becomes active “1” while the abnormality holding signal is active “1”, the flip-flop FF307 is set and the abnormality occurrence signal becomes active “1”.

The processor 202 recognizes the bus abnormality by the abnormality occurrence signal from the abnormality detection section 207, and after performing the abnormality processing, clears the abnormality occurrence signal by outputting "1" to the processor abnormality cancellation signal. .

The differentiating circuit 303 detects a fall of the bus occupancy request signal from the processor 202 and generates a differentiated signal. The inverted signal of the differentiated signal from the differentiating circuit 303 and the abnormality occurrence signal from the FF 307 are input to the OR 304. The output of the OR 304 is input to the reset of the FF 305. Therefore, when the abnormality occurrence signal from the FF 307 becomes active “1” or the bus occupancy request signal from the processor 202 changes from active “1” to inactive “0”, the abnormality holding signal of the FF 305 is cleared.

FIG. 4 is a timing chart showing an abnormal access to the common bus in the first embodiment. Numbers indicating each timing described in the timing chart ~
This will be described below with reference to FIG. First, when the processor 202 sets the bus occupation request signal and the access request signal to active “1”, the bus access arbitration unit 205 performs arbitration on the common bus 208 and performs transfer control when the right to use the common bus 208 is acquired. The unit 206 starts the bus transfer. Bus access arbitration unit 20
5 sets the bus exclusive signal to active "1" when the right to use the common bus 208 is acquired. Also, the transfer control unit 2
In the step 06, when the bus exclusive signal becomes active "1", the bus transfer signal becomes active "1" to start the first bus transfer. When the first bus transfer ends, the transfer control unit 206
The bus transfer signal is set to inactive “0”, and the transfer end signal is set to active “1”, so that the processor 202
To the end of transfer. At this time, since the processor 202 performs the bus transfer again, the bus occupation request signal from the processor 202 is held at the active “1”. The bus access arbitration unit 205 keeps the bus occupation signal active at “1” and notifies the other common bus access boards 201 that the bus is occupied. The right to use is retained. When detecting an abnormality in the common bus 208, the abnormality detection unit 207 sets the bus abnormality signal to active “1”. When the bus abnormality signal becomes active “1”, the bus access arbitration unit 205 releases the common bus 208 by setting the bus exclusive signal to inactive “0”. When the bus abnormality signal becomes active “1”, the bus exclusive signal from the bus access arbitration unit 205 is active “1”, so that the FF 305 is set and the abnormality holding signal becomes active “1”. The processor 202 sets the access request signal to active “1” in order to perform the next bus transfer. Since the abnormality holding signal is active “1”, the FF 307 is set and the abnormality occurrence signal becomes active “1”. When detecting that the abnormality occurrence signal becomes active “1”, the transfer control unit 206 suspends the bus transfer and sets the transfer end signal to active “1”. When the abnormality occurrence signal becomes active “1”, the abnormality detection unit 207 outputs
08 is held. Further, since the abnormality occurrence signal becomes active “1”, the FF 305 is cleared, and the abnormality holding signal becomes inactive “0”. The processor 202 detects that the abnormality occurrence signal and the transfer end signal become active “1” at the same time, recognizes that an abnormality has occurred on the common bus 208, and performs abnormality processing. The abnormality processing signal becomes active "1" upon detecting that the abnormality occurrence signal and the transfer end signal become active "1" at the same time, and becomes inactive "0" upon completion of the abnormality processing by the processor 202. When the processor 202 completes the abnormality processing, the processor 202 sets the processor abnormality release signal to active “1”, thereby making the abnormality occurrence signal inactive “0”.

By the above operation, the abnormality occurrence signal does not become active "1" except at the time of the bus access request from the processor 202. Therefore, the status at the time of occurrence of the abnormality is accurately maintained,
After the abnormal processing is completed, the bus transfer can be resumed by referring to the contents held in the status.

FIG. 5 is a timing chart showing another access abnormality of the common bus in the first embodiment. FIG.
FIG. 5 shows a case where the processor 202 has correctly recognized the occurrence of the abnormality. FIG. 5 shows a case where the processor 202 has failed to recognize the occurrence of the abnormality for some reason. This will be described below using numbers to indicate timings described in the timing chart. The processor 202 sets the access request signal to active “1” in order to perform the second bus transfer. Since the abnormality holding signal is active “1”, the FF 307 is set and the abnormality occurrence signal becomes active “1”. When detecting that the abnormality occurrence signal becomes active “1”, the transfer control unit 206 suspends the bus transfer and sets the transfer end signal to active “1”. The abnormality detection unit 207 holds the status on the common bus 208 when the abnormality occurrence signal becomes active “1”. Further, since the abnormality occurrence signal becomes active “1”, the FF 305 is cleared, and the abnormality holding signal becomes inactive “0”. The abnormality occurrence signal and the transfer end signal become active “1” at the same time. However, if the processor 202 cannot detect the abnormality for some reason, it performs the normal operation without performing the abnormality processing. Since the processor 202 has not recognized the abnormality, it assumes that the second access to the common bus 208 has been normally completed, and sets the bus exclusive request signal to inactive “0”. When an access to the common bus 208 is required, the processor 202 sets the access request signal to active “1”.
To However, the bus access arbitration unit 205 does not arbitrate for the common bus 208 because the abnormality occurrence signal is active “1”, and the transfer control unit 206 does not access the common bus 208 and transfers data to the processor 202. Only the end signal is made active "1".

With the above operation, unless the processor 202 recognizes and clears the occurrence of an abnormality, the transfer control unit 20
6 no longer starts a new bus transfer and the common bus 208
Unnecessary access to is eliminated.

FIG. 6 is a timing chart showing another access abnormality of the common bus in the first embodiment. FIG.
In FIG. 6, the bus error occurs while the processor 202 is occupying the common bus. However, in FIG. 6, the bus error occurs when the processor 202 releases the common bus. Is shown. This will be described below using numbers to indicate timings described in the timing chart. When the processor 202 performs the second bus transfer and ends normally, an error occurs and the bus error signal becomes active “1”. Since the bus exclusive signal from the bus access arbitration unit 205 is still active “1”, the FF 305
Is set, and the abnormality holding signal becomes active “1”. After completing the second bus transfer, the processor 202 sets the bus occupancy request signal to inactive “0” in order to release the common bus 208. The differentiating circuit 303 detects the falling of the bus exclusive request signal, outputs a differentiated signal, and outputs
F305 is reset to make the abnormality holding signal inactive "0". When an access to the common bus 208 is required, the processor 202 sets the access request signal to active “1”.
By doing so, arbitration by the bus access arbitration unit 205 is performed. However, since the abnormality holding signal is already inactive "0", even if the access request signal becomes active "1", the abnormality occurrence signal does not become active "1" and no abnormality processing is performed.

With the above operation, even if an abnormality occurs on the common bus 208 when the processor 202 cancels the bus occupation request, the processor 20 will not operate when the next bus access request is made.
2 is not notified of the occurrence of an abnormality on the common bus 208.

FIG. 7 is a diagram showing the configuration of the second embodiment of the present invention. The common bus access board 401 includes a processor 402, a bus control unit 403, and a memory 404. Further, the bus control unit 403 includes a processor 402
Bus arbitration unit 405 that arbitrates access from another common bus access board 401 in response to a bus access request signal from the common bus 408 to the common bus 408, a transfer control unit 406 that controls data transfer to the common bus 408, and a common bus An abnormality detection unit 407 for detecting an abnormality on 408
Consists of The diagram showing a part of the configuration of the abnormality detection unit and the transfer control unit in FIG. 3 is also used in the second embodiment.

In the second embodiment, lock transfer to the common bus 408 is performed. Lock transfer refers to, for example, the common bus 4
08 is a 32-bit data bus width and the common resource is 6
If the data bus width is 4 bits, data access to the common resource is performed by two accesses to the common bus 408,
This is a transfer method used when data synchronization is required. Once the right to use the common bus 408 is acquired, the transfer is a transfer that exclusively uses the common bus 408 until the lock signal becomes inactive “0”.

FIG. 8 is a timing chart showing normal termination of lock transfer in the second embodiment. This will be described below using numbers to indicate timings described in the timing chart. The processor 402 sets a bus access request signal and a lock transfer signal to active “1” to perform lock transfer. The bus access arbitration unit 405 arbitrates, acquires the right to use, and performs transfer to the common bus 408. Since the lock transfer signal is a bus access request in the active “1” state, the bus access arbitration unit 405 sets the bus exclusive signal to active “1” and occupies the common bus 408. When the transfer to the common bus 408 ends, the transfer control unit 406 sets the transfer end signal to active “1” and notifies the processor 402. The processor 402 sets the transfer end to active “1”.
When the processor 402 recognizes that the bus transfer request is inactive, the bus access request is temporarily set to inactive "0" while the lock transfer signal remains active "1". The processor 402 sets the bus access request signal to active "1" again for the next bus transfer. When the transfer to the common bus 408 is completed, the transfer control unit 406 sets the transfer end signal to active “1” and notifies the processor of the transfer end. The processor 402 recognizes the end of the transfer, and sets the bus access request signal and the lock transfer signal to inactive "0" to end the lock transfer. When recognizing that the lock transfer signal has become inactive “0”, the bus access arbitration unit 405 changes the bus exclusive signal to inactive “0”, and releases the continuous occupancy of the bus.

FIG. 9 is a timing chart showing a bus error during lock transfer in the second embodiment. Numbers indicating each timing described in the timing chart ~
This will be described below with reference to FIG. The processor 402 sets a bus access request signal and a lock transfer signal to active “1” to perform lock transfer. The bus access arbitration unit 405 arbitrates, acquires the right to use, and performs transfer to the common bus 408. When the transfer to the common bus 408 ends, the transfer control unit 406 sets the transfer end signal to active “1” and notifies the processor 402. While the common bus 408 is continuously occupied, the common bus 4
08 when the bus transfer to the common bus 4 is not performed.
When an abnormality occurs on the block 08, the abnormality detection section 407 detects the abnormality and sets the bus abnormality signal to active "1". Also,
Since the bus exclusive signal is active "1" when the bus abnormality signal becomes active "1", the FF 305 is set to make the abnormality holding signal active "1". The bus access arbitration unit 405 sets the bus exclusive signal to inactive “0” when a bus error occurs, and releases the continuous exclusive use of the bus. Since the processor 402 has not yet been notified that an abnormality has occurred on the common bus 408, the processor 402
Sets the bus access request signal to active "1" for the next bus access as in the normal operation. When the bus access request signal becomes active “1”, the FF 307 is set and the abnormality occurrence signal becomes active “1”. The abnormality detection unit 407 holds the status on the common bus 408 when the abnormality occurrence signal becomes active “1”. Further, the transfer control unit 406 sets the transfer end signal to active “1” without performing the bus transfer to the common bus. The processor 402 recognizes the abnormality on the common bus 408 and performs the abnormality processing because the abnormality occurrence signal from the abnormality detection unit 407 and the transfer end signal from the transfer control unit 406 become active “1”.

FIG. 10 is another example of a timing chart showing a bus error during lock transfer in the second embodiment. This will be described below using numbers to indicate timings described in the timing chart. The processor 402 sets a bus access request signal and a lock transfer signal to active “1” to perform lock transfer. The bus access arbitration unit 405 arbitrates, acquires the right to use, and performs transfer to the common bus 408. When the transfer to the common bus 408 ends, the transfer control unit 406 sets the transfer end signal to active “1” and notifies the processor 402. In addition, the processor 402
In order to perform the second bus transfer, the bus access request signal is set to active “1” and the transfer to the common bus 408 is performed. On the common bus 408, since the common bus 408 continues to be used exclusively after the transfer is completed and until the processor 402 sets the lock transfer signal to the inactive “0”, an abnormality occurs on the bus at this time, and a bus abnormality signal is generated. Is active "1"
, The FF 305 is set and the abnormality holding signal becomes active “1”. When the processor 402 sets the lock transfer signal to inactive “0”, the differentiating circuit 303 detects the fall and generates a differentiated signal. The FF 305 is reset by the differential signal from the differentiating circuit 303, and the abnormality holding signal becomes inactive "0". When the processor 402 needs to access the common bus 408, the processor 402 sets the bus access request signal to active “1”. However, since the abnormality holding signal in the abnormality detection unit 407 is already inactive “0”, The abnormality occurrence signal remains inactive “0” and the processor 402
Is not notified, and the normal access to the common bus 408 is performed.

FIG. 11 is a diagram showing the configuration of the third embodiment of the present invention. The common bus access board 501 includes a processor 502, a bus control unit 503, and a memory 504. Further, the bus control unit 503 includes the processor 50.
A bus access arbitration unit 505 that arbitrates access from another common bus access board 501 in response to a bus access request signal from the second common bus 508 to the common bus 508, a common bus 508
A transfer control unit 506 for controlling data transfer to the CPU, and an abnormality detecting unit 50 for detecting an abnormality on the common bus 508.
7 is comprised. The diagram showing a part of the configuration of the abnormality detection unit and the transfer control unit in FIG. 3 is also used in the third embodiment.

In the third embodiment, sequential transfer to the common bus 508 is performed. Sequential transfer is a transfer method used to transfer a plurality of data at high speed over a common bus. Once the right to use the common bus 508 is acquired, the common transfer is performed until the last data signal from the processor 502 becomes active “1”. It has a bus 508 exclusively.

FIG. 12 is a timing chart showing the normal end of sequential transfer in the third embodiment. This will be described below using numbers to indicate timings described in the timing chart. The processor 502 is connected to the common bus access board 50
1, the first data to be transferred from the memory 504 to the common bus 508 is read. The processor 502 sets the bus access request signal to active “1” in order to store the first data in the common resource by sequential transfer. The bus access arbitration unit 505 arbitrates, acquires the right to use, and starts transfer to the common bus 508. Since the last data signal is a bus access request in the inactive "0" state, the bus access arbitration unit 505 sets the bus exclusive signal to active "1" to occupy the common bus 508, and sets the bus transfer signal to "active". 1 ". The transfer control unit 506 sets the memory write signal to active “1” for the common resource and stores data.
When the data storage is completed, the access completion signal from the common resource becomes active “1”. The transfer control unit 506 includes:
When the access completion signal becomes active "1", the bus transfer signal is made inactive "0". The transfer control unit 506 sets the transfer end signal to active “1” and notifies the processor 502 that the data transfer has ended. The processor 502 sets the bus access request signal to inactive “0” and reads the next data to be transferred from the memory 504. Processor 502 sets the bus access request signal to active “1” again, and repeats the above operation. After reading the last data to be transferred from the memory 504, the processor 502 sets the last data signal to active "1" and sets the bus access request signal to active "1". The transfer control unit 506 performs the last data transfer, the bus access arbitration unit 505 detects the active “1” of the last data signal, and sets the bus exclusive signal to inactive “0” after the end of the data transfer to set the common bus 508 to the inactive state. To release the continuation of proprietary.

FIG. 13 is a timing chart showing the sequential transfer abnormal termination in the third embodiment. This will be described below using numbers to indicate timings described in the timing chart. The processor 502 reads the first data from the memory 504 and transfers it to the common bus 508. The normal sequential transfer operation is repeated. After the second data is transferred to the common bus 508, an error occurs on the common bus, and the bus error signal becomes active "1".
Becomes Since the bus exclusive signal is active "1", the FF 305 is set and the abnormality holding signal becomes active "1". Further, due to the occurrence of the abnormality, the bus access arbitration unit 505 changes the bus exclusive signal to inactive “0”.
And release the continuous occupation of the bus. Since the processor 502 does not recognize that an abnormality has occurred on the common bus 508, the processor 502 sets the bus access request signal to active "1" as in the normal operation. When the bus access request signal becomes active "1", the FF3
07 is set and the abnormality occurrence signal becomes active "1". The abnormality detecting unit 507 holds the status on the common bus 508 when the abnormality occurrence signal becomes active “1”. The transfer control unit 506 sets the transfer end signal to active “1” without performing the bus transfer to the common bus 508. The processor 502 detects that the abnormality occurrence signal from the abnormality detection unit 507 and the transfer end signal from the transfer control unit 506 have become active “1”, recognizes the occurrence of the abnormality, and performs the abnormality processing. In the abnormality processing, the abnormality detection unit 5
The status held in 07 is referred to.

[0046]

According to the present invention, when a bus error occurs in the common bus, the status (address, data, read / write transfer direction, etc.) of the access of the processor to the common bus can be correctly held, and the bus access is retried. Processing can be easily realized.

Until the processor recognizes the occurrence of a bus error on the common bus, no new bus transfer is performed, so that the use efficiency of the common bus is improved. Furthermore, since only a bus error on the required common bus is notified to the processor, unnecessary error processing due to a bus error that does not involve the processor need not be performed, thereby increasing the efficiency of the system and ensuring the processor. Data transfer abnormal processing can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention.

FIG. 2 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 3 is a diagram showing a part of the configuration of an abnormality detection unit and a transfer control unit according to the present invention.

FIG. 4 is a timing chart (part 1) showing a common bus access abnormality in the first embodiment.

FIG. 5 is a timing chart (part 2) showing a common bus access abnormality in the first embodiment.

FIG. 6 is a timing chart (part 3) showing a common bus access abnormality in the first embodiment.

FIG. 7 is a diagram showing a configuration of a second embodiment of the present invention.

FIG. 8 is a timing chart showing normal termination of lock transfer in the second embodiment.

FIG. 9 is a timing chart showing a bus error during lock transfer in the second embodiment.

FIG. 10 is a timing chart showing a bus abnormality after lock transfer is normally completed in the second embodiment.

FIG. 11 is a diagram showing a configuration of a third example of the present invention.

FIG. 12 is a timing chart showing a normal end of sequential transfer in the third embodiment.

FIG. 13 is a timing chart showing a sequential transfer abnormal end in the third embodiment.

FIG. 14 is a diagram showing an overall configuration of a conventional system using a common bus.

FIG. 15 is a diagram showing a configuration of a conventional common bus access board.

FIG. 16 is a diagram showing a part of the configuration of a conventional abnormality detection unit and transfer control unit.

FIG. 17 is a timing chart showing a conventional common bus continuous occupation normal termination.

FIG. 18 is a timing chart (part 1) showing a conventional common bus continuous occupation abnormal termination.

FIG. 19 is a timing chart (part 2) showing a conventional common bus continuous occupation abnormal termination.

FIG. 20 is a timing chart (part 3) showing a conventional common bus continuous occupation abnormal termination.

[Explanation of symbols]

 Reference Signs List 101 processor 102 bus access arbitration means 103 transfer control means 104 abnormality occurrence notification means 105 abnormality occurrence holding means 106 status holding means 107 common bus

Continuation of the front page (72) Inventor Souichi Arai 1-1, Tanabe-Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fuji Electric Co., Ltd. (56) References JP-A-4-257957 (JP, A) JP-A-4- 152448 (JP, A) JP-A-4-271448 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 11/00, 13/00, 13/36

Claims (5)

(57) [Claims] 1. An error occurrence holding means for holding that an error has occurred on the common bus while a processor occupies the common bus and performs data transfer, when the processor requests access to the common bus, anda abnormality occurrence notification means for determining whether to notify the abnormality in said processor the state of the abnormality occurrence holding means, the abnormality occurrence holding means, the abnormality occurrence notification means the
When the processor is notified of an error, or when the processor
When the exclusive use of the common bus is released, the occurrence of
An abnormality processing device for data transfer on a common bus, which is cleared . 2. A bus access arbitration means for arbitrating an access request from another processor and acquiring a right to use a common bus when the processor performs data transfer using a common bus, and said bus access Transfer control means for controlling data transfer from the processor to the common bus while the arbitration means obtains the right to use the common bus, wherein the transfer control means performs data transfer to the common bus, Abnormality occurrence holding means for holding that an error has occurred on a common bus; and determining whether or not to notify the processor of the occurrence of an error based on the state of the error occurrence holding means when the processor requests access to the common bus. An abnormality processing device for data transfer on a common bus, comprising: 3. The transfer control unit according to claim 1, wherein said transfer control unit is configured to send a notification to said common bus from said processor until the processor ends abnormal processing after the abnormality notification unit notifies the processor of the occurrence of the abnormality. 3. An abnormal process in the data transfer of the common bus according to claim 2, wherein, in response to an access request, only the transfer completion notification is sent to the processor without actually accessing the common bus. apparatus. 4. The bus access arbitration means, when the abnormality occurrence holding means detects an abnormality on the common bus,
4. The abnormality processing apparatus according to claim 2, wherein exclusive use of the common bus is released. 5. The apparatus according to claim 1, further comprising: status holding means for holding a status output to said common bus when said abnormality occurrence notifying means notifies said processor of an abnormality occurrence. 5. The abnormality processing device for data transfer of the common bus according to any one of the above-mentioned items.