JP3237082B2 - Method of forming resist pattern - Google Patents
Method of forming resist patternInfo
- Publication number
- JP3237082B2 JP3237082B2 JP01422692A JP1422692A JP3237082B2 JP 3237082 B2 JP3237082 B2 JP 3237082B2 JP 01422692 A JP01422692 A JP 01422692A JP 1422692 A JP1422692 A JP 1422692A JP 3237082 B2 JP3237082 B2 JP 3237082B2
- Authority
- JP
- Japan
- Prior art keywords
- resist
- resist pattern
- forming
- substrate
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Photosensitive Polymer And Photoresist Processing (AREA)
- Drying Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、レジストパターンの形
成方法に関し、特に、例えばリフトオフ法によるFET
のゲート電極作製のためのレジストパターンの形成方法
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a resist pattern, and more particularly to a method of forming a resist pattern by, for example, a lift-off method.
And a method of forming a resist pattern for producing a gate electrode.
【0002】[0002]
【従来の技術】近年、半導体集積回路等の高性能化、高
集積度化への要求は一層増大している。そのため、従来
の紫外線を用いたフォトリソグラフィーに代わって、電
子線、軟X線、イオンビーム等を用いるリソグラフィー
により、超微細なパターン加工技術を確立する努力が払
われている。特に、化合物電界効果型トランジスタの高
周波数化、高性能化には、ゲート長の短縮化が有効であ
り、リフトオフ法により微細ゲート電極を形成してい
る。2. Description of the Related Art In recent years, demands for higher performance and higher integration of semiconductor integrated circuits and the like have been further increased. For this reason, efforts have been made to establish an ultra-fine pattern processing technique by lithography using electron beams, soft X-rays, ion beams, or the like, instead of conventional photolithography using ultraviolet rays. In particular, shortening the gate length is effective for increasing the frequency and improving the performance of the compound field effect transistor, and a fine gate electrode is formed by a lift-off method.
【0003】そのためには、基板20上にレジストを塗
布して、露光、現像後、図2(A)に示すように、断面
が垂直若しくは順テーパー形状のレジストパターン21
を用いることが考えられるが、同図(B)に示すよう
に、そのレジストパターン21にゲート用金属22を蒸
着し、その後、同図(C)に示すように、レジスト21
を溶解除去すると、ゲート電極23端部に不要なバリ2
4ができたり、リフトオフの際に、ゲート電極23自身
が破壊されたりしてしまう。For this purpose, a resist is coated on a substrate 20, exposed and developed, and then, as shown in FIG. 2A, a resist pattern 21 having a vertical or forward tapered cross section.
However, as shown in FIG. 2B, a gate metal 22 is vapor-deposited on the resist pattern 21 and then, as shown in FIG.
Dissolves and removes unnecessary burrs 2 at the end of the gate electrode 23.
4 or the gate electrode 23 itself is destroyed during lift-off.
【0004】このような問題を避けるには、レジスト断
面形状が、図3(E)に示すような逆テーパー形状(又
は、オーバーハング形状)のレジストパターン35を用
いることが必要である。このような逆テーパー形状のレ
ジストパターンを得る従来の1つの方法として、レジス
ト表面をアルカリ処理して、現像液に対して難溶化さ
せ、レジスト内部との現像速度の違いを利用して、所望
のレジスト断面形状を得る方法が提案されている(特開
平3−119720号)。すなわち、図3(A)に示す
ように、基板30上にポジ型レジスト31を塗布し、そ
の表面を、同図(B)に示すように、アルカリ処理して
表面難溶化層32を形成し、次いで、同図(C)に示す
ように、ホットプレート33上に載せてレジスト31を
ベーク処理し、その後、同図(D)のように、所望のパ
ターンを光、電子線、イオン線、X線等34を用いて露
光し、次に、同図(E)に示すように、現像液で現像す
ることにより、逆テーパー形状のレジストパターン35
を得ることができる。その後、同図(F)に示すよう
に、レジストパターン35上にゲート用金属36を蒸着
又はスパッタし、次に、同図(G)に示すように、レジ
スト35を溶解除去すると、ゲート電極36が形成され
る。この場合、レジストパターン35の開口断面が逆テ
ーパー形状であるので、出来上がったゲート電極36端
部にはバリ等がなく、また、リフトオフによりゲート電
極36の下部が剥がされないので、ゲート電極36が破
壊されることはない。In order to avoid such a problem, it is necessary to use a resist pattern 35 having an inverse tapered shape (or overhang shape) as shown in FIG. As one conventional method for obtaining such an inversely tapered resist pattern, a resist surface is alkali-treated to make it hardly soluble in a developing solution, and a desired developing rate is obtained by utilizing a difference in developing speed from the inside of the resist. A method for obtaining a resist cross-sectional shape has been proposed (JP-A-3-119720). That is, as shown in FIG. 3A, a positive resist 31 is applied on a substrate 30, and the surface thereof is subjected to an alkali treatment to form a surface hardly-solubilized layer 32 as shown in FIG. 3B. Then, as shown in FIG. 3C, the resist 31 is baked on a hot plate 33, and then, as shown in FIG. 3D, a desired pattern is formed by light, electron beam, ion beam, Exposure is performed using X-rays or the like 34, and then, as shown in FIG.
Can be obtained. Thereafter, as shown in FIG. 3F, a gate metal 36 is deposited or sputtered on the resist pattern 35, and then, as shown in FIG. Is formed. In this case, since the opening cross section of the resist pattern 35 has an inversely tapered shape, there is no burr or the like at the end of the completed gate electrode 36, and since the lower portion of the gate electrode 36 is not peeled off by lift-off, the gate electrode 36 is broken. It will not be done.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、この従
来のレジスト表面を難溶化させる方法は、レジスト表面
を難溶化するための余分な工程が必要となる。However, this conventional method for making the resist surface hardly soluble requires an extra step for making the resist surface hardly soluble.
【0006】本発明はこのような状況に鑑みてなされた
ものであり、その目的は、ベーク処理に工夫を施すだけ
で、余分な工程を用いることなく、開口断面が逆テーパ
ー形状のリフトオフ法による微細ゲート電極作製用のレ
ジストパターンを形成する方法を提供することにある。The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a lift-off method in which the opening cross section is inversely tapered without using any extra steps by merely devising a baking process. An object of the present invention is to provide a method for forming a resist pattern for producing a fine gate electrode.
【0007】[0007]
【課題を解決するための手段】一般に、基板上にレジス
ト層を形成する場合、スピンナー等でレジストを塗布し
た後に、基板とレジストとの密着性を向上させるため、
及び、レジスト中の不溶な溶剤を除去するため等の目的
でベーク処理を行うが、ポジ型レジストの場合、ベーク
温度によって感度が変化すること、具体的には、高温で
ベークしたものは低温でベークしたものより低感度にな
ることが知られている。In general, when a resist layer is formed on a substrate, a resist is applied using a spinner or the like, and then the adhesion between the substrate and the resist is improved.
And, baking is performed for the purpose of removing insoluble solvents in the resist, but in the case of a positive resist, the sensitivity varies depending on the baking temperature, specifically, those baked at a high temperature are reduced at a low temperature. It is known that the sensitivity is lower than the baked one.
【0008】本発明は、ポジ型レジストのこの特性を活
用したものであって、レジストパターン形成工程におい
て、基板上にレジストを塗布した後にベークを行う際、
基板を温度制御可能なプレート上に載せ、レジスト面側
からプレート温度よりも高温なガス又は熱線を当てるこ
とにより、レジスト厚内で温度差を作り、それによる感
度差から、逆テーパー形状を得ることが可能になること
を見出して完成したものである。The present invention utilizes this characteristic of a positive type resist. In a resist pattern forming step, when baking is performed after applying a resist on a substrate,
A substrate is placed on a temperature-controllable plate, and a gas or heat ray higher than the plate temperature is applied from the resist surface side to create a temperature difference within the resist thickness, and obtain a reverse tapered shape from the sensitivity difference due to it. It was completed after finding that it became possible.
【0009】すなわち、本発明のレジストパターンの形
成方法は、開口断面が表面側へ向かって窄む逆テーパー
形状を有するレジストパターンであって、リフトオフ法
による微細ゲート電極作製用のレジストパターンの形成
方法において、基板上にレジストを塗布して、露光前に
ベーク処理する際に、その基板を温度制御可能なプレー
ト上に載せ、レジスト表面側から温風又は熱線を当て、
基板側から相対的に冷却して、レジスト厚内に温度差を
作ってベーク処理して、レジスト厚内に感度差を形成す
ることにより、露光、現像後の開口断面が逆テーパー形
状を有するレジストパターンを形成することを特徴とす
る方法である。That is, the method of forming a resist pattern according to the present invention is a resist pattern having an inverted tapered shape in which the cross section of the opening narrows toward the surface, and the method of forming a resist pattern for producing a fine gate electrode by a lift-off method. In, apply a resist on the substrate, when baking before exposure, put the substrate on a temperature-controllable plate, and apply hot air or heat rays from the resist surface side,
By cooling relatively from the substrate side, making a temperature difference within the resist thickness and baking to form a sensitivity difference within the resist thickness, the resist has a reverse tapered opening cross section after exposure and development. The method is characterized by forming a pattern.
【0010】この場合、レジストはポジ型レジストであ
ることが望ましい。In this case, the resist is preferably a positive resist.
【0011】[0011]
【作用】本発明においては、露光前にベーク処理する際
に、その基板を温度制御可能なプレート上に載せ、レジ
スト表面側から温風又は熱線を当て、基板側から相対的
に冷却して、レジスト厚内に温度差を作ってベーク処理
して、レジスト厚内に感度差を形成することにより、露
光、現像後の開口断面が逆テーパー形状を有するレジス
トパターンを形成するので、レジストパターン形成工程
で必ず行われるベーク処理工程に工夫を施すだけの簡単
なプロセスで、表面難溶化のような余分で複雑な工程を
増やさずに、微細ゲート電極のリフトオフ形成に最適な
逆テーパー形状のレジストパターンを確実に形成するこ
とができる。In the present invention, when baking before exposure, the substrate is placed on a temperature-controllable plate, hot air or heat rays are applied from the resist surface side, and relatively cooled from the substrate side. By forming a temperature difference within the resist thickness and baking to form a sensitivity difference within the resist thickness, a resist pattern having a reverse tapered opening cross section after exposure and development is formed. This is a simple process that simply devises the baking process that is always performed in the process, without adding extra and complicated processes such as surface insolubilization, and forming an inverse tapered resist pattern that is optimal for lift-off formation of fine gate electrodes. It can be formed reliably.
【0012】[0012]
【実施例】以下、本発明のレジストパターンの形成方法
の1実施例を図面を参照しつつ説明する。図1は本発明
によるレジストパターン形成方法の工程を示す断面図で
ある。まず、図1(A)に示すように、GaAs基板2
の上にポリメチルメタアクリレートを主成分とするポジ
型レジスト1(商品名;東京応化(株)製 OEBR−
1000)をスピンナー塗布し、同図(B)に示すよう
に、レジスト膜1厚内で温度差ができるように、レジス
ト面に150℃の熱風又は熱線3を当て、基板2底面は
110℃のクールプレート4にて冷却する。この処理を
30分間行い、図示のように、相対的にレジスト膜1露
出側に低感度部5、深部側に高感度部6を形成する(感
度差形成)。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a method for forming a resist pattern according to the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing steps of a method for forming a resist pattern according to the present invention. First, as shown in FIG.
Positive resist 1 containing polymethyl methacrylate as a main component (trade name; OEBR- manufactured by Tokyo Ohka Co., Ltd.)
1000) is applied by a spinner, and hot air or a hot wire 3 of 150 ° C. is applied to the resist surface so that a temperature difference occurs within the thickness of the resist film 1 as shown in FIG. Cool on the cool plate 4. This process is performed for 30 minutes, and as shown in the figure, a low sensitivity portion 5 is formed relatively on the exposed side of the resist film 1 and a high sensitivity portion 6 is formed relatively on the deep side (sensitivity difference formation).
【0013】次に、同図(C)に示すように、電子線描
画装置の電子線、又は、光、イオン線、X線7を用い
て、レジスト膜1に対し、0.25μm幅のゲートパタ
ーンを形成するためのレジストパターンを描画する。Next, as shown in FIG. 1C, a gate having a width of 0.25 μm is formed on the resist film 1 by using an electron beam of an electron beam lithography apparatus, or light, ion beam, or X-ray 7. A resist pattern for forming a pattern is drawn.
【0014】電子線等による描画の終了後、メチルイソ
ブチルケトンとイソプロピルアルコールとの混合比を
1:3とする23℃程度の現像液に、基板2ごとレジス
ト膜1を1分間浸漬して現像した後、23℃程度のイソ
プロピルアルコールからなるリンス液に基板2ごと30
秒程度浸漬洗浄することによって、レジスト膜1厚内の
感度差により、同図(D)に示すような逆テーパー状断
面のレジストパターン8が得られる。After the completion of drawing with an electron beam or the like, the resist film 1 together with the substrate 2 was immersed in a developing solution at a mixing ratio of methyl isobutyl ketone and isopropyl alcohol of 1: 3 at about 23 ° C. for 1 minute and developed. Thereafter, the substrate 2 together with a rinse solution of isopropyl alcohol at about 23 ° C.
By immersion cleaning for about a second, a resist pattern 8 having an inversely tapered cross section as shown in FIG.
【0015】このようにして得られたレジストパターン
8をマスクにして、スパッタ法によりアルミニウムを堆
積させて、同図(E)に示すようなゲート電極用金属膜
9を成膜した後、アセトンを用いてレジスト膜8を溶解
除去し、同図(F)に示すようなゲート長0.25μm
のAlゲート電極10を形成した。Using the resist pattern 8 thus obtained as a mask, aluminum is deposited by sputtering to form a gate electrode metal film 9 as shown in FIG. Then, the resist film 8 is dissolved and removed, and the gate length is 0.25 μm as shown in FIG.
Al gate electrode 10 was formed.
【0016】得られたAlゲート電極10は、端部にバ
リ等がなく綺麗で、破壊もされていなかった。The obtained Al gate electrode 10 was clean with no burrs or the like at the ends and was not broken.
【0017】以上、本発明のレジストパターンの形成方
法を実施例に基づいて説明してきたが、本発明はこれら
実施例に限定されず種々の変形が可能である。Although the method of forming a resist pattern according to the present invention has been described based on the embodiments, the present invention is not limited to these embodiments, and various modifications are possible.
【0018】[0018]
【発明の効果】以上の説明から明らかなように、本発明
のレジストパターンの形成方法によれば、露光前にベー
ク処理する際に、その基板を温度制御可能なプレート上
に載せ、レジスト表面側から温風又は熱線を当て、基板
側から相対的に冷却して、レジスト厚内に温度差を作っ
てベーク処理して、レジスト厚内に感度差を形成するこ
とにより、露光、現像後の開口断面が逆テーパー形状を
有するレジストパターンを形成するので、レジストパタ
ーン形成工程で必ず行われるベーク処理工程に工夫を施
すだけの簡単なプロセスで、表面難溶化のような余分で
複雑な工程を増やさずに、微細ゲート電極のリフトオフ
形成に最適な逆テーパー形状のレジストパターンを確実
に形成することができる。As is apparent from the above description, according to the method for forming a resist pattern of the present invention, when baking is performed before exposure, the substrate is placed on a temperature-controllable plate, and Exposure after exposure and development by applying hot air or heat rays from the substrate and relatively cooling from the substrate side, creating a temperature difference within the resist thickness and baking to form a sensitivity difference within the resist thickness Since a resist pattern with a reverse-tapered cross section is formed, it is a simple process that only devises the baking process that is always performed in the resist pattern forming process, and does not increase extra and complicated processes such as surface insolubilization. In addition, it is possible to reliably form a resist pattern having an inverse tapered shape that is optimal for lift-off formation of a fine gate electrode.
【図1】本発明のレジストパターン形成方法の1実施例
の工程を示す断面図である。FIG. 1 is a cross-sectional view showing the steps of one embodiment of a method for forming a resist pattern according to the present invention.
【図2】従来の順テーパー形状でのリフトオフ工程を示
す断面図である。FIG. 2 is a sectional view showing a conventional lift-off process in a forward tapered shape.
【図3】従来の断面逆テーパー形状レジストパターン形
成方法の工程を示す断面図である。FIG. 3 is a cross-sectional view showing steps of a conventional method for forming a resist pattern having a reverse tapered cross section.
1…ポジ型レジスト 2…基板 3…熱風又は熱線 4…クールプレート 5…低感度部 6…高感度部 7…電子線、光、イオン線、X線 8…レジストパターン 9…ゲート電極用金属膜 10…ゲート電極 DESCRIPTION OF SYMBOLS 1 ... Positive resist 2 ... Substrate 3 ... Hot air or heat ray 4 ... Cool plate 5 ... Low sensitivity part 6 ... High sensitivity part 7 ... Electron beam, light, ion beam, X-ray 8 ... Resist pattern 9 ... Metal film for gate electrode 10 ... Gate electrode
Claims (2)
パー形状を有するレジストパターンであって、リフトオ
フ法による微細ゲート電極作製用のレジストパターンの
形成方法において、基板上にレジストを塗布して、露光
前にベーク処理する際に、その基板を温度制御可能なプ
レート上に載せ、レジスト表面側から温風又は熱線を当
て、基板側から相対的に冷却して、レジスト厚内に温度
差を作ってベーク処理して、レジスト厚内に感度差を形
成することにより、露光、現像後の開口断面が逆テーパ
ー形状を有するレジストパターンを形成することを特徴
とするレジストパターンの形成方法。In a method of forming a resist pattern for forming a fine gate electrode by a lift-off method, a resist is applied to a substrate, the resist pattern having an inverse tapered shape in which an opening cross section narrows toward a surface side. When baking before exposure, the substrate can be temperature controlled.
Put on a rate , apply warm air or heat rays from the resist surface side, cool relatively from the substrate side, make a temperature difference within the resist thickness and bake to form a sensitivity difference within the resist thickness Forming a resist pattern having a reverse tapered cross section of the opening after exposure and development.
特徴とする請求項1記載のレジストパターンの形成方
法。2. The method according to claim 1, wherein the resist is a positive resist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01422692A JP3237082B2 (en) | 1992-01-29 | 1992-01-29 | Method of forming resist pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01422692A JP3237082B2 (en) | 1992-01-29 | 1992-01-29 | Method of forming resist pattern |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0661139A JPH0661139A (en) | 1994-03-04 |
| JP3237082B2 true JP3237082B2 (en) | 2001-12-10 |
Family
ID=11855155
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01422692A Expired - Fee Related JP3237082B2 (en) | 1992-01-29 | 1992-01-29 | Method of forming resist pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3237082B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8338072B2 (en) | 2006-09-26 | 2012-12-25 | Fujitsu Limited | Resist composition, resist pattern forming process, and method for manufacturing semiconductor device |
| US8748077B2 (en) | 2011-03-11 | 2014-06-10 | Fujitsu Limited | Resist pattern improving material, method for forming resist pattern, method for producing semiconductor device, and semiconductor device |
| US8795949B2 (en) | 2010-12-16 | 2014-08-05 | Fujitsu Limited | Resist pattern improving material, method for forming resist pattern, and method for producing semiconductor device |
| US8980535B2 (en) | 2010-10-22 | 2015-03-17 | Fujitsu Limited | Resist pattern improving material, method for forming resist pattern, and method for producing semiconductor device |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01138547U (en) * | 1988-03-09 | 1989-09-21 | ||
| JP2007041099A (en) * | 2005-08-01 | 2007-02-15 | Toppan Printing Co Ltd | Ink-discharge printed matter and method for producing the same |
| CN112864004A (en) * | 2021-01-04 | 2021-05-28 | 湘潭大学 | Method for solving burrs and photoresist removal residues in film coating process of photoetching process |
-
1992
- 1992-01-29 JP JP01422692A patent/JP3237082B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8338072B2 (en) | 2006-09-26 | 2012-12-25 | Fujitsu Limited | Resist composition, resist pattern forming process, and method for manufacturing semiconductor device |
| US8980535B2 (en) | 2010-10-22 | 2015-03-17 | Fujitsu Limited | Resist pattern improving material, method for forming resist pattern, and method for producing semiconductor device |
| US8795949B2 (en) | 2010-12-16 | 2014-08-05 | Fujitsu Limited | Resist pattern improving material, method for forming resist pattern, and method for producing semiconductor device |
| US8748077B2 (en) | 2011-03-11 | 2014-06-10 | Fujitsu Limited | Resist pattern improving material, method for forming resist pattern, method for producing semiconductor device, and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0661139A (en) | 1994-03-04 |
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