JP3237346B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a complete CMOS static random access memory (SRAM) in which a load transistor is formed directly on a semiconductor substrate together with a driving transistor and a selection transistor. About.

[0002]

2. Description of the Related Art A P-channel type thin film transistor (TF) is used as a memory cell of a 4 Mb or 16 Mb SRAM.
An SRAM memory cell using T) as a load transistor has been developed. The memory cell for the TFT load type SRAM consumes less power during standby and is excellent in stability as compared with the memory for the high resistance load type SRAM. In addition, it is excellent in high integration as compared with a bulk CMOS type SRAM memory cell having a bulk structure in which a load transistor is formed on a semiconductor substrate.

However, a memory cell for a TFT load type SRAM has a problem that its manufacturing process is complicated. Therefore, a full CMOS type SRA having a bulk structure
The M memory cell is being reviewed. Complete C of bulk structure
The MOS SRAM memory has a simpler manufacturing process, can obtain a higher current during operation, and is superior in memory stability, as compared with the TFT load SRAM memory.

FIG. 8 shows an equivalent circuit of a memory cell for a complete CMOS type SRAM having a bulk structure. As shown in FIG.
This memory cell has a pair of drive transistors DQ1 and DQ2 forming a flip-flop circuit, select transistors SQ3 and SQ4 for selecting a memory cell, and load transistors LQ5 and LQ6. Select transistor SQ
3, SQ4 is determined according to the gate voltage generated on the word line W.
With the transistor turned on, the driving transistor DQ
1, information stored in the flip-flop circuit constituted by DQ2 is transmitted to the bit line b and the inverted bit line b '.

In a bulk-structured complete CMOS SRAM memory cell, a transistor and wiring layout pattern that can efficiently reduce the size of the memory cell are important. Recently, SRAM memory cells MC having the layout pattern shown in FIG. 9 have been developed. In this memory cell MC, impurity diffusion layers 4 are arranged in two rows for each cell, and four rows of gate electrodes 2 are arranged in a direction perpendicular to the impurity diffusion layers 4.

Two outer rows of gate electrodes 2 out of the four rows of gate electrodes 2 become word lines W 1 and W 2, and a selection transistor S is provided at the intersection of these word lines and impurity diffusion layer 4.
Q3 and SQ4 are formed. Load transistors LQ5 and LQ6 and drive transistors DQ1 and DQ2 are formed at the intersection of the central two rows of gate electrodes 2 and 2 and the impurity diffusion layer 4. The load transistors LQ5 and LQ6 are formed on a P-type impurity diffusion layer and select transistors SQ3 and LQ6.
SQ4 and drive transistors DQ1 and DQ2 are formed on the N-type impurity diffusion layer.

These transistors are connected by a first intermediate conductive layer 6, a second intermediate conductive layer 8, and a metal wiring layer 10 laminated thereon so as to constitute the circuit shown in FIG. Metal wiring layer 1 composed of aluminum wiring layer etc.
0 indicates the bit line b, the inverted bit line b ′ and the power supply line V _SS
Becomes

In the conventional example shown in FIG. 9, power supply line V _SS is shared with adjacent memory cells, so that one memory cell MC
As a result, 2.5 rows of metal wiring layers 10 pass.

[0009]

In the memory cell having such a layout, the select transistors SQ3 and SQ4 and the drive transistors DQ1 and DQ are provided on the N-type impurity diffusion layer 4.
Since four Q2s are arranged in a row, the memory cells MC are short in the horizontal direction and long in the vertical direction. The metal wiring layers 10 are wired extending in the vertical direction at a pitch of 2.5 columns for each memory cell MC.

[0010] Therefore, in the layout pattern shown in FIG. 9, the pitch width and the wiring width between the metal wiring layers 10 become narrow, and the parasitic capacitance of the bit line and the bit line resistance increase. Further, when the pitch between the metal wiring layers 10 is narrow, there is a problem that the reliability of the wiring is reduced and the wiring processing becomes difficult.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has a bulk structure having reduced bit line parasitic capacitance and resistance, reduced access time, improved wiring reliability, and simplified wiring processing. An object of the present invention is to provide a memory cell for a complete CMOS type SRAM.

[0012]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises, for each memory cell, three rows of impurity diffusion layers formed on a semiconductor substrate;
On these three rows of impurity diffusion layers, three rows of gate electrode layers formed so as to be substantially orthogonal to the impurity diffusion layers via a gate insulating layer, The central gate electrode located at the center of the memory cell corresponds to the word line of the memory cell, and at the intersection of the central gate electrode and the impurity diffusion layer, a selection transistor is formed. A driving transistor and a load transistor are formed at intersections of the other two rows of side gate electrodes and the impurity diffusion layer, respectively.

The first row of one of the three rows of impurity diffusion layers
The impurity diffusion layer is a P-type impurity diffusion layer, the other two rows of the second and third impurity diffusion layers are N-type impurity diffusion layers,
Moreover, it is preferable that the P-type impurity diffusion layer is separated at an intersection with the central gate electrode.

It is preferable that the second and third impurity diffusion layers are disposed closer to each other than the separation distance from the first impurity diffusion layer in the memory cell and at symmetrical positions. It is preferable that a buried diffusion layer located below the gate electrode is formed at a part of the intersection between the second impurity diffusion layer or the third impurity diffusion layer and the two rows of side gate electrodes.

The pair of load transistors, the pair of drive transistors, and the pair of select transistors are connected to form a memory cell of a static random access memory by a multilayer wiring layer laminated on the gate electrode. I have.

[0016]

In the semiconductor memory device of the present invention, three rows of gate electrodes are arranged so as to be substantially orthogonal to the three rows of impurity diffusion layers, and the layout pattern is such that the central gate electrode is a word line. Since the cells are horizontally elongated, the pitch interval and the wiring width of the metal wiring layers arranged substantially perpendicular to the word lines can be increased without increasing the cell area of the memory cells. As a result, the parasitic capacitance and resistance of the bit line formed of the metal wiring layer can be significantly reduced, and the access speed to the memory cell is improved.

Further, since the wiring pitch between the metal wiring layers can be increased, the reliability of the wiring is improved and
Wiring processing becomes easy.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to the present invention will be described below in detail based on an embodiment shown in the drawings. FIG. 1 is a plan view showing a layout pattern of an impurity diffusion layer in an SRAM memory cell according to one embodiment of the present invention. FIG. 2 is a plan view showing a gate electrode layout pattern in the memory cell according to the embodiment. FIG. 4 is a plan view showing a layout pattern of a first intermediate conductive layer in the memory cell according to the embodiment. FIG.
FIG. 5 is a plan view showing a layout pattern of an intermediate conductive layer, FIG. 5 is a plan view showing a layout pattern of a metal wiring layer in the memory cell according to the embodiment, and FIG. 6 is a cross-sectional view of main parts along line VI-VI shown in FIG. FIG. 7 is a cross-sectional view of a main part along the line VII-VII shown in FIG. 2, and FIG. 8 is an equivalent circuit diagram of the SRAM memory cell.

As shown in FIG. 1 to FIG.
The RAM memory cell MC includes load transistors LQ5 and LQ6 and a selection transistor SQ on a semiconductor substrate 11.
3, SQ4 and drive transistors DQ1 and DQ2 are directly formed in a bulk-structured complete CMOS SRAM memory cell. On the semiconductor substrate 11 shown in FIGS. 6 and 7, as shown in FIG.
An element isolation region (LOCO) is formed by selective oxidation so that the second and third impurity diffusion layers 12a, 12b, and 12c are formed.
S) 14 is formed.

As shown in FIG. 2, the side gate electrodes 16a, 16c and the central gate electrode 16b are provided on the impurity diffusion layers 12a, 12b, 12c for each memory cell MC.
Are formed so as to be substantially orthogonal to the impurity diffusion layer. In the impurity diffusion layers 12a, 12b, and 12c, these three rows of gate electrodes 16a, 16b, and 16c are formed by LOCOS.
After being formed on the substrate 14, it is formed in a self-aligned manner by performing ion implantation of impurities. First impurity diffusion layer 12a located on the leftmost side of three rows of impurity diffusion layers
Is a P-type impurity diffusion layer, and the other two rows of impurity diffusion layers 12b and 12c are N-type impurity diffusion layers.

When a P-type semiconductor substrate is used as the semiconductor substrate, the first impurity diffusion layer 12a, which is a P-type impurity diffusion layer, needs to be formed on the surface of the N-type well region. The distance between the first impurity diffusion layer 12a and the N-type second and third impurity diffusion layers is set to be wider than the distance between the second and third impurity diffusion layers 12b and 12c.

The second and third impurity diffusion layers 12b and 12c
Are arranged at point target positions in the memory cell MC.
Also, the first impurity diffusion layers 12a, 12a are vertically separated in FIGS. 1 and 2 at a portion where the central gate electrode 16b is arranged in the memory cell MC, and are symmetric with respect to the center line of the central gate electrode. It is arranged. These impurity diffusion layers
It becomes a source / drain region of a transistor described later.

The impurity diffusion layers 12a, 12b and 12c are
Since it is formed after the formation of the gate electrode as described above,
Although not formed in principle at the intersection with the gate electrode, the side gate electrode 16 shown in FIGS.
At the intersection of a and the second impurity diffusion layer 12b, it is necessary to previously form the buried diffusion layer 18 on the surface of the semiconductor substrate (see FIG. 7).

As shown in FIGS.
A gate insulating layer 62 is formed between a, 16b, and 16c and the semiconductor substrate 11. Gate electrodes 16a, 1
6b and 16c are formed of, for example, a polysilicon layer or a polycide layer (laminated structure of polysilicon and silicide). The gate insulating layer 62 is formed on the semiconductor substrate 11.
Is composed of a silicon oxide layer obtained by thermally oxidizing the surface of the substrate. Semiconductor substrate 11 is formed of, for example, a P-type silicon substrate.

By forming the impurity diffusion layers 12a, 12b, 12c and the gate electrode layers 16a, 16b, 16c in the layout pattern shown in FIGS. 1 and 2, the first impurity diffusion layer 12a and the side gate electrodes 16a, 16b Are formed, P-channel load transistors LQ5 and LQ6 are formed. The central gate electrode 16b corresponds to the word line W of the memory cell MC.
N-channel select transistors SQ3 and SQ4 are formed at the intersections of the second and third impurity diffusion layers 12b and 12c. Further, one side gate electrode 16a and the third
At the intersection with the impurity diffusion layer 12c, one N-channel drive transistor DQ1 is formed, and at the intersection between the other side gate electrode 16c and the second impurity diffusion layer 12b,
Another N-channel drive transistor DQ2 is formed.

In order to form the memory cell circuit shown in FIG. 8 using these transistors, the source / drain regions and gate electrodes of each transistor are connected by the following intermediate conductive layer and metal wiring layer. As shown in FIGS. 6 and 7, on the gate electrodes 16a, 16b and 16c,
A first interlayer insulating layer 64 is formed. First interlayer insulating layer 64
Is composed of, for example, a silicon oxide layer, a PSG layer, a BPSG layer, and the like. On the first interlayer insulating layer 64, FIG.
The first intermediate conductive layers 20a, 20b, 2
0c and 20d are formed. These first intermediate conductive layers are
For example, it is formed of a polysilicon layer, and is processed into a pattern shown in FIG. 3 by a photolithography technique.

Before forming these first intermediate conductive layers, contact holes 22, 24, 26, 28, 30, and 32 shown in FIG. 3 are formed in the first interlayer insulating layer 64 shown in FIGS. Through these contact holes, the first intermediate conductive layers 20a, 20b, 20c, 20d are connected to the impurity diffusion layers 12a, 12b, 12c shown in FIG. FIG.
Among the first intermediate conductive layers shown in FIG. 8, the conductive layer 20a is a conductive layer for shifting the bit line contact position, and the conductive layers 20b and 20c are the storage nodes and the load transistors LQ5 and LQ6 of the memory cell shown in FIG. a conductive layer for connecting the door, the conductive layer 20d is a conductive layer for shifting the take-out position of the power supply voltage line V _SS.

As shown in FIGS. 6 and 7, a second intermediate insulating layer 66 is formed on the first intermediate conductive layer. The second intermediate insulating layer 66 is composed of, for example, a silicon oxide layer, a PSG layer, a BPSG layer, or the like. The second intermediate conductive layer 3 is formed on the second intermediate insulating layer 68 in the pattern shown in FIG.
4a, 34b, 34c, 34d and 34e are formed.
These second intermediate conductive layers are made of, for example, a polysilicon layer, and are processed into a pattern shown in FIG. 4 by photolithography.

Before the formation of these second intermediate conductive layers, the contact holes 36, 38, 4 shown in FIG. 4 are formed in the second interlayer insulating layer 66 and the first interlayer insulating layer 64 shown in FIGS.
0, 42, 44, 46, 48, 49 are formed, and the second intermediate conductive layers 34a, 34a, 3
4b, 34c, 34d, 34e are connected to the impurity diffusion layers 12a, 12c, the side gate electrodes 16a, 16c shown in FIG. 2, and the first intermediate conductive layers 20b, 20c shown in FIG.

The conductive layers 34a and 34b of the second intermediate conductive layer shown in FIG.
This is a conductive layer for connecting the output of the MOS inverter to the input of the other CMOS inverter. The conductive layer 34
c is a conductive layer for connecting to the reference potential V _ss in the memory cell circuit shown in FIG. The conductive layer 34
d is a conductive layer for shifting the take-out position of the power supply voltage line V _SS. Further, the conductive layer 34e is a conductive layer for shifting the bit line extraction position.

The second intermediate conductive layers 34a, 34b, 3
4c, 34d, and 34e, a third interlayer insulating layer 68 and, if necessary, a planarizing layer 7 are formed as shown in FIGS.
0 is formed. Third interlayer insulating layer 68 is formed of, for example, a silicon oxide layer, a PSG layer, a BPSG layer, and the like.
The flattening layer 70 is formed of, for example, an SOG layer.

On the flattening layer 70, metal wiring layers 50a, 50b, 50c, 50d composed of an aluminum wiring layer or the like are formed in the pattern shown in FIG. 5, for example.
Before the metal wiring layer is formed, contact holes 52 and 5 are formed in the planarizing layer and the interlayer insulating layer disposed thereunder.
4, 56, 58, 60 are formed. Through these contact holes, the metal wiring layer is connected to the first underlying layer.
Intermediate conductive layers 20a, 20d and second intermediate conductive layer 34
e, 34d. Then, the metal wiring layer 50a
But inverted bit line b ', and the metal wiring layer 50b is next bit line b, the metal wiring layer 50c becomes the power supply voltage line V _SS.

The memory cell MC of this embodiment is laid out so as to be line-symmetric with respect to the boundary between adjacent cells. However, as shown in FIG. Sex is broken. That is, the bit line contact hole 60 of the bit line metal wiring layer 50d of the adjacent memory cell is formed at the position shown in FIG. This is to separate the contact hole 58 and the contact holes 54 and 60 as much as possible. In this connection, the symmetry of the metal wiring layers 50a, 50b, 50c is partially lost.

The SRAM memory cell MC according to the present embodiment
Then, three rows of gate electrodes 16a, 16b are arranged substantially orthogonally to three rows of impurity diffusion layers 12a, 12b, 12c.
b, 16c are arranged and the gate electrode 16b at the center is a word line W, so that the memory cell M
C becomes horizontally long. Therefore, the pitch interval and the wiring width of the metal wiring layers 50a, 50b, 50c arranged in a direction substantially perpendicular to the word line W can be increased without increasing the cell area of the memory cell MC. As a result, the parasitic capacitance and resistance of the bit lines b and b 'formed of the metal wiring layer can be significantly reduced, and the access speed to the memory cells is improved.

The metal wiring layers 50a, 50b, 50c
Since the wiring pitch between the wirings can be increased, the reliability of the wiring is improved and the wiring processing is facilitated. For example, when the memory cell MC according to the present embodiment is realized using the fine processing technology of the 0.25 μm rule, the memory cell M
The cell size of C is 2.8 μm × 2.0 μm = 5.6 μm
m ² , and the aspect ratio of the cell is 1.4, which proves that the cell is longer than before. Further, the pitch between the metal wiring layers is as large as 1.12 μm, and the operation speed delay in the metal wiring layers can be considerably improved.

By the way, when the memory cell of the conventional layout pattern shown in FIG. 9 is realized by using the microfabrication technique of the 0.5 μm rule, the cell size is 4.6 μm × 4.
0 μm = 18.4 μm ² , and the aspect ratio of the cell is 1.15. Note that the present invention is not limited to the above-described embodiments, and can be variously modified within the scope of the present invention.

[0037]

As described above, according to the present invention, the memory cells are elongated horizontally, and the metal wiring arranged in a direction substantially perpendicular to the word lines without increasing the cell area of the memory cells. The pitch between layers and the wiring width can be increased. As a result, the parasitic capacitance and resistance of the bit line formed of the metal wiring layer can be significantly reduced, and the access speed to the memory cell is improved.

Further, since the wiring pitch between the metal wiring layers can be increased, the reliability of the wiring is improved, and
Wiring processing becomes easy.

[Brief description of the drawings]

FIG. 1 is a plan view showing a layout pattern of an impurity diffusion layer in an SRAM memory cell according to one embodiment of the present invention.

FIG. 2 is a plan view showing a layout pattern of a gate electrode in the memory cell according to the embodiment.

FIG. 3 is a first view of the memory cell according to the embodiment;
FIG. 4 is a plan view showing a layout pattern of an intermediate conductive layer.

FIG. 4 is a second view of the memory cell according to the embodiment;
FIG. 4 is a plan view showing a layout pattern of an intermediate conductive layer.

FIG. 5 is a plan view showing a layout pattern of a metal wiring layer in the memory cell according to the embodiment.

FIG. 6 is a cross-sectional view of a main part along line VI-VI shown in FIG. 2;

FIG. 7 is a cross-sectional view of a main part along line VII-VII shown in FIG. 2;

FIG. 8 is an equivalent circuit diagram of an SRAM memory cell.

FIG. 9 is a plan view showing a layout pattern of an SRAM memory cell according to a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate 12a ... 1st impurity diffusion layer 12b ... 2nd impurity diffusion layer 12c ... 3rd impurity diffusion layer 14 ... LOCOS 16a ... Side gate electrode 16b ... Central gate electrode 16c ... Side gate electrode 18 ... Embedded diffusion layer 20a, 20b, 20c, 20d ... first intermediate conductive layer 34a, 34b, 34c, 34d, 34e ... second intermediate conductive layer 50a, 50b, 50c ... metal wiring layer 62 ... gate insulating layer DQ1, DQ2 ... driving transistor SQ3, SQ4 ... Select transistor LQ5, LQ6 ... Load transistor b ... Bit line b '... Inverted bit line W ... Word line MC ... Memory cell

Claims (5)

(57) [Claims] 1. A semiconductor device having a memory cell including a pair of load transistors, a pair of drive transistors, and a pair of select transistors formed on a semiconductor substrate, wherein each of the memory cells includes a semiconductor substrate. Three rows of impurity diffusion layers formed thereon; and three rows of gate electrodes formed on these three rows of impurity diffusion layers via a gate insulating layer so as to be substantially orthogonal to the impurity diffusion layers. A central gate electrode located at the center of the three rows of gate electrode layers corresponds to a word line of a memory cell, and is selected at an intersection between the central gate electrode and the impurity diffusion layer. A transistor is formed, and a driving transistor and a load transistor are formed at intersections of the side gate electrodes in the other two rows other than the center gate electrode and the impurity diffusion layer, respectively. That the semiconductor memory device. 2. A method according to claim 1, wherein one of the three rows of impurity diffusion layers is a P-type impurity diffusion layer, and the other two rows of second and third impurity diffusion layers are N-type impurity diffusion layers. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a diffusion layer, and the P-type impurity diffusion layer is separated at an intersection with the central gate electrode. 3. The memory device according to claim 2, wherein the second and third impurity diffusion layers are located closer to each other than the distance between the first and second impurity diffusion layers in the memory cell. Semiconductor storage device. 4. A buried diffusion layer located below a gate electrode is formed at a part of an intersection between the second impurity diffusion layer or the third impurity diffusion layer and the two rows of side gate electrodes. The semiconductor memory device according to claim 2. 5. The memory cell of a static random access memory, wherein the pair of load transistors, the pair of drive transistors, and the pair of select transistors are formed by a multilayer wiring layer stacked on the gate electrode. 5. The semiconductor memory device according to claim 1, further comprising: