JP3237683B2 - Frame synchronization control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization control circuit for synchronizing TDMA frames between base stations in a mobile communication system using a TDMA (Time Division Multiple Access) system.

[0002]

2. Description of the Related Art FIG. 4 shows a configuration example of a mobile communication system using a TDMA system. In the figure, a plurality of base stations 1
₀ to 1 _n communicate with mobile stations (portable radios) 3 in the respective wireless zones 2 ₀ to 2 _n using the TDMA method.

[0003] The following describes a conventional frame synchronization control in the base station 1 _0. Base station 1 ₀ detects the transmission frame timing of the peripheral base station 1 _i, detects a difference between the transmission frame timing of the own station as a synchronization error.
However, since the transmission frame timing of the peripheral base station 1 _i cannot be directly detected, the following method is used.

[0004] When the signal near the base station 1 _i is a reception timing t _i which are received by the base station 1 _0, the propagation delay time between the base station 1 ₀ and the peripheral base station 1 _i and t _0i, the base station 1 ₀
There transmission frame timing of the peripheral base station 1 _i to be detected, is estimated to _{t i -t 0i ... (1)} . On the other hand, when the transmission frame timing of the base station 1 ₀ and t _0, the base station 1 ₀ and transmission frame timing difference near the base station 1 _i (synchronization error) [Delta] T _{0i is, ΔT 0i = t i -t 0i} -t 0 … (2)

[0005] Now, when the number of peripheral base stations is n, the average of the base station 1 ₀ and the transmission frame timing difference 1 ₁ to 1 _n each peripheral base stations (average synchronization error) [Delta] T ₀ is

[0006]

(Equation 1)

[0007] Thus, the base station 1 _0, the reception timing and the transmission frame timing of the peripheral base station 1 _i determined from the propagation delay time between base stations near the base station signals (t _i -t _0i), the base station 1 ₀ Transmission frame timing
The frame synchronization is established by detecting the difference (synchronization error ΔT _0i ) from (t ₀ ) and correcting the transmission frame timing accordingly. Furthermore, when the neighboring base stations is more than one in accordance with the average of the transmission frame timing differences of the neighboring base stations 1 ₁ to 1 _n and the base station 1 ₀ (average synchronization error [Delta] T _0), corrects the transmission frame timing This establishes frame synchronization.

FIG. 5 shows a configuration example of a conventional frame synchronization control circuit. In the figure, a synchronization word detection circuit 11 recognizes an information type of a received TDMA signal, detects a synchronization word, and sends out a synchronization word detection pulse a to a reception control circuit 20. The reception control circuit 20 detects the reception timing from the synchronization word detection pulse a, sends out a synchronization word sending timing signal b to the synchronization word position generating circuit 12 with a predetermined time difference, and sends the transmission timing signal c to the transmission control circuit. 30. This time difference differs depending on the TDMA frame format. The synchronizing word position generating circuit 12 sets a synchronizing word detection window in accordance with the synchronizing word sending timing signal b and sends out a synchronizing word position pulse d to the reception control circuit 20. The transmission control circuit 30 sets the transmission frame timing according to the transmission timing signal c.

The reception control circuit 20 is provided with a synchronizing word detection pulse a
, And the time difference between the input timing of the synchronizing word position pulse d and the input timing of the synchronizing word position pulse d.
Here, the transmission frame timing of the own base station has a fixed time relationship with the input timing of the synchronization word position pulse d. Further, the transmission frame timing of the peripheral base station can be obtained by correcting the propagation delay time between the base station and the peripheral base station from the input timing of the synchronization word detection pulse a. This makes it possible to detect a difference (synchronization error) between the transmission frame timings of the base station and the peripheral base station.
Therefore, the reception control circuit 20 can establish frame synchronization between the peripheral base station and the own base station by controlling the synchronization word transmission timing signal b and the transmission timing signal c according to the synchronization error.

[0010]

By the way, each part of the conventional frame synchronization control circuit is configured to operate by the system clock output from the system clock generation circuit 13. That is, the configuration is such that the synchronization error is detected at the system clock cycle and the transmission frame timing is controlled. Therefore, when the system clock is slow, errors in transmission frame timing between base stations are accumulated, and the frame synchronization error of the entire system may increase.

On the other hand, if a high-speed system clock is used, the above problem can be solved and the synchronization accuracy can be improved. However, in order to avoid burst collision, the number of symbols in the guard time (symbol = 1 / system clock) is reduced. You have to take a lot. That is, a long guard time is required, and a decrease in transmission efficiency cannot be avoided. Also,
Since the operation clock of the entire base station becomes faster, an increase in power consumption was unavoidable.

An object of the present invention is to provide a frame synchronization control circuit capable of improving the accuracy of frame synchronization between base stations while shortening the guard time and minimizing the increase in power consumption.

[0013]

According to a first aspect of the present invention, there is provided a high-speed clock generating circuit for generating a clock faster than a system clock used in a base station, and a reception timing of a TDMA signal transmitted by a peripheral base station. A synchronization error detection means for detecting a synchronization error between a transmission frame timing of a peripheral base station detected from the base station and a transmission frame timing generated by a system clock of the base station with a cycle accuracy of a high-speed clock; Transmission timing control means for controlling the transmission frame timing of the base station with the cycle accuracy of the high-speed clock.

According to a second aspect of the present invention, in the frame synchronization control circuit of the first aspect, when the transmission frame timing of the own base station is initially set, the average of the detected transmission frame timings of the peripheral base stations is determined. The value is used as the transmission frame timing of the base station.

[0015]

According to the present invention, only the circuits related to the frame synchronization control are operated by the high-speed clock, and the others are operated by the low-speed system clock. Therefore, detection of the reception timing of the peripheral base station signal, detection of the synchronization error of the transmission frame timing between the base stations, and control of the transmission frame timing of the own base station can be performed with high accuracy, and the frame synchronization between the base stations can be performed. Accuracy can be improved. Moreover,
Since transmission / reception processing is performed using the system clock, it is not necessary to lengthen the guard time, and it is possible to minimize an increase in power consumption.

In addition, even when initializing the transmission frame timing, it is possible to initialize the transmission frame timing with high accuracy by using the average value of the transmission frame timings of the peripheral base stations detected by the high-speed clock. .

[0017]

FIG. 1 shows the configuration of a first embodiment of a frame synchronization control circuit according to the present invention. In the figure, a synchronous word detection circuit 1
1, the arrangement of the synchronizing word position generation circuit 12, the system clock generation circuit 13, the reception control circuit 20, and the transmission control circuit 30 is the same as the conventional one. However, the reception control circuit 20
Has a synchronization error detection circuit 21, a synchronization error averaging circuit 22, and a reception timing control circuit 23. The transmission control circuit 30 has a transmission timing control circuit 31.

A feature of the present invention is that a high-speed clock generation circuit 40 for generating a clock faster than the system clock is provided.
The configuration is such that a high-speed clock is supplied to the synchronization error detection circuit 21, the reception timing control circuit 23, and the transmission timing control circuit 31.

The synchronizing word detecting circuit 11 recognizes the information type of the received TDMA signal, detects a synchronizing word, and sends out a synchronizing word detecting pulse a to the synchronizing error detecting circuit 21 and the receiving timing control circuit 23. The reception timing control circuit 23 detects the reception timing from the synchronizing word detection pulse a with the high-speed clock cycle accuracy, and thereafter outputs the synchronizing word sending timing signal b at a predetermined timing to the synchronizing word position generating circuit 1.
2 and sends the transmission timing signal c to the transmission timing control circuit 31. The synchronizing word position generating circuit 12 sets a synchronizing word detection window according to the synchronizing word sending timing signal b and sends out a synchronizing word position pulse d to the synchronizing error detection circuit 21. The transmission timing control circuit 31 sets a transmission frame timing according to the transmission timing signal c.

The synchronization error detection circuit 21 detects the time difference between the input timing of the synchronization word detection pulse a (synchronization word reception timing) and the input timing of the synchronization word position pulse d using a high-speed clock. Here, the transmission frame timing of the own base station has a fixed time relationship with the input timing of the synchronization word position pulse d. Further, the transmission frame timing of the peripheral base station can be obtained by correcting the propagation delay time between the base station and the peripheral base station from the input timing of the synchronization word detection pulse a. This makes it possible to detect the difference (synchronization error) between the transmission frame timing of the base station and the peripheral base station with the accuracy of the high-speed clock cycle. The synchronization error averaging circuit 22 calculates the average of the synchronization errors with each of the peripheral base stations, and sends an average synchronization error signal e to the reception timing control circuit 23 and the system clock generation circuit 13.

The system clock generating circuit 13 controls the phase of the system clock with high-speed clock cycle accuracy according to the average synchronization error signal e. The reception timing control circuit 23 similarly controls the synchronization word transmission timing signal b and the transmission timing signal c according to the average synchronization error signal e. The transmission timing control circuit 31 sets the transmission frame timing of its own base station with the cycle accuracy of the high-speed clock according to the transmission timing signal c, and establishes frame synchronization with the peripheral base station.

FIG. 2 shows the phase relationship among the synchronizing word detection pulse a, synchronizing word position pulse d, average synchronizing error signal e, transmission frame timing, system clock and high-speed clock. Note that the synchronization word position pulse d and the transmission frame timing indicated by a broken line indicate a state before the synchronization control.

Next, a process in which the base station initializes the transmission frame timing will be described. A synchronization word position pulse d is generated based on the synchronization word detection pulse a of the peripheral base station detected first. The synchronization error detection circuit 21 detects the phase difference between the timing of the synchronization word position pulse d and the timing of the synchronization word detection pulse a of another peripheral base station that is sequentially detected by controlling the cycle of the high-speed clock. The synchronization error averaging circuit 22 averages the phase difference corresponding to each peripheral base station, and the reception timing control circuit 23 calculates
The transmission timing signal c for setting the initial transmission frame timing of the base station is transmitted to the transmission timing control circuit 31. The transmission timing control circuit 31 initializes the transmission frame timing of the own base station according to the transmission timing signal c.

FIG. 3 shows the configuration of a second embodiment of the frame synchronization control circuit of the present invention. The feature of the present embodiment is that the synchronization error detection circuit 21 uses a high-speed clock,
The configuration is such that a synchronization error is detected from the synchronization word detection pulse a and the transmission timing signal c. That is, the transmission frame timing of the own base station has a fixed time relationship with the transmission timing signal c. The transmission frame timing of the peripheral base station can be obtained by correcting the propagation delay time between the base station and the peripheral base station from the input timing of the synchronization word detection pulse a. This makes it possible to detect the difference (synchronization error) between the transmission frame timings of the own base station and the peripheral base station with the cycle accuracy of the high-speed clock. Other configurations are the same as in the first embodiment.

[0025]

As described above, the present invention improves the frame synchronization accuracy between base stations by selectively using the high-speed clock and the low-speed system clock and operating only the circuits related to the frame synchronization control with the high-speed clock. be able to. In addition, since the other components are operated by the system clock, there is no need to lengthen the guard time, and the increase in power consumption can be minimized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a frame synchronization control circuit of the present invention.

FIG. 2 is a diagram showing a relationship between signals of respective parts of the first embodiment.

FIG. 3 is a block diagram showing a configuration of a second embodiment of the frame synchronization control circuit of the present invention.

FIG. 4 is a diagram showing a configuration example of a mobile communication system using a TDMA scheme.

FIG. 5 is a block diagram showing a configuration example of a conventional frame synchronization control circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 base station 2 wireless zone 3 mobile station (portable radio) 11 sync word detection circuit 12 sync word position generation circuit 13 system clock generation circuit 20 reception control circuit 21 synchronization error detection circuit 22 synchronization error averaging circuit 23 reception timing control circuit 30 Transmission control circuit 31 Transmission timing control circuit 40 High-speed clock generation circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-276935 (JP, A) Yoshihiko Akaiwa et al. “Autonomous base station mutual synchronization method in TDMA cellular system” IEICE Technical Report RCS 90-46, Page 25 to 29 (58) Fields investigated (Int. Cl. ⁷ , DB name) H04B ^7/ 24-7/26 102 H04Q ^7/ 00-7/38

Claims (2)

(57) [Claims] 1. A wireless communication system , comprising: a base station corresponding to each wireless zone that communicates with a mobile station in each wireless zone by using a TDMA method; and operates by a system clock of the base station to synchronize TDMA frames among a plurality of base stations. A frame synchronization control circuit for generating a system clock;
Separately, a high-speed clock generation circuit that generates a clock faster than the system clock; a transmission frame timing of a peripheral base station detected from a reception timing of a TDMA signal transmitted by the peripheral base station;
A synchronization error detecting means for detecting a synchronization error with a transmission frame timing generated by a system clock of the own base station with a cycle accuracy of the high-speed clock; A frame synchronization control circuit, comprising: transmission timing control means for controlling with clock cycle accuracy. 2. The frame synchronization control circuit according to claim 1, wherein, at the time of initial setting of the transmission frame timing of the own base station, the average value of the detected transmission frame timings of the peripheral base stations is transmitted by the own base station. A frame synchronization control circuit characterized in that the frame timing is configured to be frame timing.