JP3238481B2 - Semiconductor read-only memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor read-only memory device (hereinafter referred to as a semiconductor ROM), and more particularly to a read mode of "1" → "1" or "0" → "1" of output data. The present invention relates to a technique for preventing generation of a “0” glitch when a row line is switched.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a part of a conventional CMOS type (complementary insulated gate type) EPROM (UV erasable / rewritable ROM).

[0003] 1 is a memory cell array, 2 is a row decoder for selectively controlling a row line of the memory cell array MA according to row address inputs A7 to A3, 3 is a column selector for selecting a column line of the memory cell array 1, and 4 is a column address. Input A2 to A0
, A column decoder for selectively controlling the column selector 3 in accordance with the above, 5 is an output circuit including a sense amplifier and an output buffer, and 6 is an output buffer control circuit. FIG. 8 shows the EPRO of FIG.
FIG. 4 is a circuit diagram showing a part of M.

In the memory cell array 1, memory cells (S11 to S1n), (S21 to S2)
In (n),..., the gate threshold value of the cell transistor is set according to the stored data “0” or “1”. WL0, W
L1 are row lines, and BL1 to BLn are column lines. Row decoder 2 has a decoder circuit for decoding a row address input and row line drive circuits 2b.

The column selector 3 includes column selection transistors CS1 to CS connected in series to column lines BL1 to BLn, respectively.
It is composed of Sn, divided into eight groups, and the other ends of the column selection transistors of each group are commonly connected.

The column decoder 4 includes a decoder circuit for decoding a column address input and column selection signals CL0, CL1,.
And a column selection transistor driving circuit 4b for supplying CL2 to the column selection signal line.

The output circuit 5 detects and amplifies signals OT0 to OT7 read at common connection points (common column lines DL0 to DL7) between the column selection transistors of each set.
And sense amplifiers SA0 to SA7 and a clocked inverter.
To eight output buffers BF0 to BF7 for inverting the outputs of .about.SA7 and outputting to the output bus.

The output buffer control circuit 6 outputs complementary output enable signals (OTEN, / OTEN) based on the read enable signal RDEN to the output buffers BF0 to BF0.
Supply to BF7. The sense amplifiers SA0 to SA7
Are each configured as shown in FIG.

In FIG. 3, reference numeral 30 denotes a differential circuit having a current mirror load, and a precharge signal PS is activated by receiving a signal / PS inverted by an inverter 31. A column line voltage clamp circuit is inserted between one input terminal of the differential circuit 30 and the common column line.
For example, a sense reference voltage VREF of 3 V is applied to the other input terminal of 0.
Is supplied.

In the above clamp circuit, the PMOS transistor P1 whose gate and drain are connected to each other has a voltage of V
An NMOS transistor N1 is connected between a CC node (for example, a power supply voltage of 5 V) and one input terminal of the differential circuit 30, and is connected between one input terminal of the differential circuit 30 and a common column line.
Is inserted, and a bias voltage BIAS is supplied to the gate of the transistor N1.

Further, a pull-up PMOS transistor P2 is connected between the VCC node and one input terminal of the differential circuit 30, and the gate of the PMOS transistor P2 is connected to the ground potential V.
SS is given. A pull-up PMOS transistor P3 is connected between the VCC node and the other input terminal of the differential circuit 30, and the gate thereof is supplied with the inverted precharge signal / PS. The normal read operation of the ROM is well known, and will be briefly described below.

At the time of access when the row address input changes while the column address input remains unchanged, the potential of each column line connected to each memory cell selected by row selection becomes
When the selected cell is in the OFF state (the state of the storage data “0”), for example, a high level of 3.5 V (higher than the sense reference voltage VREF), and the selected cell is in the ON state (the state of the storage data “1”). In this case, for example, it becomes a low level of 2.5 V (a level lower than the sense reference voltage VREF). The potential of this selected column line becomes output data D0 to D7 via a sense amplifier and an output buffer. In this case, the high level / low level of the potential of the selected column line corresponds to “0” level (low level) / “1” level (high level) of read / read data output.

That is, since the potential of the column line connected to the selected memory cell changes between 2.5 V and 3.5 V, the read data output is between "1" and "0". And changes as “1” → “0” or “1” → “1” or “0” → “0” or “0” → “1”.

On the other hand, at the time of access when the column address input changes while the row address input remains unchanged, a read data output corresponding to the level of the column line connected to the selected memory cell appears, and the read data is output. The output changes in the order of “1” → “0” or “1” → “1” or “0” → “0” or “0” → “1”. The row lines WL0, WL1,... Are usually made of polysilicon, polycide, etc.
1n-1), (R21 to R2n-1)... Also, row line W
A large number of cells (S11 to S1n), (S21
ＳS2n)... Exist as loads.

Due to the signal delay due to the resistance and the load capacitance, the row lines WL0, WL1,... The rise of the row selection signal near the column line BLn near the other end (end) of the WL1... On the side opposite to the row decoder side is delayed, and the selection of the cell connected to the column line BLn starts at the time of row selection. There is a problem that a glitch occurs in the output data due to the delay. Hereinafter, the reason why the glitch occurs in the output data will be described in detail. FIG. 9 is a timing waveform chart showing an example from the address selection of the EPROM to the data output.

For example, when reading data from the selected cells S11 and S1n-2, the row line WL0 is selected and activated ("H" level), and at the same time, the column selection signal line CL0 for selecting the column selection transistor CS1 is activated. (“H” level)
After that, the read enable signal RDEN is activated ("H" level). In this case, since the rise of the row line signal near the selected cell S1n-2 is delayed more than the row line signal near the selected cell S11, the cell S1n-2 is more advanced than the timing of the data read from the cell S11 to the common column line DL0. , The timing of the data read to the common column line DL7 is delayed. The output enable signal OTEN is activated (“H”) slightly after the activation of the read enable signal RDEN.
Level), the read data OT of the common column line DL0 is
0 is output to the output bus 7 as output data D ", and the read data OT7 of the common column line DL7 is output to the output bus 7 as output data D7.

Thereafter, when the row address input is changed and the selected row line is switched from WL0 to WL1 to read data from the selected cells S21 and S2n-2 while keeping the column address input and the read enable signal RDEN unchanged. Similarly to the above, the rise of the row line signal near the selected cell S2n-2 is delayed more than the row line signal near the selected cell S21.
Output data D0 of cell S21 and output data D of cell S2n-2
7 has a timing difference.

In the above operation, the output data D0 is normally read, but the output data D7 is normally read after a "0" glitch occurs. In other words, the rising and falling of the waveform of the row selection signal near the column line BLn becomes less, and the non-selection period of the row selection signal near the column line BLn becomes longer when the row address input is switched. During this non-selection period, the PM connected to one input terminal of the sense amplifier is
The potential of the common column line is pulled up by the OS transistors P1 and P2.

Therefore, the newly selected cell S2n-2
Is in the ON state, the output data D7 should originally change from "1" to "1" or "0" to "1", but during this change (the non-selection period). To "0" transiently. When such a “0” glitch occurs, the access time of “1” data to the selected cell S2n-2 in the ON state is significantly deteriorated. The above phenomenon occurs not only in the EPROM but also in an electrically erasable / rewritable ROM (EEPROM).

[0020]

As described above, in the conventional semiconductor ROM, in the read mode of "1" → "1" or "0" → "1" of the output data, the resistance of the row line and the load capacitance are reduced. As a result, a "0" glitch occurs at the time of switching the row lines due to the delay of the row selection signal, and the access time of the "1" data is greatly deteriorated.

The present invention has been made in order to solve the above-mentioned problems, and it is intended that output data "1" → "1" or "0" →
In the “1” read mode, even if the row selection signal is delayed due to the resistance of the row line or the load capacitance, it is possible to prevent a “0” glitch from being generated when the row line is switched.
An object of the present invention is to provide a semiconductor read-only memory device capable of improving the access time of "1" data.

[0022]

According to the present invention, there is provided a semiconductor read-only memory device, a memory cell array in which read-only memory cells are arranged in a matrix, a row decoder for selecting a row line of the memory cell array, and the memory cell array. A column selection transistor for selecting the column line of the above, a column decoder for controlling the column selection transistor, a sense amplifier for detecting and amplifying a read signal from the selected column line passing through the column selection transistor, and an output of the sense amplifier. A data output buffer for buffer amplification and the row decoder
It is located on the opposite side across the line, and at the transition of the row address input
All the outputs of the row decoder are in a non-selected state.
The de receiving a row decoder output transition detection circuit which detects Rukoto, the detection output of the row decoder output transition detection circuit
And a control circuit for controlling the data output buffer to a non-operating state.
The row decoder output transition detection circuit includes
From the same type of transistor as the read-only memory cell.
And outputs each output of the row decoder to the gate through the row line.
And a dummy cell transistor,
Common to the drains of these dummy cell transistors.
Connected between the dummy column line and the power supply.
Pull connected to the gate and the precharge signal is supplied to the gate
A first logic circuit having an up transistor;
The output of the first logic circuit and the precharge signal
Is supplied and a detection output is input to the control circuit.
And a logic circuit . In addition, the present invention
Semiconductor read-only memory devices are read-only memory cells.
Memory cell array in which memory
A row decoder for selecting a row line of the recell array;
A column selection transistor for selecting a column line of the recell array;
A column decoder for controlling the column selection transistor;
Read signal from selected column line via column select transistor
Amplifier that detects and amplifies
A data output buffer for buffering the output;
The decoder is located on the opposite side of the row line, and the row address
All outputs of the row decoder are unselected at the transition of source input
Row decoder output transition detection
Detection circuit and the detection output of this row decoder output transition detection circuit
And controls the data output buffer to a non-operating state.
And a control circuit for detecting the row decoder output transition.
The path is of the same type as the read-only memory cell.
The gate consists of a gate, and the gate is
Cell transistor input to each output of the
And the drains of these dummy cell transistors.
Column line having a dummy column line commonly connected to
The circuit and one end of the current path are connected to the power supply and
The first transformer for pull-up to which the recharge signal is supplied
A transistor, an output node of the dummy column line circuit and the first
Connected in series with the other end of the current path of the transistor,
One gate is connected to the power supply and the other gate is
And a third transistor to which a source voltage is applied, and one of the transistors
The other end of the current path of the first transistor is connected to the input end
The precharge signal is supplied to the other input terminal.
A logic circuit for inputting a detection output to the control circuit.
It is characterized by

[0023]

[Function] Output data "1" → "1" or "0" →
In the “1” read mode, the row selection signal is delayed due to the resistance of the row line and the load capacitance, and the rise of the row selection signal near the other end of the row line opposite to the row decoder side is delayed. The non-selection period of the row selection signal at the other end becomes longer,
The column line potential is pulled up. However, during this non-selection period (when the row line is switched), a detection output (pulse) is generated from the row decoder output transition detection circuit. The control circuit is
When this detection output is input, the operation of the output buffer is controlled to an impossible state. Therefore, no "0" glitch occurs in the output data during the non-operation period of the output buffer, and the output data changes from "1" to "1" or "0" to "1" as originally intended.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a part of an EPROM according to an embodiment of the semiconductor ROM of the present invention.

This EPROM is different from the conventional EPROM described above with reference to FIG. 7 in that a row decoder output transition detecting circuit 11 is added and an output buffer control circuit 12 is changed, and the other parts are the same. Therefore, the same reference numerals as in FIG. 7 are used.

That is, 1 is a memory cell array, 2 is a row decoder for selectively controlling a row line of the memory cell array 1 in accordance with row address inputs A7 to A3, 3 is a column selector for selecting a column line of the memory cell array 1, and 4 is a column selector. Column address input A2
A column decoder for selectively controlling the column selector 3 according to A0;
5 is an output circuit including a sense amplifier and an output buffer;
11 is a row decoder output transition detection circuit, and 12 is an output buffer control circuit. Row decoder output transition detection circuit 1
1 is for detecting a transition state of the output of the row decoder 2.

When the detection output ENB of the row decoder output transition detection circuit 11 is being input, the output buffer control circuit 12 inhibits the input of the read enable signal RDEN and deactivates the output buffer 7 of the output circuit 5. Control the state.

FIG. 2 is a circuit diagram showing a part of the EPROM shown in FIG. 1, and the conventional EPROM described with reference to FIG.
The row decoder output transition detection circuit 11 and the output buffer control circuit 12 are different from those of the first embodiment, and the other components are the same.

That is, the memory cell array 1 includes memory cells (S11 to S1n) and (S21 to S2n) in a matrix of m rows × n columns.
... are arranged. Each of these memory cells has a floating gate and a control gate, and is composed of, for example, an N-channel MOS transistor having a source connected to the ground potential VSS.
It is set according to “1”.

In the memory cell array 1, WL
Are row lines commonly connected to the gates of the memory cells in the same row. BL1 to BLn are column lines commonly connected to the drains of the memory cells in the same column.

The row decoder 2 includes a decoder circuit for decoding a row address input and a row line driving circuit 2b for selectively driving the row lines WL0, WL1 (for example, a polysilicon line) in accordance with the output of the decoder circuit. Having.

The column selector 3 is connected to, for example, N series connected to the column lines BL1 to BLn of the memory cell array 1, respectively.
It comprises channel column selection transistors CS1 to CSn,
It is divided into eight sets, and the other ends of the column select transistors of each set are commonly connected. The column decoder 4 includes a decoder circuit for decoding a column address input and column select transistors CS1 to CSn according to the output of the decoder circuit.
Column selection signals CL0, CL1,.
And a column selection drive circuit 4b for supplying CL2 to a column selection signal line (for example, an aluminum line).

The output circuit 5 detects and amplifies the signals OT0 to OT7 read out at the common connection points (common column lines DL0 to DL7) between the respective column selection transistors.
And sense amplifiers SA0 to SA7 and a clocked inverter.
To eight output buffers BF0 to BF7 for inverting the outputs of .about.SA7 and outputting to the output bus.

The row decoder output transition detection circuit 11
Two NOR circuits 111 and 112 are used. First
The NOR circuit 111 includes a dummy cell NM for which each output of the row line driving circuits 2...
The OS transistors (SD1, SD2...), A dummy column line DBL commonly connected to the drains of these dummy cell transistors, and a connection between the dummy column line and the VCC node. And a pull-up PMOS transistor P4 input thereto.
In this case, the dummy cell transistors (SD1, SD2
.. Are arranged on the opposite side of the row lines WL0, WL1,... From the row decoder side, and the memory cells (S11 to S1)
n), (S21-S2n)... are of the same type. The second NOR circuit 112 receives the output of the first NOR circuit 111 and the precharge signal PS.

In the row decoder output transition detecting circuit 11, the precharge signal PS is at the active level ("L").
, The pull-up transistor P4 is turned on,
Dummy column line DBL is precharged to "H" level. When all the outputs of the row decoder 2 are in the non-selected state at the time of the transition of the row address input, the transistors (SD1, SD2...) For the dummy cells are turned off, and the dummy column line DBL is set to the “H” level. And the output ENB of the second NOR circuit 112 becomes “L” level (detection output level). During other periods, the output ENB of the second NOR circuit 112 is at “H” level. Precharge signal P
When S is at the inactive level (“H”), the output ENB of the second NOR circuit 112 goes to “L” level.

The output buffer control circuit 12 includes a NAND circuit 121 to which the output of the row decoder output transition detection circuit 11 and the read enable signal RDEN are input, and a complementary output enable signal (OTEN) based on the output of the NAND circuit 121. , / OTEN) for controlling the output buffers BF0 to BF7.

In the output buffer control circuit 12, when the output ENB of the row decoder output transition detection circuit 11 is at "H" level, the read enable signal RDE
When N is input, the complementary output enable signal (OTE
N, / OTEN) and output buffers BF0 to BF
7 to an operable state. On the other hand, when the output ENB of the row decoder output transition detection circuit 11 is at the “L” level, the input of the read enable signal RDEN is inhibited, and the output buffers BF0 to BF7 are controlled to the inactive state. A large load capacitance (including external capacitance) C0 is parasitic on the output bus 7. FIG. 3 shows sense amplifiers SA0 to SA0.
FIG. 9 is a circuit diagram illustrating an example of one of SA7s.

In this sense amplifier, reference numeral 30 denotes a differential circuit having a current mirror load, and a precharge signal PS is activated by receiving a signal / PS inverted by an inverter 31. A column line voltage clamp circuit is inserted between one input terminal of the differential circuit 30 and a common column line, and a sense reference voltage VREF of, for example, 3 V is supplied to the other input terminal of the differential circuit 30. .

In the above clamp circuit, the PMOS transistor P1 whose gate and drain are connected to each other has a voltage of V
An NMOS transistor N1 is connected between a CC node (for example, a power supply voltage of 5 V) and one input terminal of the differential circuit 30, and is connected between one input terminal of the differential circuit 30 and a common column line.
Is inserted, and a bias voltage BIAS is supplied to the gate of the transistor N1.

Further, a pull-up PMOS transistor P2 is connected between the VCC node and one input terminal of the differential circuit 30, and the gate of the PMOS transistor P2 is connected to the ground potential V.
SS is given. A pull-up PMOS transistor P3 is connected between the VCC node and the other input terminal of the differential circuit 30, and the gate thereof is supplied with the inverted precharge signal / PS.

Next, the operation of the EPROM will be described.
Here, the normal read operation is basically the same as the operation of the EPROM shown in FIG. 7, so that the detailed description is omitted, and hereinafter, the output data “1” → “1” or “0” →
The read operation in the read mode “1” will be described. FIG. 4 is a timing waveform diagram showing an example from the address selection of the EPROM to the data output.

For example, when reading data from the selected cells S11 and S1n-2, the row line WL0 is selected and activated ("H" level), and at the same time, the column selection transistor CS is read.
After activating (“H” level) the column selection signal line CL0 for selecting “1”, the read enable signal RD
EN is activated ("H" level). In this case, the rise of the row line signal near the selected cell S1n-2 is delayed more than the row line signal near the selected cell S11.
Cell S1n-2 than the timing of the data read to 0
, The timing of the data read to the common column line DL7 is delayed. Then, when the output enable signal OTEN is activated ("H" level) slightly after the activation of the read enable signal RDEN, the read data OT0 of the common column line DL0 is output to the output bus 7 as the output data D ". , Read data OT7 of the common column line DL7
Are output to the output bus 7 as output data D7.

Thereafter, while the column address input and the read enable signal RDEN remain unchanged, the row address input is changed to switch the selected row line from WL0 to WL1 to read data from the selected cells S21 and S2n-2. Similarly to the above, the rise of the row line signal near the selected cell S2n-2 is delayed more than the row line signal near the selected cell S21.
Output data D0 of cell S21 and output data D of cell S2n-2
7 has a timing difference.

In the above operation, when the newly selected cell S2n-2 is in the ON state, that is, reading "1" → "1" or "0" → "1" of the output data D7. In the mode, the resistance (R21 to R21) of the row line WL1 is used.
R2n) and the load capacitance cause a delay in the row selection signal, which delays the rise of the row selection signal near the other end (termination) opposite to the row decoder, and deselects the row selection signal at the other end. The period becomes longer, and during this non-selection period, the PMOS transistors P1, P2 connected to one input terminal of the sense amplifier,
The potential of the common column line is pulled up by P2.

However, in the EEPROM of this embodiment, a detection output ENB is generated from the row decoder output transition detection circuit 11 during the non-selection period (when the row line is switched). The output buffer control circuit 12 outputs the detection output EN
When B is input, the operation of the output buffers BF0 to BF7 is controlled to an impossible state.

Therefore, there is no difference in the access time between the output data D0 to D7 during data reading, and no "0" glitch occurs in the output data D7 during the non-operation period of the output buffers BF0 to BF7. , The output data D7 changes from “1” → “1” or “0” → “1” as it should be.

If the "0" glitch does not occur in the output data as described above, a margin for latch timing of an output latch circuit (not shown) occurs, so that the design of the memory system becomes easy and the malfunction of the memory system occurs. Is prevented. FIG. 5 is a circuit diagram showing a modification of the row decoder output transition detection circuit 11 in FIG.

Reference numeral 50 denotes the dummy cells SD1, S1 as described above.
And a dummy column line DBL. Two NMOS transistors N2 and N3 are inserted in series between the output node of the dummy column line circuit 50 and the pull-up transistor P4. ing. And
The gate of the NMOS transistor N2 is connected to the Vcc node, and the bias voltage BIAS is applied to the gate of the NMOS transistor N3. Other configurations are the same as those of the row decoder output transition detection circuit 11 in FIG. FIGS. 6A to 6C show modifications of the dummy cell in FIG.

6A is a normal NMOS transistor, FIG. 6B is an EEPROM cell, and FIG.
(C) shows a flash type EEPROM having an erase gate.
OM cell is shown.

[0050]

As described above, according to the present invention, in the read mode of "1" → "1" or "0" → "1" of the output data, the row line resistance or load capacitance causes the row data. Even if the selection signal is delayed, it is possible to prevent a "0" glitch from being generated when the row line is switched, and to realize a semiconductor read-only memory device capable of improving the access time of "1" data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an EPROM according to one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a part of the EPROM of FIG. 1;

FIG. 3 is a circuit diagram showing one example of a sense amplifier taken out from FIG. 2;

FIG. 4 is a timing waveform chart showing an example of a read operation of the EPROM of FIG. 1;

FIG. 5 is a circuit diagram showing a modified example of the row decoder output transition detection circuit in FIG. 2;

FIG. 6 is a circuit diagram showing a modification of the dummy cell in FIG. 2;

FIG. 7 is a block diagram showing a part of a conventional EPROM.

FIG. 8 is a circuit diagram showing a part of the EPROM of FIG. 7;

9 is a timing waveform chart showing an example of a read operation of the EPROM of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Row decoder, 3 ... Column selector, 4 ... Column decoder, 5 ... Output circuit, 7 ... Output bus, 1
DESCRIPTION OF SYMBOLS 1 ... Row decoder output transition detection circuit, 12 ... Output buffer control circuit, 50 ... Dummy column line circuit, 111, 112 ... NOR circuit, 121 ... NAND circuit, 122 ... Inverter circuit, S11-S1n, S21-S2n ... Memory cell , WL0, W
L1 ... row line, BL1 to BLn ... column line, CS1 to CSn ...
Column selection transistor, DL1 to DLn ... common column line, SA
0 to SA7: sense amplifier, BF0 to BF7: output buffer, SD1, SD2: dummy cell, DBL: dummy column line.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-76095 (JP, A) JP-A-64-17298 (JP, A) Special table 61-500513 (JP, A) (58) Field (Int. Cl. ⁷ , DB name) G11C 17/00 G11C 11/34

Claims (5)

(57) [Claims] A memory cell array in which read-only memory cells are arranged in a matrix; a row decoder for selecting a row line of the memory cell array; a column selection transistor for selecting a column line of the memory cell array; a column decoder for controlling the transistor, a sense amplifier for detecting and amplifying a read signal from the selected column line passing through the column selection transistor, and a data output buffer for buffering amplifying the output of the sense amplifier, the row decoder and row Lines located on opposite sides of the line
At the transition of the address input, all outputs of the row decoder
A row decoder output transition detection circuit for detecting that it is a non-selected state, before receiving the detection output of the row decoder output transition detection circuit
A control circuit for controlling the data output buffer to a non-operating state , wherein the row decoder output transition detection circuit is
It consists of the same type of transistor as the memory cell and has a gate
Output of the row decoder via the row line
Input dummy cell transistors and these dummy cells
A transistor commonly connected to each drain of the cell transistor
Connected between the dummy column line and the power supply,
For pull-up where the precharge signal is supplied to the gate
A first logic circuit having a transistor, an output of the first logic circuit and the precharge signal
Is supplied and a detection output is input to the control circuit.
A semiconductor read-only memory device comprising a logic circuit . 2. The semiconductor read-only memory according to claim 1, wherein:
In the apparatus, the first logic circuit and the second logic
A semiconductor read-only memory device, wherein each circuit is a NOR circuit . 3. The read-only memory cells are arranged in a matrix.
Memory cell array, a row decoder for selecting a row line of the memory cell array, and a column selection transistor for selecting a column line of the memory cell array.
, A column decoder controlling the column selection transistor, and reading from a selected column line via the column selection transistor.
A sense amplifier that detects and amplifies signals, and a data output that buffers and amplifies the output of this sense amplifier
A buffer and the row decoder are disposed on opposite sides of the row line,
At the transition of the address input, all outputs of the row decoder
Row decoder output to detect non-selection status
The transition detection circuit and the row decoder output
Control circuit for controlling the data output buffer to a non-operating state
Comprising the door, the row decoder output transition detection circuit, said read-only
It consists of the same type of transistor as the memory cell and has a gate
Output of the row decoder via the row line
Input dummy cell transistors and these dummy cells
A transistor commonly connected to each drain of the cell transistor
A dummy column line circuit having a me column line , one end of a current path connected to a power supply,
First transistor for pull-up to which a signal is supplied
When the output node of the dummy column line circuit first transistor
Connected in series with the other end of the current path of the
Connected to the power supply, and the bias voltage is impressed on the other gate.
Second and third transistors to be applied, and one input terminal connected to the other end of the current path of the first transistor.
Is connected, and the precharge signal is supplied to the other input terminal.
A logic circuit for supplying a detection output to the control circuit.
The semiconductor read only memory device, characterized in that it comprises a. 4. A semiconductor read-only memory according to claim 3,
In the device, the logic circuit is a NOR circuit . 5. The method according to claim 1, wherein:
Semiconductor read-only memory device, wherein the control circuit
Is the detection output of the row decoder output transition detection circuit
Disables input of read enable signal
The semiconductor read only memory device comprising a this <br/> for controlling said data output buffer to the non-operating state by.