JP3239459B2 - Power supply voltage monitoring circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply voltage monitoring circuit, and more particularly to a power supply voltage monitoring circuit which outputs a signal for instructing release of a reset after a delay of a predetermined time when the power supply voltage exceeds a specified value. Circuit.

[0002]

2. Description of the Related Art FIG.
FIG. 1 shows a circuit diagram of an example of a conventional power supply voltage monitoring circuit proposed in US Pat. Reference numeral 1 denotes a digital circuit such as a CPU having a reset terminal 1a. When the reset terminal 1a is at a high level (hereinafter, referred to as "H"), reset is released, and when the reset terminal 1a is at a low level (hereinafter, referred to as "L"). It goes into the reset state. The digital circuit 1 operates with the power supply voltage Vcc.

The power supply voltage Vcc is applied to the digital circuit 1.
And the power supply terminal T of the power supply voltage monitoring circuit.₁, Between T2
Is also applied. The power supply voltage monitoring circuit
Output terminal T that outputs the signal_ThreeAnd the output terminal T_ThreeIs
Resistance R_LThrough the power terminal T ₁Connected to
It is connected to the reset terminal 1a of the digital circuit 1. output
Terminal T_ThreeAnd power terminal T_TwoBetween the reset control signal
NPN transistor Q for output_FourIs connected.

Further, the power supply voltage Vcc is determined by the resistors R ₁ and R _2.
With the divided voltage V ₁ is generated in the reference voltage V _Z is generated by the constant current source 3 and a Zener diode D _Z. The partial pressure voltages V ₁ is input to the inverting input terminal of the comparator 2, the reference voltage V _Z is input to a non-inverting input terminal of the comparator 2. The partial pressure voltages V ₁ is compared with the reference voltage V _Z by the comparator 2.

Accordingly, the output voltage of the comparator 2 becomes “H” when the divided voltage V ₁ according to the power supply voltage Vcc is smaller than the reference voltage V _Z (V ₁ <V _Z ), and the divided voltage V ₁
When is larger than the reference voltage _{V Z (V 1> V Z} ) is "L".

The output voltage of the comparator 2 is supplied to the base of a transistor Q ₄ via a resistor R ₄ and a diode D _3, while the output voltage of the NPN transistor Q is supplied via a resistor R _6.
Supplied to ₃ bases.

An oscillation circuit 6 is connected between the power supply terminals T ₁ and T ₂ . Oscillator circuit 6 a comparator 7, the resistor R ₇ to R
_10, consisting of a capacitor C _2. The oscillation output voltage of the comparator 7 of the oscillation circuit 6 is supplied to the frequency divider 8.

The frequency dividing circuit 8 has a reset terminal connected to a transistor.
Star Q_ThreeThrough the power terminal T_TwoConnected to. Divider circuit
8 is reset when its reset terminal becomes "H"
Is released and the output oscillation signal of the oscillation circuit 6 is divided.
During this time, the signal of "H" is output. Output signal of frequency divider 8
Is the resistance R_FiveAnd diode D_TwoThrough the transistor
Q _FourSupplied to the base.

Next, the operation of the power supply voltage monitoring circuit of FIG. 4 will be described. FIG. 5 shows a waveform diagram of a main part of the circuit of FIG. First, it is assumed that the power supply voltage Vcc is applied as shown in FIG. When the power supply voltage Vcc is equal to the detection voltage V _S (V _S = V
_When it becomes equal to or more than _{Z Z} (1 + R ₁ / R ₂ )), the output voltage V ₂ of the comparator 2 becomes “L”. (Time t ₁ ) When the output voltage V _{2 of the} comparator 2 becomes “L”, the diode D ₃ is turned off. When the output voltage V ₂ of the comparator 2 becomes "L", the transistor Q ₃ is turned off, the reset terminal of the frequency divider circuit 8 becomes "H", the frequency divider circuit 8 is released the reset. The frequency divider 8 sets the output voltage V ₃ to “H” for a fixed time T _D for dividing the oscillation signal from the oscillator 6, and thereafter sets the output voltage V ₃ to “L”.

Therefore, at time t₁And diode D_ThreeBut
The diode D_TwoIs on and transistor Q
_FourRemains "H". Therefore, Transis
TA Q _FourIs the time t₀~ T_TwoIs on during this time, and during this time
Is the output terminal T_ThreeVoltage V₀Is "L" and the digital circuit
1 is in a reset state.

[0011] time T _D of the output signal to divide the oscillation circuit 6 from the time t ₁ is elapsed, since the output voltage of the dividing circuit 8 becomes "L", the diode D ₂ is turned off, along with this transistor Q ₄ Te is also turned off. Therefore, the voltage V ₀ of the output terminal T ₃ becomes “H”, and the digital circuit 1
Is released from reset. Thus, the power supply voltage Vcc is equal to or higher than the detection voltage V _S, after a predetermined time T _D has elapsed, the reset digital circuit 1 is released.

[0012]

However, in the conventional power supply voltage monitoring circuit, the power supply voltage is supplied to the oscillating circuit and the frequency dividing circuit even when the reset control signal does not instruct the reset, so that the current consumption is large. There was a problem.

The present invention has been made in view of the above points, and does not supply a power supply voltage to an oscillation circuit and a frequency dividing circuit except when a reset control signal instructs a reset, and monitors a power supply voltage that consumes a small amount of current. It is intended to provide a circuit.

[0014]

According to the present invention, in order to solve the above problems, a reset is instructed when the power supply voltage is equal to or lower than a specified value. A power supply voltage monitoring circuit that supplies a reset control signal for instructing release of a reset after a predetermined time determined by the oscillation signal and the frequency dividing circuit to the power supply voltage supply circuit, when the power supply voltage falls below a specified value. N
Tsu is DOO, outputs a reset control signal for instructing a reset, a signal indicating the time after the predetermined time from the time when the power supply voltage reaches a specified value or higher is supplied from the frequency divider, the divider in response to a signal from the reset, it outputs a reset control signal for instructing the release of the reset, before
An output circuit for holding the state of the serial reset control signal, said
Controlled by the reset control signal held in the output circuit
Is, when the reset control signal indicates a reset supplies a power supply voltage to the oscillator circuit and divider circuit, when the reset control signal instructs to cancel the reset, to the oscillator circuit and divider circuit And a switch circuit for interrupting the supply of the power supply voltage .

[0015]

According to the present invention, the switch circuit supplies the power supply voltage to the oscillation circuit and the frequency dividing circuit when the reset control signal indicates the reset, and when the reset control signal indicates the release of the reset, the oscillation circuit And shut off the supply of the power supply voltage to the frequency dividing circuit. For this reason, it is possible to reduce the current consumption of the power supply voltage monitoring circuit.

[0016]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. 1, the same components as those in FIG. 3 are denoted by the same reference numerals.
Reference numeral 1 denotes a digital circuit such as a CPU having a reset terminal 1a. When the reset terminal 1a is at a high level (hereinafter referred to as "H"), the reset is released, and when the reset terminal 1a is at a low level (hereinafter referred to as "L"). To the reset state. The digital circuit 1 operates with the power supply voltage Vcc.

The power supply voltage Vcc is applied to the digital circuit 1.
And the power supply terminal T of the power supply voltage monitoring circuit.₁, Between T2
Is also applied. The power supply voltage monitoring circuit
Output terminal T that outputs the signal_ThreeAnd the output terminal T_ThreeIs
Resistance R_LThrough the power terminal T ₁Connected to
It is connected to the reset terminal 1a of the digital circuit 1. output
Terminal T_ThreeAnd power terminal T_TwoBetween the reset control signal
NPN transistor Q for output_FourIs connected.

The comparator circuit 5 includes a resistor R₁, R_Two,
R₆, R_Fifteen, Current source 3, Zener diode D_Z, Con
Parator 2, transistor Q_ThreeConsisting of Power terminal
T₁, T _TwoA resistor R for dividing voltage₁, R_TwoAnd reference voltage generation
Constant current source 3 and Zener diode D_ZIs connected
And the resistance R₁, R_TwoDivided voltage of power supply voltage Vcc
V ₁Is generated, and the constant current source 3 and the Zener die
Aether D_ZThe reference voltage V_ZIs generated.

The divided voltage V ₁ is input to the inverting input terminal of the comparator 2, and the reference voltage V _Z is input to the non-inverting input terminal of the comparator 2. The partial pressure voltages V ₁ is compared with the reference voltage V _Z by the comparator 2.

Therefore, the output voltage of the comparator 2 becomes “H” when the divided voltage V ₁ according to the power supply voltage Vcc is smaller than the reference voltage V _Z (V ₁ <V _Z ), and the divided voltage V ₁
When is larger than the reference voltage _{V Z (V 1> V Z} ) is "L".

The output voltage V of the comparator 2_TwoIs the resistance R_Four
And diode D_ThreeThrough the transistor Q_FourBase of
While the resistor R₆NPN Transis through
TA Q _ThreeSupplied to the base.

The base of the transistor Q ₄ is connected to the power supply terminal T ₂ via a resistor R ₁₆ . The base of the transistor Q ₃ are power terminal T through a resistor ₁₅
Connected to _two .

[0023] 6 in the oscillation circuit is connected between the collector and a power supply terminal T ₂ of the transistor Q ₁₂ of the switch circuit 12. Oscillator circuit 6 a comparator 7, the resistor R ₇ to R _10, composed of the capacitor C _2. With an inverting input terminal of the comparator 7 is connected to the capacitor C _2, connected to the output terminal of the comparator 7 via a resistor R _9. Also, with the non-inverting input terminal of the comparator 7 resistors R _7, the divided voltage obtained by dividing the power supply voltage V ₁₁ min with R ₈ is applied,
Feedback from the output terminal of the comparator 7 via a resistor R ₁₀ is applied.

The capacitor C ₂ is charged / discharged by the output level of the comparator 7 via the resistor R _9. Therefore, the level of the inverting input terminal of the comparator 7 changes by charging / discharging of the capacitor C ₂ , and the oscillation is maintained. . Oscillation circuit 6
The oscillation output voltage of the comparator 7 is supplied to the frequency dividing circuit 13.

The frequency dividing circuit 13 has a reset terminal * R
(* Indicates a negative logic) is connected to the power supply terminal T ₂ via the transistor Q _3. Also, supplied with the power supply voltage V ₁₁ from the collector of the transistor Q ₁₂ of the switch circuit 12.

The frequency dividing circuit 13 is reset when its reset terminal * R is "L", and its Q output terminal is "H". The reset is released when the reset terminal * R becomes "H", and the signal of "H" is output from the Q output terminal during the period of dividing the output oscillation signal of the oscillation circuit 6. The signal at the Q output terminal of the frequency divider 13 is supplied to the reset terminal * R of the memory circuit 14.

The output circuit 11 includes a memory circuit 14, a resistor R
_5, the diode D _2, resistors R _4, diode D _3, the resistor R _16, the more the transistor Q _4. Set terminal * S of the memory circuit 14 is connected to the collector of the transistor Q _3. The Q output terminal of the memory circuit 14 has a resistor R ₅ ,
While being connected to the base of the transistor Q ₄ via the diode D _2, it is connected to the base of the transistor Q ₁₁ of the switch circuit 12 via the resistor R _11.

The memory circuit 14 is set when the set terminal * S is at "L" and the Q output terminal is at "H". When the reset terminal * R is at "L", the memory circuit 14 is reset and the Q output terminal is at "L". L ”.

Reference numeral 12 denotes a switch circuit which includes transistors Q ₁₁ and Q ₁₂ , and resistors R ₁₁ , R ₁₂ and R ₁₃ . The switch circuit 12 outputs the voltage V ₄ of the Q output terminal of the memory circuit 14.
When the but "H", the transistors Q ₁₁ and Q ₁₂ are turned on, from the collector of the transistor Q _12, approximately equal voltage oscillation to the power supply voltage Vcc circuit 6, and frequency divider 13
Supplied to When the voltage V _{4 at} the Q output terminal of the memory circuit 14 is “L”, the transistors Q ₁₁ and Q ₁₂
There turned off, from the collector of the transistor Q _12, the power supply voltage is not supplied to the oscillation circuit 6, and frequency divider 13.

Next, the operation of the power supply voltage monitoring circuit of FIG. 1 will be described. FIG. 2 shows a waveform diagram of a main part of the circuit of FIG. FIG. 2 (A) shows the voltage V ₀ which power supply voltage Vcc, and the output terminal T ₃ of the reset control signal. FIG. 2B shows the output voltage V ₂ of the comparator 2, the voltage V ₄ of the Q output terminal of the memory circuit 14, and the voltage V ₁₁ of the power supply terminals of the oscillation circuit 6 and the frequency divider 13. FIG. 2C shows the current consumption I _in of the power supply voltage monitoring circuit.

First, it is assumed that the power supply voltage Vcc is applied as shown in FIG. At time t _0, when the power supply voltage Vcc becomes equal to or higher than the reference voltage V _Z, the output voltage V of the comparator 2
₂ becomes "H". Then, at time t _1, the power supply voltage Vcc
Is equal to or higher than the detection voltage V _S (V _S = V _Z · (1 + R ₁ / R ₂ )), the output voltage V ₂ of the comparator 2 becomes “L”.
Becomes When the output voltage V ₂ of the comparator 2 is "H", the diode D ₃ is on, the transistor Q ₄ is turned on, the voltage V ₀ which output terminal T ₃ becomes "L".

[0032] time becomes t _0, the output voltage V ₂ becomes "H" of the comparator 2, the transistor Q ₃ is turned on, a reset terminal * voltage R of the frequency divider circuit 13, and the set terminal of the memory circuit 14 The voltage of * S becomes “L”.
At this time, the memory circuit 14 is set, and the voltage V _{4 at the} Q output terminal thereof becomes “H”.

Therefore, the transistors Q ₁₁ and Q ₁₂ of the switch circuit 12 are turned on, and the power supply voltage is supplied to the oscillation circuit 6 and the frequency dividing circuit 13. When the power supply voltage is supplied, the voltage of the reset terminal * R of the frequency divider 13 becomes “L”.
So, the frequency divider circuit 13 is reset, the voltage V ₇ of the Q output terminal is "H". Further, since the voltage V _{4 at} the Q output terminal of the memory circuit 14 is “H”, the diode D ₂ is turned on.

At time t ₁ , since the power supply voltage Vcc becomes higher than the detection voltage V _S , the output voltage V ₂
There becomes "L", the transistor Q ₃ is turned off, the reset terminal * voltage R of the frequency divider circuit 13, and the voltage of the set terminal * S of the memory circuit 14 becomes "H". Thus, frequency divider 13 is released to reset during a predetermined time T _D for dividing an output signal from the oscillation circuit 6, the voltage V ₇ of the Q output terminal keeps the "H", passed T _D Time t
After _2, the output voltage V ₇ becomes “L”.

Time t₁The set terminal of the memory circuit 14
The voltage of * S becomes “H”, but the output voltage of the frequency divider 13
V₇Maintains “H”, and the voltage of the Q output terminal of the memory circuit 14 is
Pressure V _FourKeep "H". Therefore, the switching circuit 12
Transistor Q₁₁, Q₁₂Is on, the oscillation circuit 6 and the
The power supply voltage is continuously supplied to the circuit 13.

At time t ₁ , the output voltage V ₂ of the comparator ₂
There becomes "L", even if the diode D ₃ is turned off, the voltage V ₄ of the Q output terminal of the memory circuit 14 keeps the "H", the diode D ₂ is on, the transistor Q ₄ are still on the Become.

At time t ₂ , the output voltage V _{7 of the} frequency divider 13 becomes “L”, so that the reset terminal * R of the memory circuit 14 becomes “L”, the memory circuit 14 is reset, and its Q voltage V ₄ of the output terminal becomes "L". Therefore, the transistors Q ₁₁ and Q ₁₂ of the switch circuit 12 are turned off, and the supply of the power supply voltage to the oscillation circuit 6 and the frequency divider 13 is cut off.

As a result, the Q output terminal of the frequency dividing circuit 13 becomes a high impedance state, and the reset terminal * R of the memory circuit 14 becomes "H", but the set terminal * S has already become "H". , The voltage V ₄ of the Q output terminal of the memory circuit 14 is kept at “L”. Therefore, the time t ₂ after, diode D _2, the transistor Q ₄ are turned off.

As described above, the transistor Q ₄ is set at the time t.
_{0 to} t ₂ , and during this time, the output terminal T
The voltage V ₀ of the reset control signal ₃ is “L”, and the digital circuit 1 is in a reset state. After time t ₂ ,
The voltage V ₀ of the output terminal T ₃ becomes “H”, and the reset of the digital circuit 1 is released.

As described above, the voltage V of the reset control signal
_During times t _{0 to} t _{2 when 0} is “L” instructing reset, the transistors Q ₁₁ and Q _{12 of} the switch circuit ₁₂ are turned on, and the power supply voltage is supplied to the oscillation circuit 6 and the frequency dividing circuit 13. . As shown in FIG. 2 (C), during this time, the power supply voltage V _CC linearly increases and then becomes a constant value.
The current consumption I _in of the power supply voltage monitoring circuit shows a similar change.

The voltage V of the reset control signal₀Is reset
Time t at which “H” is issued to instruct release _TwoAfter that, the oscillation circuit
6, and the supply of the power supply voltage to the frequency dividing circuit 8 is interrupted.
The current consumption I of the power supply voltage monitoring circuit_inIs the comparator
FIG. 2C shows only the currents of the circuit 5 and the memory circuit 14.
It has a small value as shown.

As shown in FIG. 2A, at time t ₃
During the ~t _4, when the power supply voltage Vcc is lower than the detection voltage V _S, the output voltage V ₂ of the comparator 2 between times t ₃ ~t _4, to "H". During this time, the diode D ₃ is on,
Transistor Q ₄ is turned on.

Before time t ₃ , the voltage V _{4 at} the Q output terminal of the memory circuit 14 is “L”, the transistors Q ₁₁ and Q ₁₂ of the switch circuit ₁₂ are off, and the oscillation circuit 6 and the frequency dividing circuit 13 Is not supplied with the power supply voltage, and the frequency divider 13
Are in a high impedance state.
Therefore, the reset terminal * R of the memory circuit 14 is set at "H".
It has become.

[0044] When the time becomes t _3, the output voltage V ₂ becomes "H" of the comparator 2, the transistor Q ₃ is turned on, a reset terminal * voltage R of the frequency divider circuit 13, and the set terminal of the memory circuit 14 The voltage of * S becomes “L”.
Since the reset terminal * R of the memory circuit 14 is "H" as described above, the memory circuit 14 is set, the voltage V ₄ of the Q output terminal is "H".

Therefore, the transistors Q ₁₁ and Q ₁₂ of the switch circuit 12 are turned on, and the power supply voltage is supplied to the oscillation circuit 6 and the frequency dividing circuit 13. When the power supply voltage is supplied, the voltage of the reset terminal * R of the frequency divider 13 becomes “L”.
So, the frequency divider circuit 13 is reset, the voltage V ₇ of the Q output terminal is "H". Further, since the voltage V _{4 at} the Q output terminal of the memory circuit 14 is “H”, the diode D ₂ is turned on.

At time t ₄ , since the power supply voltage Vcc becomes higher than the detection voltage V _S , the output voltage V ₂
There becomes "L", the transistor Q ₃ is turned off, the reset terminal * voltage R of the frequency divider circuit 13, and the voltage of the set terminal * S of the memory circuit 14 becomes "H". Thus, frequency divider 13 is released to reset during a predetermined time T _D for dividing an output signal from the oscillation circuit 6, the voltage V ₇ of the Q output terminal keeps the "H", passed T _D Time t
₅ thereafter the output voltage V ₇ becomes "L".

Time t_FourThe set terminal of the memory circuit 14
The voltage of * S becomes “H”, but the output voltage of the frequency divider 13
V₇Maintains “H”, and the voltage of the Q output terminal of the memory circuit 14 is
Pressure V _FourKeep "H". Therefore, the switching circuit 12
Transistor Q₁₁, Q₁₂Is on, the oscillation circuit 6 and the
The power supply voltage V₁₁Continue to be supplied.

At time t ₄ , the output voltage V ₂ of the comparator ₂
There becomes "L", even if the diode D ₃ is turned off, the voltage V ₄ of the Q output terminal of the memory circuit 14 keeps the "H", the diode D ₂ is on, the transistor Q ₄ are still on the Become.

At time t ₅ , the output voltage V _{7 of the} frequency divider 13 becomes “L”, so that the reset terminal * R of the memory circuit 14 becomes “L”, the memory circuit 14 is reset, and its Q voltage V ₄ of the output terminal becomes "L". Therefore, the transistors Q ₁₁ and Q ₁₂ of the switch circuit 12 are turned off, and the supply of the power supply voltage to the oscillation circuit 6 and the frequency divider 13 is cut off.

As a result, the Q output terminal of the frequency divider 13 becomes high impedance, and the reset terminal * R of the memory circuit 14 becomes "H", but the set terminal * S is already "H". , The voltage V ₄ of the Q output terminal of the memory circuit 14 is kept at “L”. Therefore, the time t ₅ after, the diode D _2, the transistor Q ₄ are turned off.

As described above, the transistor Q ₄ is set at the time t.
₃ be between ON states ~t _5, during this period, the output terminal T
The voltage V ₀ of the reset control signal ₃ is “L”, and the digital circuit 1 is in a reset state. In addition, time t ₅ after,
The voltage V ₀ of the output terminal T ₃ becomes “H”, and the reset of the digital circuit 1 is released.

As described above, the voltage V of the reset control signal
₀ instructs the reset between times t ₃ ~t ₅ is "L", the transistors Q _11, Q ₁₂ of the switch circuit 12 is turned on, the power supply voltage is supplied to the oscillation circuit 6, and frequency divider 13 . As shown in FIG. 2C, during this time, the current consumption I _in of the power supply voltage monitoring circuit is reduced by the oscillation circuit 6 and the frequency dividing circuit 1.
Since the current of 3 is included, the value is large.

The voltage V of the reset control signal₀Is reset
Time t at which “H” is issued to instruct release _FiveAfter that, the oscillation circuit
6, and the supply of the power supply voltage to the frequency dividing circuit 13 is cut off.
Therefore, the current consumption I of the power supply voltage monitoring circuit is_inIs a comparison
FIG. 2C shows only the currents of the data circuit 5 and the memory circuit 14.
It becomes a small value as shown in FIG.

As described above, in the first embodiment, only when the voltage V ₀ of the reset control signal at the output terminal T ₃ is “L” instructing reset, the power supply voltage V is applied to the oscillation circuit 6 and the frequency dividing circuit 13. ₁₁ is supplied. Therefore, current consumption of the power supply voltage monitoring circuit can be reduced. Therefore, when the power supply voltage monitoring circuit of the present embodiment is used in a battery-operated device, the life of the battery can be extended as compared with a conventional circuit.

FIG. 3 is a circuit diagram of a second embodiment of the present invention. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. In the second embodiment, the switch circuit 12 is low potential side and the power supply between the terminals T ₂ of the on-the oscillation circuit 6, and frequency divider 23, are configured to perform off.

[0056] As shown in FIG. 3, the comparator circuit 5, the output voltage V ₂ of the comparator 2 produces a voltage V ₈ inverted by the inverter 25, and supplied to the transistor Q ₃₃ via the resistor R _26. The transistor Q ₃₃ is turned on when the power supply voltage V _CC is lower than the detection voltage V _{S, and} changes the “H” voltage to the reset terminal R of the frequency divider 23 and the memory circuit 24.
To the set terminal S.

The oscillation circuit 6, and frequency divider 23, a collector and a power supply terminal T of the transistor Q ₂₂ of the switch circuit 12
Connected between _one . The frequency dividing circuit 23 is reset when its reset terminal R is "H", and the Q output terminal becomes "H". When the reset terminal R becomes “L”, the reset is released, and the “H” signal is output from the Q output terminal during the period of dividing the output oscillation signal of the oscillation circuit 6. The signal at the Q output terminal of the frequency divider 23 is supplied to the reset terminal * R of the memory circuit 24.

The output circuit 11 includes a memory circuit 24, a resistor R
_5, the diode D _2, resistors R _4, diode D _3, the resistor R _16, the more the transistor Q _4. The set terminal S of the memory circuit 24 is connected to the collector of the transistor Q _33. Also, * Q output terminal of the memory circuit 14 is connected to the base of the transistor Q ₂₁ of the switch circuit 12 via the resistor R _21.

In the memory circuit 24, the set terminal S is "H".
, The * Q output terminal is set to "L", and when the reset terminal * R is "L", the output is reset and the * Q output terminal is set to "H".

Reference numeral 12 denotes a switch circuit which includes transistors Q ₂₁ and Q ₂₂ and resistors R ₂₁ , R ₂₂ and R ₂₃ . While the collector of the transistor Q _21, the resistor R _5, via the diode D ₂ is connected to the base of the transistor Q _4.

The switch circuit 12 has the *
When the voltage V ₅ of the Q output terminal of the "L", the transistor Q _21, and Q ₂₂ is turned on, the collector voltage of the transistor Q ₂₂ becomes substantially the voltage of the power supply terminal T _2, the oscillation circuit 6, and frequency divider 23 is supplied with a power supply voltage. Further, the voltage V ₅ of the * Q output terminal of the memory circuit 24 is "H"
, The transistors Q ₂₁ and Q ₂₂ are turned off,
The power supply voltage is not supplied to the oscillation circuit 6 and the frequency dividing circuit 23.

When the voltage V _{5 at} the * Q output terminal of the memory circuit 24 is “L” and the transistor Q
_21, and when Q ₂₂ is turned on, the voltage V ₆ of the collector connected to the resistor R ₅ of the transistor Q ₂₁ becomes "H",
The diode D ₂ and the transistor Q ₄ are turned on.

Next, the operation of the second embodiment will be described.
Since the operation of the second embodiment is almost the same as that of the first embodiment,
As shown in FIG. 2, a case where the power supply voltage V _CC becomes equal to or lower than the detection voltage V _S between times t _{3 and} t ₄ will be described.

As shown in FIG. 2A, the times t _{3 to} t ₄
During the period, when the power supply voltage Vcc becomes lower than the detection voltage V _S , the output voltage V ₂ of the comparator ₂ is changed between the times t _{3 and} t ₄ .
It becomes "H". During this time, the diode D ₃ is on, the transistor Q ₄ is turned on.

Before time t ₃ , * Q of the memory circuit 24
Voltage V ₅ is "H" of the output terminal, the transistor Q _21, Q ₂₂ of the switching circuit 12 is off, the power supply voltage not supplied to the oscillation circuit 6, and frequency divider 23, the divider circuit 2
3 is in a high impedance state. Therefore, the reset terminal * R of the memory circuit 24 is at "H".

At time t ₃ , the output voltage V ₂ of the comparator 2 becomes “H” and the output voltage V
₈ becomes "L". Therefore, the transistor Q ₃₃ is turned on, the reset terminal voltage R of the frequency divider circuit 23, and the voltage of the set terminal S of the memory circuit 24 to "H".
Since the reset terminal * R of the memory circuit 24 is "H" as described above, the memory circuit 24 is set, the voltage V ₅ of the * Q output becomes "L".

Accordingly, the transistors Q ₂₁ and Q ₂₂ of the switch circuit 12 are turned on, and the power supply voltage is supplied to the oscillation circuit 6 and the frequency dividing circuit 23. When the power supply voltage is supplied, the voltage of the reset terminal R of the frequency dividing circuit 23 is “H”, so that the frequency dividing circuit 23 is reset, and the voltage V ₇ of the Q output terminal becomes “H”. The transistor Q ₂₁ is turned on, so that the collector voltage V ₆ is "H", the diode D ₂ is turned on.

At time t ₄ , since the power supply voltage Vcc becomes higher than the detection voltage V _S , the output voltage V ₂
There becomes "L", the transistor Q ₃₃ is turned off, the reset terminal voltage R of the frequency divider circuit 23, and a memory circuit 2
4, the voltage of the set terminal S becomes “L”. Thus, frequency divider 23 is released to reset during a predetermined time T _D for dividing an output signal from the oscillation circuit 6, the voltage V ₇ of the Q output terminal keeps the "H", passed T _D time t ₅ after that the output voltage V ₇ that becomes "L".

Time t_FourThe set terminal of the memory circuit 24
Although the voltage of S becomes “L”, the output voltage V
₇Keeps “H”, and the power of the * Q output terminal of the memory circuit 24 is
Pressure V _FourKeep "L". Therefore, the switching circuit 12
Transistor Q_{twenty one}, Q_{twenty two}Is on, the oscillation circuit 6 and the
The power supply voltage is continuously supplied to the circuit 23.

At time t ₄ , the output voltage V ₂ of the comparator ₂
There becomes "L", even if the diode D ₃ is turned off, the transistor Q ₂₁ is kept ON, the collector voltage V ₆ is so "H", the diode D ₂ is on, the transistor Q ₄ are still on the Become.

At time t ₅ , the output voltage V _{7 of the} frequency dividing circuit 23 goes to “L”, so that the reset terminal * R of the memory circuit 24 goes to “L”, and the memory circuit 14 is reset. voltage V ₅ of the Q output terminal becomes "H". Therefore, the transistors Q ₂₁ and Q ₂₂ of the switch circuit 12 are turned off, and the supply of the power supply voltage to the oscillation circuit 6 and the frequency dividing circuit 23 is cut off.

As a result, the Q output terminal of the frequency dividing circuit 23 enters a high impedance state, and the reset terminal * R of the memory circuit 24 becomes "H", but the set terminal S is already "L". voltage V ₅ of the * Q output terminal of the memory circuit 24 is kept to "H". Therefore, the time t ₅ after, the diode D _2, the transistor Q ₄ are turned off.

As described above, transistor Q ₄ is turned on at time t.
₃ be between ON states ~t _5, during this period, the output terminal T
The voltage V ₀ of the reset control signal ₃ is “L”, and the digital circuit 1 is in a reset state. In addition, time t ₅ after,
The voltage V ₀ of the output terminal T ₃ becomes “H”, and the reset of the digital circuit 1 is released.

As described above, the voltage V of the reset control signal
₀ instructs the reset between times t ₃ ~t ₅ is "L", the transistors Q _21, Q ₂₂ of the switch circuit 12 is turned on, the power supply voltage is supplied to the oscillation circuit 6, and frequency divider 23 . As shown in FIG. 2C, during this time, the current consumption I _in of the power supply voltage monitoring circuit is reduced by the oscillation circuit 6 and the frequency dividing circuit 2.
Since the current of 3 is included, the value is large.

The voltage V of the reset control signal₀Is reset
Time t at which “H” is issued to instruct release _FiveAfter that, the oscillation circuit
6, and the supply of the power supply voltage to the frequency dividing circuit 23 is cut off.
Therefore, the current consumption I of the power supply voltage monitoring circuit is_inIs a comparison
FIG. 2C shows only the currents of the data circuit 5 and the memory circuit 24.
It becomes a small value as shown in FIG.

[0076] As described above, in the second embodiment, like the first embodiment, the voltage V of the reset control signal at the output terminal T ₃
Only when “ ₀ ” is “L” indicating reset, the oscillation circuit 6
The power supply voltage is supplied to the frequency dividing circuit 23. For this reason,
The current consumption of the power supply voltage monitoring circuit can be reduced. Therefore, when the power supply voltage monitoring circuit of the present embodiment is used in a battery-operated device, the life of the battery can be extended as compared with the conventional circuit.

The circuits of the first embodiment and the second embodiment are as follows.
While the low-level reset control signal output from the output terminal T ₃ is Low reset type for instructing the reset, by a PNP-type reset control signal output transistor, a high level reset control signal indicates a reset It is also possible to configure a High reset type circuit. Further, the switch circuit 12 can be configured to use a MOSFET or a JFET instead of the transistor.

[0078]

As described above, according to the present invention, the switch circuit supplies the power supply voltage to the oscillation circuit and the frequency dividing circuit only when the reset control signal indicates the reset.
It has such features that the current consumption of the power supply voltage monitoring circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a waveform diagram of a main part of the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional example.

FIG. 5 is a waveform diagram of a main part of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Digital circuit 2 Comparator 5 Comparator circuit 6 Oscillation circuit 7 Comparator 11 Output circuit 12 Switch circuit 13, 23 Divider circuit 14, 24 Memory circuit

Claims (1)

(57) [Claims] 1. Reset when power supply voltage is lower than specified value
At the time when the power supply voltage exceeds a specified value.
Determined by the oscillation signal of the oscillation circuit and the frequency dividing circuit
Reset control signal to instruct reset release after a predetermined time
Power supply voltage monitoring circuit that supplies the signal to the power supply voltage supply circuit
In the above, when the power supply voltage falls below a specified value,Set,
Outputs a reset control signal for instructing reset, and
After the above-mentioned predetermined time from the time when the source voltage becomes
The signal indicating the time is supplied from the frequency dividerAnd above
Reset according to the signal from the peripheral circuit,Reset solution
Output a reset control signal instructing, The reset
An output circuit for holding a state of the control signal; Controlled by a reset control signal held in the output circuit
And When the reset control signal indicates a reset
Supplies a power supply voltage to the oscillation circuit and the frequency dividing circuit,
When the reset control signal instructs release of reset
Interrupts the supply of power supply voltage to the oscillation circuit and the frequency divider circuit.
And a switch circuit for disconnecting the power supply.
Pressure monitoring circuit.