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JP3239504B2 - Method of manufacturing thin film transistor matrix - Google Patents
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JP3239504B2 - Method of manufacturing thin film transistor matrix - Google Patents

Method of manufacturing thin film transistor matrix

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Publication number
JP3239504B2
JP3239504B2 JP364093A JP364093A JP3239504B2 JP 3239504 B2 JP3239504 B2 JP 3239504B2 JP 364093 A JP364093 A JP 364093A JP 364093 A JP364093 A JP 364093A JP 3239504 B2 JP3239504 B2 JP 3239504B2
Authority
JP
Japan
Prior art keywords
film
electrode
forming
storage capacitor
transparent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP364093A
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Japanese (ja)
Other versions
JPH06208137A (en
Inventor
喜義 尾崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
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Fujitsu Ltd
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Filing date
Publication date
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Priority to JP364093A priority Critical patent/JP3239504B2/en
Publication of JPH06208137A publication Critical patent/JPH06208137A/en
Application granted granted Critical
Publication of JP3239504B2 publication Critical patent/JP3239504B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明はアクティブマトリクス駆
動方式による液晶パネル等に構成される薄膜トランジス
タ(TFT) マトリクスの製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor (TFT) matrix formed on a liquid crystal panel or the like by an active matrix driving method.

【0002】近年,ラップトップパーソナルコンピュー
タや壁掛けテレビに使用するTFT マトリクス型液晶パネ
ルの開発が進められている。TFT マトリクス型液晶パネ
ルは表示品質がCRT と同等であることが認められつつあ
るが, 価格, 信頼性, 製造歩留の点で改善の余地が残さ
れている。
In recent years, TFT matrix type liquid crystal panels used for laptop personal computers and wall-mounted televisions have been developed. Although the display quality of TFT matrix type liquid crystal panels has been recognized to be equivalent to that of CRTs, there is still room for improvement in price, reliability, and manufacturing yield.

【0003】[0003]

【従来の技術】アクティブマトリクス駆動方式による液
晶パネルはドット表示を行う個々の画素に対応してマト
リクス状にTFT を配置し,各画素にメモリ機能を持たせ
コントラスト良く多ラインの表示を可能としている。
2. Description of the Related Art In an active matrix driving type liquid crystal panel, TFTs are arranged in a matrix corresponding to individual pixels for dot display, and each pixel is provided with a memory function to enable multi-line display with high contrast. .

【0004】図4はTFT マトリクスの平面図である。TF
T マトリクス型液晶パネルは, X,Y方向に交差してマ
トリクス状に配置された多数のゲートバスライン41とド
レインバスライン42に駆動電圧を印加して,両バスライ
ン交差部に接続されたTFT 43を選択駆動することによ
り, 対応する所望の画素をドット表示するように構成さ
れている。このようなTFT マトリクスの構造は, 例え
ば, 透明絶縁性のガラス基板上にチタン(Ti)−アルミニ
ウム(Al)からなる多数のゲートバスラインとドレインバ
スラインとが窒化シリコン(SiN) 等からなる層間絶縁膜
を介してX,Y方向に交差した形に配置され, 両バスラ
インの交差部にTFT が接続されている。また,TFT の動
作半導体層にアモルファスシリコン(a-Si)層を用いる場
合には,ゲート絶縁膜にプラズマ気相成長(P-CVD) 法に
よる窒化シリコン膜(SiN) あるいは窒化シリコンオキシ
ナイトライド(SiNO)膜が用いられていた。
FIG. 4 is a plan view of a TFT matrix. TF
The T matrix type liquid crystal panel applies a driving voltage to a large number of gate bus lines 41 and a plurality of drain bus lines 42 arranged in a matrix so as to intersect in the X and Y directions, and the TFTs connected to the intersections of both bus lines. By selectively driving 43, a corresponding desired pixel is displayed in dots. The structure of such a TFT matrix is, for example, that a large number of gate bus lines and drain bus lines made of titanium (Ti) -aluminum (Al) are formed on a transparent insulating glass substrate by an interlayer made of silicon nitride (SiN). They are arranged so as to intersect in the X and Y directions via an insulating film, and a TFT is connected to the intersection of both bus lines. When an amorphous silicon (a-Si) layer is used as the operating semiconductor layer of the TFT, a silicon nitride film (SiN) or a silicon nitride oxynitride (SiN) film formed by a plasma vapor deposition (P-CVD) method is used as a gate insulating film. (SiNO) film was used.

【0005】なお,図中, 8DはTFT のドレイン電極, 8S
はTFT のソース電極, 8Cは蓄積容量上部電極(補助容量
バスライン)を示す。図5(A) 〜(F) は従来のTFT 素子
の製造工程を説明する断面図である。
In the figure, 8D is the drain electrode of the TFT, 8S
Indicates the source electrode of the TFT, and 8C indicates the storage capacitor upper electrode (auxiliary capacitor bus line). 5A to 5F are cross-sectional views illustrating the steps of manufacturing a conventional TFT element.

【0006】図5(A) において,透明絶縁性基板として
ガラス基板 1上にスパッタリングによりAl膜とCr膜を連
続して成膜し,フォトリソグラフィによりレジスト膜を
パターニングした後, レジスト膜をマスクにしてエッチ
ングしてゲート電極 2と蓄積容量下部電極 3を形成す
る。
In FIG. 5A, an Al film and a Cr film are continuously formed by sputtering on a glass substrate 1 as a transparent insulating substrate, and the resist film is patterned by photolithography. To form a gate electrode 2 and a storage capacitor lower electrode 3.

【0007】次いで, レジスト膜を剥離し,P-CVD 法に
より, 第1層目絶縁膜であるゲート絶縁膜および蓄積容
量誘電体膜としてSiN 膜 4, 動作半導体層としてa-Si膜
5,チャネル保護膜としてSiN 膜 6を連続成長する。こ
こで, 第1層目絶縁膜は,CVD SiN 膜 4の代わりに原子
層エピタキシ(ALD) 法によるアルミナ膜を用いてもよ
い。
Next, the resist film is peeled off, and the gate insulating film as the first insulating film and the SiN film as the storage capacitor dielectric film, and the a-Si film as the working semiconductor layer by the P-CVD method.
5. Continuously grow a SiN film 6 as a channel protective film. Here, instead of the CVD SiN film 4, an alumina film formed by an atomic layer epitaxy (ALD) method may be used as the first insulating film.

【0008】図5(B) において,ゲート電極 2の直上の
チャネル保護膜 6を残すようにパターニングする。図5
(C) において,基板上にコンタクト層として n+ 型a-Si
層 7とソースドレイン電極用金属膜 8を連続成膜する。
In FIG. 5B, patterning is performed so that the channel protective film 6 immediately above the gate electrode 2 is left. FIG.
In (C), an n + -type a-Si
The layer 7 and the metal film 8 for source / drain electrodes are continuously formed.

【0009】図5(D) において,コンタクト層 7とソー
スドレイン電極用金属膜 8をパターニングして, ドレイ
ン電極8Dと, ソース電極8Sと, 蓄積容量上部電極8Cを形
成する。
In FIG. 5D, the contact layer 7 and the metal film 8 for source / drain electrodes are patterned to form a drain electrode 8D, a source electrode 8S, and a storage capacitor upper electrode 8C.

【0010】図5(E) において,第2層目絶縁膜14とし
て,P-CVD 法によりSiN 膜を成膜し,ソース電極8Sと蓄
積容量上部電極8C上にコンタクト孔を形成する。図5
(F) において,基板上に透明電極膜としてITO 膜を成膜
して, 蓄積容量上部電極8Cとソース電極8Sとにコンタク
トをとり, パターニングして画素電極11とし,TFT マト
リクスを形成する。
In FIG. 5E, a SiN film is formed as a second insulating film 14 by a P-CVD method, and a contact hole is formed on the source electrode 8S and the storage capacitor upper electrode 8C. FIG.
In (F), an ITO film is formed as a transparent electrode film on the substrate, and the storage capacitor upper electrode 8C and the source electrode 8S are contacted and patterned to form the pixel electrode 11, thereby forming a TFT matrix.

【0011】[0011]

【発明が解決しようとする課題】第2層目絶縁膜 9は厚
さ3000〜4000Åに成膜するが,成膜条件により膜質は大
きく変わる。この膜質の変化により,この膜に, ドライ
またはウエットエッチングによりコンタクト孔を形成し
た際に, 図6のようにコンタクト孔の断面形状が順テー
パ,垂直,逆テーパの形が得られる。順テーパの場合は
特に問題はなく,ITO 膜11を成膜した際にコンタクト孔
を通して蓄積容量上部電極とソース電極とにコンタクト
をとることができるが,逆テーパの場合はコンタクトを
とることができず表示欠陥となる。
The second-layer insulating film 9 is formed to a thickness of 3000 to 4000.degree., But the quality of the film greatly changes depending on the film forming conditions. Due to this change in film quality, when a contact hole is formed in this film by dry or wet etching, the contact hole has a forward tapered, vertical, or reverse tapered cross-sectional shape as shown in FIG. In the case of a forward taper, there is no particular problem. When the ITO film 11 is formed, a contact can be made with the storage capacitor upper electrode and the source electrode through the contact hole. In the case of a reverse taper, a contact can be made. Display defects.

【0012】また, 第2層目絶縁膜 9はモノシラン(SiH
4)とアンモニア(NH3) を主原料とする強い還元雰囲気中
で成膜されるため,下地に金属の化合物汚染が微量に残
留していても, これを還元して導通性異物を発生させ
る。そのため,基板表面が導通することがあった。
The second insulating film 9 is made of monosilane (SiH
4 ) Since the film is formed in a strong reducing atmosphere mainly composed of ammonia and NH 3 , even if a small amount of metal compound contamination remains on the base, it is reduced to generate conductive foreign substances. . For this reason, the substrate surface sometimes became conductive.

【0013】本発明はTFT 素子の製造において,2層目
絶縁膜に開けるコンタクト孔を順テーパ形状にし且つ基
板表面の導通化を防止し,素子の信頼性と製造歩留の向
上を目的とする。
An object of the present invention is to improve the reliability and manufacturing yield of a TFT device by forming a contact hole formed in a second insulating film in a forward tapered shape and preventing conduction on the substrate surface, thereby improving the reliability of the device and the manufacturing yield. .

【0014】[0014]

【課題を解決するための手段】上記課題の解決は, 1)透明絶縁性の基板 1上にゲート電極 2と蓄積容量下
部電極 3を形成し,その上に第1層目絶縁膜 4, 動作半
導体層 5, チャネル保護膜 6を順次成膜する工程と,次
いで, 該ゲート電極直上の該チャネル保護膜を残すよう
に, 該チャネル保護膜をパターニングする工程と, 次い
で,該基板上に高濃度半導体からなるコンタクト層 7と
ソースドレイン電極用金属膜 8を順に成膜する工程と,
次いで, 該コンタクト層と該ソースドレイン電極用金属
膜 8をパターニングして, ドレイン電極8Dと, ソース電
極8Sと, 蓄積容量上部電極8Cを形成する工程と, 次い
で, 該基板上に透明樹脂からなる第2層目絶縁膜 9を被
着する工程と, 次いで,該ソース電極上および該蓄積容
量上部電極上において,第2層目絶縁膜にコンタクト孔
を形成する工程と, 次いで,該基板上に透明電極膜を成
膜して, 該蓄積容量上部電極と該ソース電極とを該透明
電極膜にコンタクトをとり, 該透明電極膜をパターニン
グして画素電極11を形成する工程とを有する薄膜トラン
ジスタマトリクスの製造方法,あるいは 2)前記第2層目絶縁膜 9が, 熱硬化性樹脂または光硬
化性樹脂または感光性樹脂である前記1)記載の薄膜ト
ランジスタマトリクスの製造方法,あるいは 3)透明絶縁性の基板 1上に形成された画素電極11を覆
って透明絶縁膜を成膜する薄膜トランジスタマトリクス
の製造方法により達成される。
To solve the above problems, 1) a gate electrode 2 and a storage capacitor lower electrode 3 are formed on a transparent insulating substrate 1 and a first insulating film 4 is formed thereon. A step of sequentially forming a semiconductor layer 5 and a channel protective film 6; and a step of patterning the channel protective film so as to leave the channel protective film immediately above the gate electrode. A step of sequentially forming a contact layer 7 made of a semiconductor and a metal film 8 for a source / drain electrode;
Next, a step of patterning the contact layer and the source / drain electrode metal film 8 to form a drain electrode 8D, a source electrode 8S, and a storage capacitor upper electrode 8C, and then a transparent resin is formed on the substrate. A step of depositing a second-layer insulating film 9, a step of forming a contact hole in the second-layer insulating film on the source electrode and the upper electrode of the storage capacitor, and a step of forming a contact hole on the substrate. Forming a transparent electrode film, contacting the storage capacitor upper electrode and the source electrode with the transparent electrode film, and patterning the transparent electrode film to form a pixel electrode 11. 2) The method of manufacturing a thin film transistor matrix according to 1) above, wherein the second insulating film 9 is a thermosetting resin, a photosetting resin, or a photosensitive resin. It is achieved by the method of manufacturing the thin film transistor matrix to form a transparent insulating transparent insulating film covering the pixel electrode 11 formed on the substrate 1.

【0015】[0015]

【作用】本発明では, 第2層目絶縁膜としてCVD SiN の
代わりに透明樹脂膜を用いる。これは本発明者が, 樹脂
膜はP-CVD 法に見られた成膜条件に依るコンタクト孔の
断面形状のばらつきがなく,逆テーパが形成されること
なく安定に塗布形成できることを確かめた結果を利用し
たものである。
In the present invention, a transparent resin film is used as the second insulating film instead of CVD SiN. This is the result of the present inventors confirming that the resin film does not have a variation in the cross-sectional shape of the contact hole due to the film formation conditions observed in the P-CVD method, and that it can be stably formed without forming a reverse taper. It is a thing using.

【0016】また,樹脂であるため,金属化合物の残渣
の還元はなく, さらに回転塗布によるため樹脂表面が平
坦化される。
Further, since the resin is used, the residue of the metal compound is not reduced, and the resin surface is flattened by spin coating.

【0017】[0017]

【実施例】【Example】

実施例(1) :図1(A) 〜(F) は本発明の実施例(1) の断
面図である。
Embodiment (1): FIGS. 1A to 1F are cross-sectional views of an embodiment (1) of the present invention.

【0018】図1(A) において,透明絶縁性基板として
ガラス基板 1上にスパッタリングにより厚さ1000ÅのAl
膜と厚さ1000ÅのCr膜を連続して成膜し,フォトリソグ
ラフィによりレジスト膜をパターニングした後, レジス
ト膜をマスクにしてエッチングしてゲート電極 2と蓄積
容量下部電極 3を形成する。
In FIG. 1A, a 1000 .mu.m thick Al is sputtered on a glass substrate 1 as a transparent insulating substrate.
A film and a Cr film having a thickness of 1000 mm are successively formed, the resist film is patterned by photolithography, and then etched using the resist film as a mask to form a gate electrode 2 and a storage capacitor lower electrode 3.

【0019】次いで, レジスト膜を剥離し,P-CVD 法に
より, 第1層目絶縁膜であるゲート絶縁膜および蓄積容
量誘電体膜として厚さ4000Åの窒化シリコン(SiN) 膜
4, 動作半導体層として厚さ 150Åのa-Si膜 5, チャネ
ル保護膜として厚さ1200ÅのSiN 膜 6を連続成長する。
ここで, 第1層目絶縁膜は, SiN 膜 4の代わりにALD法
によるアルミナ膜を用いてもよい。
Next, the resist film is peeled off, and a 4000-nm-thick silicon nitride (SiN) film is formed by a P-CVD method as a gate insulating film as a first insulating film and a storage capacitor dielectric film.
4, a 150-mm thick a-Si film as a working semiconductor layer, and a 1200-nm thick SiN film 6 as a channel protective film are continuously grown.
Here, instead of the SiN film 4, an alumina film formed by an ALD method may be used as the first insulating film.

【0020】図1(B) において,ゲート電極 2直上のチ
ャネル保護膜 6を残すようにパターニングする。図1
(C) において,基板上にコンタクト層として厚さ 600Å
の n+ 型a-Si層 7と厚さ1500Åのクロム(Cr)膜からなる
ソースドレイン電極用金属膜 8を連続成膜する。
In FIG. 1B, patterning is performed so that the channel protective film 6 immediately above the gate electrode 2 is left. FIG.
In (C), the contact layer is 600 mm thick on the substrate.
The n + -type a-Si layer 7 and a metal film 8 for a source / drain electrode made of a chromium (Cr) film having a thickness of 1500 ° are continuously formed.

【0021】図1(D) において,コンタクト層 7とソー
スドレイン電極用金属膜 8をパターニングして, ドレイ
ン電極8Dと, ソース電極8Sと, 蓄積容量上部電極8Cを形
成する。
In FIG. 1D, a contact layer 7 and a metal film 8 for source / drain electrodes are patterned to form a drain electrode 8D, a source electrode 8S, and a storage capacitor upper electrode 8C.

【0022】図1(E) において,第2層目絶縁膜 9とし
て,透明の熱硬化性樹脂膜を塗布し,キュア(熱処理)
を行う。熱硬化性樹脂は,例えばシリコン系またはエポ
キシ系熱硬化性樹脂を用い,回転塗布または印刷法によ
り塗布し,キュア後所定の厚さを 0.4μmにする。印刷
法の場合は基板上の接続端子に樹脂を付着しないように
してもよい。
In FIG. 1E, a transparent thermosetting resin film is applied as a second insulating film 9 and cured (heat treated).
I do. The thermosetting resin is, for example, a silicon-based or epoxy-based thermosetting resin, and is applied by spin coating or printing, and after curing, has a predetermined thickness of 0.4 μm. In the case of the printing method, the resin may not be attached to the connection terminals on the substrate.

【0023】次いで,フォトリソグラフィにより,ソー
ス電極と蓄積容量上に開口部を持つレジスト膜10を基板
上に形成する。図1(F) において,レジスト膜10をマス
クにして, 熱硬化性樹脂膜をエッチングしてコンタクト
孔を形成し,レジスト膜10を除去する。この際同時に接
続端子上の樹脂もエッチング除去する。
Next, a resist film 10 having an opening on the source electrode and the storage capacitor is formed on the substrate by photolithography. In FIG. 1F, using the resist film 10 as a mask, the thermosetting resin film is etched to form a contact hole, and the resist film 10 is removed. At this time, the resin on the connection terminals is also removed by etching.

【0024】次に, 樹脂上に画素電極膜として厚さ 700
ÅのITO 膜を成膜して, 蓄積容量上部電極8Cとソース電
極8Sとにコンタクトをとり, パターニングして画素電極
11とし,TFT マトリクスを形成する。
Next, a pixel electrode film having a thickness of 700
(1) ITO film is formed, and the storage capacitor upper electrode (8C) and the source electrode (8S) are contacted and patterned to form a pixel electrode.
11, and form a TFT matrix.

【0025】実施例(2) :実施例(1) では, 第2層目絶
縁膜 9として透明の熱硬化性樹脂膜を用いたが,これの
代わりに光硬化性樹脂, 例えば, UV樹脂を用い, 実施例
(1) と同様に成膜してもよい。
Embodiment (2): In Embodiment (1), a transparent thermosetting resin film was used as the second insulating film 9, but instead of this, a photocurable resin such as a UV resin was used. Use, Example
A film may be formed in the same manner as in (1).

【0026】実施例(3):図2は本発明の実施例(3)の
断面図である。2層目絶縁膜 9として感光性樹脂,例え
ば感光性ポリイミド樹脂を用い, フォトマスク12を用い
て, 感光性ポリイミド樹脂をパターニングしてソース電
極8Sと蓄積容量上部電極8C上にコンタクト孔を形成す
る。
Embodiment (3): FIG. 2 is a sectional view of an embodiment (3) of the present invention. A photosensitive resin, for example, a photosensitive polyimide resin is used as the second insulating film 9, and a photosensitive mask is used to pattern the photosensitive polyimide resin to form contact holes on the source electrode 8S and the storage capacitor upper electrode 8C. .

【0027】実施例(4):図3は本発明の実施例(4)の
断面図である。この例は,第2層目絶縁膜として本発明
の透明樹脂膜 9あるいは従来例のSiN膜14を用いてTFT
を形成した後, 基板表面に保護膜13として透明絶縁膜を
成膜するようにしている。この際, 接続端子上は保護膜
を成膜しないようにする。または成膜してもその後エッ
チング除去してもよい。保護膜13により基板表面は平坦
化され, 次工程が精度よく行える。
Embodiment (4): FIG. 3 is a sectional view of an embodiment (4) of the present invention. In this example, a TFT is formed by using the transparent resin film 9 of the present invention or the conventional SiN film 14 as the second insulating film.
After the formation, a transparent insulating film is formed as a protective film 13 on the substrate surface. At this time, no protective film is formed on the connection terminal. Alternatively, the film may be formed and then removed by etching. The substrate surface is flattened by the protective film 13, so that the next step can be performed with high accuracy.

【0028】次に実施例の効果を要約する。 (1) 2層目絶縁膜に樹脂膜を用いるため,成膜が容易
で, 成膜装置も簡単で小型化できる。また, 感光性樹脂
を用いた場合はレジストの塗布工程が省略できる。 (2) 樹脂は成膜条件が安定しているため,コンタクト孔
を形成する際に, 従来みられた逆テーパ形状をなくすこ
とができる。従って, コンタクト孔の形状が安定化する
ため,画素電極膜のITO 膜を成膜した際に断線を防止で
きる。 (3)樹脂であるため,金属酸化物の残渣の還元はなくな
り, 基板表面の導通を防止できる。 (4)樹脂膜は回転塗布に依るため基板表面を平坦化でき
る。 (5) 信頼性, 製造歩留が向上し,低価格化が実現でき
る。
Next, the effects of the embodiment will be summarized. (1) Since a resin film is used for the second insulating film, film formation is easy, and a film forming apparatus can be simplified and downsized. When a photosensitive resin is used, the step of applying a resist can be omitted. (2) Since the film formation conditions of resin are stable, it is possible to eliminate the conventional reverse taper shape when forming contact holes. Therefore, since the shape of the contact hole is stabilized, disconnection can be prevented when the ITO film of the pixel electrode film is formed. (3) Since it is a resin, reduction of metal oxide residues is eliminated, and conduction on the substrate surface can be prevented. (4) Since the resin film depends on spin coating, the substrate surface can be flattened. (5) Reliability and manufacturing yield can be improved, and lower prices can be realized.

【0029】[0029]

【発明の効果】本発明によれば,TFT 素子の製造におい
て,第2層目絶縁膜に開けるコンタクト孔を順テーパ形
状に形成でき且つ基板表面の導通化を防止することがで
きた。この結果,本発明は素子の信頼性と製造歩留の向
上に寄与することができた。
According to the present invention, in the manufacture of a TFT device, a contact hole formed in the second insulating film can be formed in a forward tapered shape, and conduction of the substrate surface can be prevented. As a result, the present invention was able to contribute to the improvement of the device reliability and the manufacturing yield.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の実施例(1) の断面図FIG. 1 is a sectional view of an embodiment (1) of the present invention.

【図2】 本発明の実施例(3)の断面図FIG. 2 is a sectional view of an embodiment (3) of the present invention.

【図3】 本発明の実施例(4)の断面図FIG. 3 is a sectional view of an embodiment (4) of the present invention.

【図4】 TFT マトリクスの平面図FIG. 4 is a plan view of a TFT matrix.

【図5】 従来のTFT 素子の製造工程を説明する断面図FIG. 5 is a cross-sectional view illustrating a manufacturing process of a conventional TFT element.

【図6】 コンタクト孔の断面図FIG. 6 is a sectional view of a contact hole.

【符号の説明】[Explanation of symbols]

1 透明絶縁性基板でガラス基板 2 ゲート電極 3 蓄積容量下部電極 4 第1層目絶縁膜(ゲート絶縁膜および蓄積容量誘電
体膜)でSiN 膜 5 動作半導体層でa-Si膜 6 チャネル保護膜でSiN 膜 7 コンタクト層で n+ 型a-Si層 8 ソースドレイン電極用金属膜 8D ドレイン電極 8S ソース電極 8C 蓄積容量上部電極 9 第2層目絶縁膜で透明樹脂膜 10 レジスト膜 11 画素電極でITO 膜
1 Glass substrate with transparent insulating substrate 2 Gate electrode 3 Lower electrode of storage capacitor 4 First layer insulating film (gate insulating film and dielectric film of storage capacitor) SiN film 5 Working semiconductor layer a-Si film 6 Channel protective film a transparent resin film 10 resist film 11 pixel electrode in the SiN film 7 contact layer is n + -type a-Si layer 8 source drain electrode metal film 8D drain electrode 8S source electrode 8C storage capacitor upper electrode 9 second layer insulating film ITO film

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 透明絶縁性の基板上にゲート電極と蓄積
容量下部電極を形成し,その上に第1層目絶縁膜, 動作
半導体層, チャネル保護膜を順次成膜する工程と, 次いで, 該ゲート電極直上の該チャネル保護膜を残すよ
うに, 該チャネル保護膜をパターニングする工程と, 次いで,該基板上に高濃度半導体からなるコンタクト層
とソースドレイン電極用金属膜を順に成膜する工程と, 次いで, 該コンタクト層と該ソースドレイン電極用金属
膜をパターニングして, ドレイン電極と, ソース電極
と, 蓄積容量上部電極を形成する工程と, 次いで, 該基板上に透明樹脂からなる第2層目絶縁膜を
被着する工程と, 次いで,該ソース電極上および該蓄積容量上部電極上に
おいて,第2層目絶縁膜にコンタクト孔を形成する工程
と, 次いで,該基板上に透明電極膜を成膜して, 該蓄積容量
上部電極と該ソース電極とを該透明電極膜にコンタクト
をとり, 該透明電極膜をパターニングして画素電極を形
成する工程とを有することを特徴とする薄膜トランジス
タマトリクスの製造方法。
A step of forming a gate electrode and a storage capacitor lower electrode on a transparent insulating substrate, and sequentially forming a first insulating film, a working semiconductor layer, and a channel protective film thereon; Patterning the channel protective film so as to leave the channel protective film immediately above the gate electrode, and then forming a contact layer made of a high concentration semiconductor and a metal film for source / drain electrodes on the substrate in this order Forming a drain electrode, a source electrode, and a storage capacitor upper electrode by patterning the contact layer and the source / drain electrode metal film; and forming a second layer of a transparent resin on the substrate. Forming a contact hole in the second insulating film on the source electrode and the upper electrode of the storage capacitor, and then forming a contact hole on the substrate. Forming an electrode film, contacting the storage capacitor upper electrode and the source electrode with the transparent electrode film, and patterning the transparent electrode film to form a pixel electrode. A method for manufacturing a thin film transistor matrix.
【請求項2】 前記第2層目絶縁膜が, 熱硬化性樹脂ま
たは光硬化性樹脂または感光性樹脂であることを特徴と
する請求項1記載の薄膜トランジスタマトリクスの製造
方法。
2. The method according to claim 1, wherein the second insulating film is a thermosetting resin, a photocurable resin, or a photosensitive resin.
【請求項3】 透明絶縁性の基板上に形成された画素電
極を覆って透明絶縁膜を成膜する工程を有することを特
徴とする請求項1記載の薄膜トランジスタマトリクスの
製造方法。
3. The method according to claim 1, further comprising the step of forming a transparent insulating film covering the pixel electrode formed on the transparent insulating substrate.
JP364093A 1993-01-13 1993-01-13 Method of manufacturing thin film transistor matrix Expired - Fee Related JP3239504B2 (en)

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Application Number Priority Date Filing Date Title
JP364093A JP3239504B2 (en) 1993-01-13 1993-01-13 Method of manufacturing thin film transistor matrix

Publications (2)

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JP3239504B2 true JP3239504B2 (en) 2001-12-17

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KR100303134B1 (en) * 1995-05-09 2002-11-23 엘지.필립스 엘시디 주식회사 Lcd and fabricating method for fabricating the same
US5994721A (en) 1995-06-06 1999-11-30 Ois Optical Imaging Systems, Inc. High aperture LCD with insulating color filters overlapping bus lines on active substrate
US5641974A (en) * 1995-06-06 1997-06-24 Ois Optical Imaging Systems, Inc. LCD with bus lines overlapped by pixel electrodes and photo-imageable insulating layer therebetween
JP3541014B2 (en) * 1995-08-11 2004-07-07 シャープ株式会社 Liquid crystal display
JP2001290172A (en) * 1995-08-11 2001-10-19 Sharp Corp Liquid crystal display
JP3541026B2 (en) * 1995-08-11 2004-07-07 シャープ株式会社 Liquid crystal display device and active matrix substrate
KR970011972A (en) 1995-08-11 1997-03-29 쯔지 하루오 Transmission type liquid crystal display device and manufacturing method thereof
TW409194B (en) 1995-11-28 2000-10-21 Sharp Kk Active matrix substrate and liquid crystal display apparatus and method for producing the same
US6682961B1 (en) 1995-12-29 2004-01-27 Samsung Electronics Co., Ltd. Thin film transistor array panel used for a liquid crystal display and a manufacturing method thereof
JPH1010583A (en) * 1996-04-22 1998-01-16 Sharp Corp Method of manufacturing active matrix substrate and active matrix substrate thereof
US6940566B1 (en) 1996-11-26 2005-09-06 Samsung Electronics Co., Ltd. Liquid crystal displays including organic passivation layer contacting a portion of the semiconductor layer between source and drain regions
US6310669B1 (en) 1997-05-26 2001-10-30 Mitsubishi Denki Kabushiki Kaisha TFT substrate having connecting line connect to bus lines through different contact holes
JP3270361B2 (en) * 1997-06-09 2002-04-02 日本電気株式会社 Thin film transistor array and method of manufacturing the same
JP2000081638A (en) * 1998-09-04 2000-03-21 Matsushita Electric Ind Co Ltd Liquid crystal display device and manufacturing method thereof
JP2001053283A (en) 1999-08-12 2001-02-23 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacturing method thereof
TW578028B (en) 1999-12-16 2004-03-01 Sharp Kk Liquid crystal display and manufacturing method thereof
JP3810681B2 (en) 2001-12-20 2006-08-16 シャープ株式会社 Thin film transistor substrate and liquid crystal display device
JP6155856B2 (en) * 2013-06-03 2017-07-05 住友化学株式会社 Display device

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