JP3240210B2 - Video system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

This invention relates to the field of televisions capable of displaying zoomed and / or cropped screens, and more particularly to televisions having a wide display format ratio screen. Alternatively, the present invention relates to a method and apparatus for horizontally panning a truncated screen.
Most of today's televisions have a format display ratio of 4: 3 horizontal width to vertical height.
The wide format display ratio more closely corresponds to the movie display format ratio, for example, 16: 9. The present invention is applicable to both direct-view television and projection television.

[0002]

BACKGROUND OF THE INVENTION Televisions having a format display ratio of 4: 3, often also referred to as 4.times.3, have limitations on how to display a single video signal source and multiple video signal sources. With the exception of experimental ones, the transmission of television signals from commercial broadcasters is broadcast with a display ratio of 4 × 3 format. Many viewers have found that the 4x3 display format is a movie
I think that there is no better than the wider format display ratio than in. Television with wide format display ratio
In addition to providing a more comfortable display, a wide display format signal source can be displayed in a corresponding wide display format. The movie looks like a movie without being truncated or distorted. The video source does not need to be truncated when converted from film to video, for example by a telecine device, or even by a television processor.

[0003] A television having a wide display format ratio displays both a normal display format signal and a wide display format signal in various forms, and a multi- screen display in which these format signals are combined. Suitable to do. However, using a screen with a wide display ratio has many problems. Such a common of problems, and change the display format ratios of multiple signal sources, the asynchronous but not least generates a timing signal that matches the video source to be displayed simultaneously,
Switching between a plurality of signal sources for performing multi-screen display and generating a high-resolution screen from a compressed data signal are sometimes performed.
These problems are solved in the widescreen television according to the invention. Widescreen televisions according to various configurations of the present invention can display high resolution single and multiple screen displays from selectable video format sources having the same or different format ratios with selectable display format ratios.

[0004] Televisions with a wide display format ratio are both interleaved and non-interleaved, and have basic,
That is, the present invention can be applied to a television system that displays a video signal at both a standard horizontal scanning frequency and a multiple thereof.
For example, a standard NTSC video signal is displayed by interlacing successive fields of each video frame, each generated by a raster scan at a basic or standard horizontal scan frequency of about 15,734 Hz. Basically scanning frequency for a video signal, f _H, various call it is made and so 1f _H or 1H. 1f
The actual frequency of the _H signal changes for different video formats. Efforts to improve the image quality of television equipment
Systems have been developed for displaying video signals sequentially in a non-interlaced manner. In progressive scanning, each display frame must be scanned at the same time allotted to scan one of the two fields of the interlaced format. AA-BB display without flicker requires each field to be scanned twice in succession. In each case, the horizontal scanning frequency must be twice the standard horizontal frequency. Such sequential scanning frequency for scanning the display or unsubstituted flickering is a variety of call you Toka 2f _H Toka 2H. For example, US Standard 2
The f _H scanning frequency is about 31,468 Hz.

[0005] In order to realize many display formats particularly suitable for widescreen television, considerable signal processing is required for the main video signal. Video de <br/> data, set according to the desired format, it is necessary to selectively compressing and decompressing. For example, in some cases, 4 × 3 NTS
C-video needs to be compressed by a factor of 4/3, ie 4: 3. In another case, for example, the video needs to be stretched to perform a horizontal zooming operation, which usually also involves vertical zooming. Horizontal zoom operations up to 33% can be performed by performing compression less than 4/3, for example, 5/4. For the S-VHS format, the luminance video bandwidth up to 5.5 MHz is:
The 1024F _H system clock is 8 MHz, the Nyquist frequency, i.e., since a large part of the folding frequency, to recalculate (The recalculate) the incoming video to a new pixel position, a sample interpolator is used.

The luminance data for the main signal is provided by a FIFO line memory for data compression (pause) and decompression (repetition) and an interpolator for recalculating sample values to smooth the data. Along the main signal path, including However, during compression and decompression,
The relative positions of O and the interpolator are different. According to the structure of the present invention, the switch or route selector inverts the form or topology of the main signal path with respect to the relative positions of the FIFO and the interpolator, so that two FIFOs and two interpolators are required. This eliminates the need to use two main signal paths. That is, these switches determine whether the interpolator precedes the FIFO (which is required during compression),
Is before the interpolator (this is required during decompression). These switches are responsive to a route control circuit responsive to the microprocessor.

[0007] The interpolator control circuit generates pixel position values, interpolator correction filter weighting information, and clock gating information for the luminance data. FIF
Pause (interrupt, or decimate) the O data,
It is clock gating information that causes compression by preventing samples from being written at a certain clock, or decompression by repeating FIFO data and reading some samples multiple times. .
For example, to handle 4/3 compression, where 4/3 represents the ratio of the number of input samples to the number of output samples, every fourth sample may not be written to the FIFO. The average slope of the ramp read from the luminance FIFO is 33% higher than the corresponding input ramp
Become steep. In this case, the reading time of the lamp is required to be 33% less than the time required to write the data . As a result, 4/3 compression is performed. Perform recalculation of luminance samples of data read from the F IFO is written into the FIFO so that smooth without becoming uneven is the function of the interpolator.

[0008] Decompression can be performed in exactly the opposite way as compression. In the case of compression, the write enable signal includes the output F
Clock gating information is added in the form of a prohibition pulse for writing to the IFO. For data expansion,
Clock gating information is attached to the read enable signal. This causes the data to be paused while being read from the FIFO. Luminance F
The average slope of the ramp read from the IFO is 33 times greater than the corresponding input ramp for 3/4 expansion or zoom.
%shallow. In this case, it is the function of the interpolator located after the FIFO to recalculate the sample data from a state having irregularities to a smooth state after expansion. In the case of decompression, data is interrupted when reading from the FIFO and when clocking to the interpolator. This is different from compression, where data is clocked continuously through the interpolator. In both cases, the clock gating operation can be easily performed in a synchronous manner. That is,
Event is generated based on the rising edge of 1024F _H system clock.

This arrangement for luminance interpolation has a number of advantages. Clock gating operations, ie, data decimation and data repetition, can be performed synchronously. Without switching the interpolator and FIFO positions using the switchable video data topology, the write or read clock would have to be double clocked due to data interruption or repetition. The term "double clocked" means that two data points must be written to the FIFO during one clock cycle, or two data points must be read from the FIFO during one clock cycle. is there. As a result, the write or read clock frequency must be twice the system clock frequency, so that the circuit configuration cannot operate in synchronization with the system clock. In addition, this switchable topology requires only one interpolator and one FIFO for both compression and decompression purposes. Without the video switching arrangement described here, double clocking can be avoided only with two FIFOs to achieve both compression and decompression functions. In that case, one FIFO for decompression must be placed before the interpolator, and one FIFO for compression must be placed after the interpolator.

The circuit for compressing and decompressing video data comprises a FIFO line memory and an interpolator. A timing circuit writes data to and reads data from the line memory and generates control signals for data compression and decompression. The interpolator smoothes the compressed or decompressed data in the FIFO line memory. A first signal path in which the switching network allows the line memory to be located in front of the interpolator for data decompression, and a second signal path in which the interpolator performs data compression prior to the line memory. Are selectively formed. The switching network is controlled, for example, by a microprocessor according to the selected display format requiring compression or decompression.

A video system for horizontal panning according to the present invention includes a video display having a wide format display ratio for displaying a video signal. A signal processor is provided having an interpolator and a first-in first-out (FIFO) line memory having asynchronous write and read ports for selectively expanding and compressing the screen represented by the data in the video signal. The screen is truncated to define a subset of the screen to be displayed by controlling the writing of data to the line memory (a set of some of the pixels of the original original screen). A microprocessor for the controller provides a control signal having a selectable duration and a selectable phase for the synchronous component of the video signal to select a boundary of the subset of the screen for display. The microprocessor can select this duration and phase in response to a user command.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Each of FIGS. 1 (a)-(i) shows some of the various combinations of single and multiple screen display formats that can be implemented in accordance with different configurations of the present invention. . These are chosen for explanation to facilitate the description of certain circuits making up a widescreen television in accordance with the arrangement of the present invention. The arrangement of the present invention is in some cases directed to the display format itself, apart from a specific circuit arrangement. For convenience of illustration and description, it is generally assumed that a normal display format for a video source or a video signal has a width-to-height ratio of 4 × 3, and generally a wide-screen display format for a video source or a video signal. Assume that the width to height ratio is 16 × 9. The configuration of the present invention is not limited by these definitions.

FIG. 1A shows a direct-view or projection television having a display ratio of a normal format of 4 × 3. 16x9 format display ratio screen is 4x3
When transmitted as a format display ratio signal, black bars appear at the top and bottom. This is generally called a letterbox (letterbox) format. In this case, the screen viewed is small with respect to the display area available for display.
Alternatively, the source of the 16 × 9 format display ratio is converted prior to transmission to fill the vertical direction of the viewing plane of the 4 × 3 format display. However, in that case, considerable information is truncated from the left and / or right. In yet another method, the mailbox format can be stretched vertically without stretching horizontally, but this causes distortion due to stretching in the vertical direction. None of these three methods are particularly attractive.

FIG. 1B shows a 16 × 9 screen. A video source with a display ratio of 16x9 format is perfectly displayed without truncation and without distortion. 16 × 9 format display ratio letterbox display (which is in the form of a 4 × 3 format display ratio No. signal originally) is to perform large display with sufficient vertical resolution, Senbaika (line doubling ) Or line addition (line addition). The widescreen television according to the present invention can display such a 16 × 9 format display ratio signal regardless of the primary video source, the secondary video source, or an external RGB source.

FIG. 1C shows a main signal of a 16 × 9 format display ratio in which an insertion screen of a 4 × 3 format display ratio is inserted and displayed. If the primary and secondary video signals are both 16 × 9 format display ratio sources, the insert screen also has a 16 × 9 format display ratio. The insert screen can be displayed at a number of different locations.

FIG. 1D shows a display format in which the main and sub video signals are displayed as screens of the same size. Each display area has an 8 × 9 format display ratio,
This is, of course, different from both 16 × 9 and 4 × 3.
In order to display a 4 × 3 format display ratio source in such a display area without horizontal or vertical distortion, the left and / or right sides of the signal must be truncated. If you tolerate some aspect ratio distortion due to horizontal squeeze of the screen, you can show more by reducing screen truncation. As a result of the horizontal stuffing, things on the screen become elongated in the vertical direction. The widescreen television of the present invention can perform any combination of truncation and aspect ratio distortion, from maximum truncation processing without any aspect ratio distortion to no truncation with maximum aspect ratio distortion.

[0017] the sub-video signal processing paths have data sampling limitations, display the same size as the generation of high-resolution screen from the main video signal becomes complicated. Various methods can be developed to eliminate such complications.

FIG. 1E shows a display format in which the display ratio screen of the 4 × 3 format is displayed at the center of the display ratio screen of the 16 × 9 format. Black bars appear on both sides.

FIG. 1F shows a display format in which one large 4 × 3 format display ratio screen and three small 4 × 3 format display ratio screens are simultaneously displayed.
Small screens outside the perimeter of a large screen are sometimes PI
P, that is, POP, not an in-screen screen (parent-child screen)
That is, it is called an off-screen screen. The term PIP or Picture-in-Picture is used in this specification for these two display formats. If two tuners widescreen television is provided, even if provided inside both, 1
Even if one is provided internally and one is provided externally, for example on a video cassette recorder, two of the display screens can display motion in real time according to the video source. The remaining screens can be displayed in the still screen format.
It can be understood that three or more moving picture planes can be displayed by adding a tuner and a sub signal processing path. Also, the positions of the large screen and the three small screens can be switched as shown in FIG.

FIG. 1 (h) shows another example in which the 4 × 3 format display ratio screen is displayed at the center and six small 4 × 3 format display ratio screens are displayed in columns on both sides.
As in the above-described format, a wide-screen television having two tuners can display two moving image planes. Then, the remaining 11 screens are displayed in the still screen format.

FIG. 1 (i) shows a grid-like display format of 12 4 × 3 format display ratio screens. Such a display format is particularly suitable for a channel selection guide, where each screen is at least a static screen from a different channel. As in the previous example, the number of moving screens depends on the number of available tuners and signal processing paths.

The various formats shown in FIG. 1 are exemplary and not limiting, and are shown in the remaining figures.
This can be realized by a wide screen television described in detail below.

The widescreen television by the configuration of the present invention, 2f _H general block diagram of what is the horizontal scanning is shown in FIG. 2, it is shown generally at 10. The television 10 generally comprises a video signal input 20, a chassis or TV microprocessor 216, a wide screen processor 30, 1f.
_H- 2f _H converter 40, deflection circuit 50, RGB interface 60, YUV-RGB converter 240, picture tube drive circuit 242, direct-view or projection tube 244, and power supply
Contains 70. The grouping of various circuits into different functional blocks is for convenience of explanation,
It is not intended to limit the physical positional relationship between such circuits.

[0024] The video signal input 20 is adapted to receive a plurality of composite video signals from different video sources. Video signals as the main video signal and the sub video signal, can be switched to the selected択的for display. RF switch 204 has two antenna inputs ANT1 and ANT2. These inputs represent inputs for both reception by the radio broadcast antenna and reception from the cable.
The RF switch 204 controls which antenna input is supplied to the first tuner 206 and the second tuner 208. An output of the first tuner 206 is an input to the one-chip 202. One chip 202 performs many functions related to tuning control, horizontal and vertical deflection control, and video control. One chip shown is TA77 for industrial use
30. Baseband video signal VIDEO generated in one chip from the signal from first tuner 206
OUT is an input to the video switch 200 and the TV1 input of the wide screen processor 30. The other baseband video input to video switch 200 is AUX1
And AUX2. These inputs can be used for video cameras, laser disk players, video tape players, video games, and the like. The output of the video switch 200 controlled by the chassis or TV microprocessor 216 is the switching video (S WITCH).
ED VIDEO ) . This SWITCH
ED VIDEO is provided as a separate input to widescreen processor 30.

Referring to FIG. 3, widescreen pro <br/> switch SW1 in set Sa 30, Y / C decoder 21
One of the TV1 signal and the SWITCHED VIDEO signal is selected as the SEL COMP OUT video signal to be input to 0. Y / C decoder 210 can be implemented in the form of an adaptive comb filter. Y / C decoder 21
To 0, two more video sources S1 and S2 are also input. S1 and S2 each represent a different S-VHS source,
Each consists of separate luminance and chrominance signals. With some adaptive comb filters Y /
Switches that are incorporated as part of the C decoder or that may be implemented as separate switches are TV
In response to the microprocessor 216, Y_M and C_
A pair of luminance and chrominance signals is selected as the output indicated as IN. The selected pair of luminance and chrominance signals are then considered as main signals and processed along the main signal path. Signal notations containing _M or _MN represent the main signal path. Chrominance signal C_IN is I <br/> by the wide screen-processor 30, is returned to again one chip, the color difference signal U_M and V
_M is generated. Here, U is equivalent to (RY), and V is equivalent to (BY). Y_M, U
The _M and V_M signals are converted to digital form by a widescreen processor for subsequent signal processing.

Functionally, the wide screen processor 3
A second tuner 208, defined as part of 0, generates a baseband video signal TV2. The switch SW2 is
As inputs to the Y / C decoder 220, the TV2 signal and S
Select one of the WITCHED VIDEO signals. Y / C
Decoder 220 can be implemented as an adaptive comb filter. The switches SW3 and SW4 are connected to the Y / C decoder 22.
0 luminance and chrominance outputs and Y_
One of the luminance and chrominance signals of the external video source indicated by EXT and C_EXT is selected. Y_EXT and C_EXT signals that correspond to S-VHS input S1. Y
/ C decoder 220 and switches SW3 and SW4, as is done with some adaptive comb filters,
They may be combined. The outputs of switches SW3 and SW4 are
After this, it is considered as a sub signal and is processed along the sub signal path. The selected luminance output is shown as Y_A. Signal notations including _A, _AX and _AUX are used for the sub-signal path. The selected chrominance is converted into color difference signals U_A and V_A. The Y_A, U_A and V_A signals are converted to digital form for subsequent signal processing. The arrangement for switching the video signal sources in the main and sub signal paths provides greater flexibility in how to select video sources for different parts of different screen display formats.

Composite sync signal COMP corresponding to Y_M
SYNC is supplied to the wide screen-processor 30 or we sync separator 212. Horizontal and vertical synchronization components H and V
Is input to the vertical countdown circuit 214. The vertical countdown circuit generates a VERTICAL RESET signal that is provided to widescreen processor 30. Widescreen-processor 30
Generates an internal vertical reset output signal INT vert RST OUT to be supplied to the RGB interface 60. A switch in the RGB interface 60 selects between the internal vertical reset output signal and the vertical synchronization component of the external RGB source. The output of this switch is the deflection circuit 5
0, the selected vertical synchronization component SEL_VER supplied to
T_SYNC. Horizontal and vertical synchronizing signals of the auxiliary video signal is generated by sync separator 250 in the wide screen-processor 30.

[0028] _1f H -2f _H converter 40 serves to convert non-interlaced signal sequentially scanned interlaced video signal. For example, each horizontal line is displayed twice, or an additional set of horizontal lines is generated by interpolation of adjacent horizontal lines in the same field. In some cases, whether to use the previous line or the interpolated line depends on the level of motion detected between adjacent fields or adjacent frames. The conversion circuit 40 operates in association with the video RAM 420 . This video RA M
420 is used to store one or more fields of the frame for sequential display. Y
The converted video data as the —2f _H , U — 2f _H and V — 2f _H signals is provided to the RGB interface 60.

The RGB interface 60, shown in detail in FIG. 14, for display by the video signal input section, allow conversion video data or <br/> Selection of external RGB video data. External RGB signal is a wide format display ratio signal which is adapted for 2f _H scanning. The vertical synchronization component of the main signal is sent to the RGB
Tsu Doo output (I NT VERT RST OU T) and to be fed, vertically chosen synchronization _{(f vm} or f
_vext ) can be supplied to the deflection circuit 50. By the operation of this wide screen television, an internal / external control signal INT / EXT is generated, and an external RG
The user can select the B signal. However, when such an external RGB signal does not exist, an external RGB signal is output.
Choosing a signal input can cause vertical collapse of the raster and damage to the cathode ray tube or projection tube. Therefore, the RGB interface circuit detects an external synchronization signal in order to invalidate selection of an external RGB input that does not exist. WSP microprocessor 340 also
Perform color and tone control for the external RGB signal.

The wide screen processor 30 includes a picture-in-picture processor 320 that performs special signal processing on the sub-video signal. The term screen-in-screen is sometimes abbreviated as PIP or pix-in pix. Gate array 300 combines the primary and secondary video signal data in various display formats, as shown in the examples of FIGS. 1 (b)-(i). Picture-in-picture processor 320 and gate array 300 are under the control of a widescreen processor microprocessor (WSP μP) 340. Microprocessor 340 is responsive to TV microprocessor 216 via a serial bus. The serial bus includes four signal lines for data, clock signals, enable signals, and reset signals. The widescreen processor 30 also provides a three level sandcastle (castle made of sand) signal as a composite vertical blanking /
Reset (COMPOSITE VERTICAL B
LANKING / RESET) to generate a signal. Alternatively, the vertical blanking signal and the reset signal may be generated as separate signals. Composite blanking signal is supplied to the RGB interface 60 by the video signal input section.

The deflection circuit 50 is shown in more detail in FIG. 13 is a widescreen-processor 30 or we vertical reset signal, the 2f _H horizontal synchronizing signal is selected from the RGB interface 60, also widescreen-processor 30
Receive pressurized et additional control signal. The additional control signal relates to horizontal phase adjustment, vertical size adjustment, and left and right pin adjustment. Deflection circuit 50 is 2f _H fly wide back pulse screen processor 30,1f _H -
It is supplied to the 2f _H converter 40 and the YUV-RGB converter 240.

The operating voltage for the entire widescreen television is generated, for example, by a power supply 70 which can be powered by an AC mains power supply.

The wide screen processor 30 is shown in more detail in FIG. The main <br/> principal components of the wide screen-processor 30, the gate array 300, picture-in-picture circuit 30
1, an analog-to-digital converter and a digital-to-analog converter 342, 346, a second tuner 208, a wide screen processor / microprocessor 340, and a wide screen output encoder 227. 1f _H and 2f _H detailed portion of the common widescreen processor both to the chassis, for example, PIP circuit, but is shown in Figure 4. The in-screen processor 320 which forms an important part of the PIP circuit 301 is shown in more detail in FIG. FIG. 6 shows the gate array 300 in more detail. The numerous elements that make up the main and sub signal paths shown in FIG. 3 have already been described in detail.

The second tuner 208 includes an IF stage 224
And an audio stage 226 are provided. Also, the second tuner 208 operates with the WSP μP 340.
WSP μP 340 includes an input / output I / O section 340A and an analog output section 340B. I / O section 340A
Is a color tone control signal and a color control signal.
An INT / EXT signal for selecting a GB video source and a control signal for switches SW1 to SW6 are supplied.
I / O unit, and in order to protect the deflection circuit and cathode ray tube, EXT SYNC of RGB interface 60 or al
Monitor the DET signal. Analog output unit 340B
Supplies control signals for vertical size, left / right adjustment and horizontal phase through respective interface circuits 254, 256 and 258.

The gate array 300 by combining the video information from the main and auxiliary signal paths, Fukugo widescreen display, for example, although shown in the individual parts of the FIG. 1 1
Work to make one. Clock information for the gate array is provided by a phase locked loop 374 that operates in cooperation with a low pass filter 376. The main video signal is supplied in analog form to the widescreen processor in the YUV format as signals designated Y_M, U_M and V_M. These main signals are converted from analog to digital form by analog-to-digital converters 342 and 346 shown in more detail in FIG.

The color component signals are common notation U and V
It is indicated by, these, R-Y or B -Y
Signals or I and Q signals. System clock frequency is 1024f _H (This is about 16M
Since Hz Der Ru) of the sample bandwidth luminance is limited to 8 MHz. U and V signals are 500KH
z, or because it is limited to 1.5MHz for wide 1, sampling of the color component data, one analog - may be performed by the digital converter and an analog switch. The selection line UV_MUX for this analog switch, ie, the multiplexer 344, is an 8 MHz signal obtained by dividing the system clock by two. A one clock wide line start SOL pulse synchronously resets this signal to zero at the start of each horizontal video line. Then U
The state of the V_MUX line is inverted every clock cycle through the horizontal line. Since the length of the line is an even multiple of the clock cycle, once initialized, the state of the UV_MUX is uninterrupted, 0, 1, 0, 1,.
And change. Analog to digital converters 342 and 346
The Y and UV data streams from are shifted because the analog-to-digital converters each have a delay of one clock cycle. To accommodate this data shift, the clock gate information from the interpolator controller 349 of the main signal processing path 304 must be similarly delayed. If this clock gating information is not delayed, the UV data will not be correctly paired when the deletion occurs. This is important because each UV pair represents one vector. U component of a vector <br/> or found that when the V component pair from the other vector, color shift occurs. V from preceding pair
The sample is deleted along with the current U sample. This UV multiplex method is referred to as 2: 1: 1 because there are two luminance samples for each color component (U, V) sample pair. The Nyquist frequency for both U and V is effectively reduced to one-half the luminance Nyquist frequency. Therefore, the Nyquist frequency of the output of the analog-to-digital converter for the luminance component is 8 MHz, while the Nyquist frequency of the output of the analog-to-digital converter for the color components is 4M.
Hz.

The PIP circuit and / or the gate array
Means may be included for enhancing the resolution of the sub-data even with data compression. For example, paired
Pixel compression and dithering and Dedizarin grayed (Gyakude
Many data reduction and data recovery schemes have been developed , including dithering . In addition, different dithering sequences with different numbers of bits and different anti-pixel compressions with different numbers of bits have been considered. One of a number of specific data reduction and recovery schemes can be selected by the WSP μP 340 to maximize the resolution of the displayed video for each specific screen display format.

[0038] Getoare over 300 includes interpolators which operate in conjunction with line memories, which can be implemented as FIFO356 and 358. The interpolator and FIFO are used to resample the main signal as needed. A sub-signal can be resampled by a separate interpolator. Clock and synchronizing circuits in Getoare over 300 is a combination of primary and secondary signals, Y_MX, U_MX and V
It controls the data manipulation of both the main and secondary signals, including producing one output video signal having the _MX component. The output components are converted to analog form by digital-to-analog converters 360, 362 and 364. Y, the signal in analog form indicated by U and V, for conversion to non-interlaced _scanning, are supplied to the 1f H -2f _H converter 40.
The Y, U, and V signals are converted into Y signals by the encoder 227.
/ C format, and outputs the wide format ratio output signal Y_OUT_EXT to the jack of the panel.
-/ C_OUT_EXT is generated. Switch SW5
Synchronizes the synchronization signal for encoder 227 with C_SYNC_MN from the gate array and C_SYNC_MN from the PIP circuit.
Select from SYNC_AUX. The switch SW6 outputs Y_M as a synchronization signal for widescreen panel output.
And C_SYNC_AUX.

The portion of the horizontal synchronization circuit is shown in more detail in FIG. Phase comparator 228 forms part of a phase locked loop including low pass filter 230, voltage controlled oscillator 232, divider 234, and capacitor 236. Voltage controlled oscillator 232, in response to a ceramic resonator or equivalent 238, operates at 32f _H. The output of the voltage controlled oscillator is divided by 32 and provided to phase comparator 228 as a second input signal of the appropriate frequency. The output of divider 234 is a 1f _H REF timing signal. 32f _H REF timing signal and 1f _H REF
The timing signal is supplied to the 1/16 counter 400. The 2f _H output is provided to pulse width circuit 402. Presetting the divider 400 with the 1f _H REF signal ensures that the divider operates synchronously with the phase locked loop of the video signal input. The pulse width circuit 402 ensures that the 2f _H -REF signal has a sufficient pulse width to allow the phase comparator 404, for example, CA1391, to operate properly. Phase comparator 404
Are the low pass filter 406 and the 2f _H voltage controlled oscillator 4
08 constitutes a part of the second phase locked loop. The voltage controlled oscillator 408 generates an internal 2f _H timing signal, this signal is used to drive the display to be sequentially scanned. The other input signal to phase comparator 404 is a 2f _H flyback pulses or a timing signal associated thereto. The use of a second phase locked loop including phase comparator 404 helps to ensure that each 2f _H scan period is symmetric within each 1f _H period of the input signal. Failure to do so will result in raster separation, for example, half of the video lines will shift to the right and half of the video lines will shift to the left.

FIG. 13 shows the deflection circuit 50 in detail. Circuit 500 is provided to adjust the vertical size of the raster according to the required amount of vertical overscan required to achieve different display formats. As shown diagrammatically, a constant current source 502 supplies a constant amount of current _IRAMP that charges a vertical ramp capacitor 504.
Transistor 506 is coupled in parallel with the vertical ramp capacitor and periodically discharges this capacitor in response to a vertical reset signal. Without any adjustment, the current I _RAMP gives the raster the largest possible vertical size. This corresponds to the amount of vertical overscan required to fill a widescreen display with a signal source having an enlarged 4x3 format display ratio, as shown in FIG. 1 (a). If a smaller vertical raster size is required, adjustable current source 508 shunts a variable amount of current I _ADJ from I _RAMP to charge vertical ramp capacitor 504 more slowly to a smaller peak value. The variable current source 508 is responsive to a vertical size adjustment signal, eg, in analog form, generated by the vertical size control circuit. Vertical size adjustment circuit 5 00 is independent of a manual vertical size adjustment circuit 5 10, the manual vertical size adjustment can be performed by a potentiometer or back panel adjustment knob. In either case, the vertical deflection coil 512 receives an appropriately sized drive current. Horizontal deflection phase adjustment circuit 518 is given by the left and right pin correction circuit 514,2F _H phase locked loop 520 and horizontal output circuit 516.

FIG. 14 shows the RGB interface 60 in more detail. The final displayed signal is
The output is selected from the output of the 1f _H -2f _H converter 40 and the external RGB input. In order to explain the wide screen television described here, it is assumed that an external RGB input is a progressive scanning source having a wide format display ratio. An external RGB signal and a composite blanking signal from the video signal input unit 20 are input to the RGB-YUV converter 610. External RGB
An external 2f _H composite sync signal for the signal is input to an external sync signal separator 600. The selection of the vertical synchronizing signal is performed by the switch 608. The selection of the horizontal synchronizing signal is performed by the switch 604. The selection of the video signal is performed by the switch 606. Switches 604, 60
6, 608 each respond to internal / external control signals generated by WSP μP 340. Whether to select an internal video source or an external video source is a user choice. However, if an external RGB source is not connected or turned on and the user inadvertently selects such an external source, or if the external source disappears, the vertical raster will collapse, It can cause serious damage to the cathode ray tube. Therefore, the external synchronization detector 602 detects the presence of the external synchronization signal. In the absence of this signal, a switch disable control signal is sent to each switch 604, 606, 608 to prevent such an external RGB source from being selected when there is no signal from the external RGB source. The RGB-YUV converter 610 is also a WS
A color tone and color control signal is received from P μP 340.

[0042] The wide screen television according to arrangement of the present invention, although not shown, may also be implemented in place of 1f _H horizontal scanning of 2f _H horizontal scanning. 1f
_{If an H} circuit is used, neither a 1f _H -2f _H converter nor an RGB interface is required. Therefore, the longer the means for displaying the external wide format display ratio RGB signal 2f _H scanning frequency. The wide screen processor for the 1f _H circuit and the in-screen screen processor are very similar. The gate array may be substantially the same, but will not use all inputs and outputs. The various resolution enhancement schemes described herein generally apply to 2f _{H H} , whether or not the television operates at 1 f _H scan.
It can be adopted regardless of whether it operates by scanning.

[0043] Figure 4 is a block diagram depicting in further detail the wide screen processor 30 shown in FIG. 3 that can be the same for both the 1f _H and 2f _H chassis. The in-screen screen processor 3 in which the Y_A, U_A and V_A signals can include a resolution processing circuit 370
It becomes the input to the 2 0. A wide screen television according to one embodiment of the present invention can expand and compress video. The special effects realized by the various composite display formats, some of which are shown in FIG.
20 generated. The processor 320 can be configured to receive the resolution processed data signals Y_RP, U_RP, and V_RP from the resolution processing circuit 370. Resolution processing is not always necessary and occurs during the selected display format. FIG. 5 shows the in-screen processor 320 in more detail. The main components of the in-screen screen processor are an analog-digital converter section 322, an input section 324, and a high-speed switch (FSW).
And a bus unit 326, a timing and control unit 328, and a digital-analog conversion unit 330. Details of the timing and control unit 328 are shown in FIG.

The in-screen screen processor 320, for example,
It can be implemented as an improved version of the basic CPIP chip developed by Thomson Consumer Electronics, Inc. Details of this basic CPIP chip can be found in The CTC 140, published by Thomson Consumer Electronics, Inc. of Indianapolis, Indiana.
Picture in Picture (CPIP) Te
mechanical Training Manual (C
TC 140 Screen-in-Screen (CPIP) Technical Training Manual). Numerous features or special effects are possible. The following is an example. The basic special effect is such that a small screen is placed on a large screen as shown in FIG. These large and small screens may be from the same video signal or different video signals, and may be interchanged. Generally, audio signals are always switched to correspond to a large screen.
Small screen can either be moved to any position on the screen, or moves to a number of predetermined positions may <br/> Rukoto. The zoom effect increases or decreases the size of the small screen to, for example, any of a number of preset sizes. At some point, for example, FIG.
In the case of the display format shown in (d), large and small screens have the same size.

In the case of the single screen mode, for example, the mode shown in FIG. 1B, FIG. 1E or FIG. : 1
5.0: Ru can zoom-in stepwise in 1 ratio range. The's Mumodo, the user searches the screen contents, or panning, the image on the screen can be moved in different regions of the screen. In any case, a small screen, a large screen, or a zoomed screen can be displayed as a still screen (still screen format). This feature allows for a strobe format that repeatedly displays the last nine frames of the video on the screen. The frame repetition rate can vary from 30 frames to 0 frames per second.

An in-screen processor used in a widescreen television according to another configuration of the present invention differs from the current configuration of the basic CPIP chip described above. If the basic CPIP chip is used with a television having a 16 × 9 screen and no video speed-up circuit is used, a wide 16 × 9 screen is scanned, effectively 4/3 times in the horizontal direction. , Which results in aspect ratio distortion. Things on the screen are elongated horizontally. When an external speed-up circuit is used, no aspect ratio distortion occurs, but the screen is not displayed on the entire screen.

Existing in-screen processors based on the basic CPIP chip as used in ordinary television are operated in a special way with some undesirable consequences. Incoming video is sampled by the clock of 640 f _H which is locked to the horizontal synchronizing signal of the main video source. That is, the data stored in the video RAM associated with the CPIP chip is not orthogonally sampled for the incoming secondary video source. This is a fundamental limitation on field synchronization by the basic CPIP method. The non-orthogonal nature of the input sampling rate causes skew errors in the sampled data. This limitation is the result of using video RAM with a CPI chip that must use the same clock to write and read data. For example, video RAM 35
When data from the video RAM, such as 0, is displayed, the skew error appears as random jitter along the vertical edge of the screen and is generally considered very objectionable.

Unlike the basic CPIP chip, the in-screen processor 320 according to the configuration of the present invention is modified to asymmetrically compress video data in one of a plurality of display modes. In this mode of operation, the screen is compressed 4: 1 in the horizontal direction and 3: 1 in the vertical direction. With this asymmetric compression mode, a screen having an aspect ratio distortion is generated and stored in the video RAM.
Things in the screen are packed horizontally. However, if these screens are read out and displayed on a 16 × 9 format display ratio screen as usual, for example, in channel scan mode, the screens will look correct. This screen fills the screen and has no aspect ratio distortion. Using the asymmetric compression mode according to this aspect of the invention, it is possible to create a special display format on a 16 × 9 screen without using an external speed-up circuit.

FIG. 11 is a block diagram of the timing and control unit 328 of the in-screen screen processor in which, for example, the above-described CPIP chip has been changed. Decimation (deci) for performing asymmetric compression as
328C ) . The remaining display modes can generate sub-screens of different sizes.
Each of the horizontal and vertical decimation circuits is WSP μP
It includes a counter programmed to determine the compression factor from a table of values under the control of 340. The range of values can be 1: 1, 2: 1, 3: 1, etc. The compression factor can be symmetric or asymmetric depending on how the table is constructed. The compression ratio is controlled by WSP
Under the control of μP 340, this can be done by a fully programmable general purpose decimation circuit.

[0050] In all screen PIP modes, picture-in-picture processor 320 work with free-running oscillator 348, for example receives the Y / C input from a decoder, which may be adapted shape line comb filter, the signals Y, U , V color components to generate horizontal and vertical sync pulses.
These signals are processed by the in-screen screen processor 320 for various full-screen modes such as zoom, freeze, channel scan, and the like. For example, during the channel scan mode, the horizontal and vertical sync from the video signal input is such that the sampled signal (different channels) has sync pulses that are not related to each other, and is also apparently a point in time that is random in time. Will be interrupted many times. Thus, the sample clock (and the read / write video RAM clock) is determined by the free running oscillator. For static and zoom modes, the sample clock is locked to the incoming video horizontal sync signal. In these special cases, the frequency of the incoming video horizontal sync is the same as the display clock frequency.

[0051] Referring again to FIG. 4, picture-in-picture process <br/> Tsu support 320 or these analog form of Y, U, V and C_
The SYNC (composite sync) output can be re-encoded in encoder circuit 366 into a Y / C component. The encoder circuit 366 operates in cooperation with the 3.58 MHz oscillator 380. This Y / C_PIP_ENC signal is
The / C component may be connected to a Y / C switch (not shown) that enables the / C component to be used instead of the Y / C component of the main signal. From this point forward, the PIP encoded Y, U, V and sync signals are the basis for horizontal and vertical timing in the rest of the chassis. This operation mode is suitable for executing the PIP zoom mode based on the operation of the interpolator and FIFO in the main signal path.

Still referring to FIG. 5, the in-screen processor 320 includes an analog-to-digital converter 322, an input unit 324, a high-speed switch FSW and a bus control unit 32.
6, a timing and control unit 328, and a digital-analog conversion unit 330. Generally, the in-screen processor 320 digitizes the video signal into luminance (Y) and color difference signals (U, V), subsamples the result, and stores it in the 1 megabit video RAM 350 as described above. In-screen screen processor 32
Although the video RAM 350 attached to 0 has a memory capacity of 1 megabit, it is not large enough to store an entire field of video data in 8-bit samples. Increasing memory capacity would be costly and would require more complex operating circuitry.
Reducing the number of bits per sample of the sub-channel means reducing the quantization resolution or bandwidth for the main signal, which is processed with 8-bit samples throughout. This effective bandwidth reduction is not usually a problem when the sub-display screen is relatively small, but it is a problem when the sub-display screen is relatively large, for example, the same size as the main display screen. Could be. The resolution processing circuit 370 can selectively implement one or more concepts for increasing the quantization resolution or effective bandwidth of the sub-video data. For example, a number of data reduction and data recovery schemes have been developed, including anti-pixel compression and dithering and inverse dithering. The dithering circuit is located downstream of the video RAM 350, for example, in the sub-signal path of the gate array, as described in detail below. In addition, different dithering and inverse dithering sequences with different numbers of bits and different anti-pixel compression with different numbers of bits are possible. In order to maximize the resolution of the displayed video for each particular screen display format, one of a number of specific data reduction and recovery concepts may be implemented using W
It can be selected depending on SP μ P340.

The luminance and color difference signals are stored in 8: 1: 1 6-bit Y, U, V format. That is, each component is quantized into 6-bit samples. There are eight luminance samples for each pair of color difference samples. Picture-in-picture processor 320, the incoming video data is caused to operate in a mode as samples in locked to incoming sub video synchronization signal 640 f _H clock frequency. In this mode, the data stored in the video RAM is sampled orthogonally. When data is read from the video RAM350 in picture-in-picture processor, the data is read using the same 640 f _H clock locked to the incoming auxiliary video signal. However, although this data is sampled and stored orthogonally, and can be read orthogonally, it cannot be displayed orthogonally directly from video RAM 350 due to the asynchronous nature of the primary and secondary video sources. The primary and secondary video sources are considered to be synchronized only when they are displaying signals from the same video source.

To synchronize the sub-channel, which is the data output from the video RAM 350, with the main channel, it is necessary to perform further processing. Referring again to FIG. 4, two 4-bit latches 352A and 352B are used to reassemble the 8-bit data block from the 4-bit output port of the video RAM. The 4-bit latches, the data clock frequency from 1280f _H 640
down to f _H.

Generally, the video display and deflection system is synchronized to the main video signal. As mentioned above, the main video signal must be speeded up to satisfy the widescreen display. The secondary video signal must be vertically synchronized with the first video signal and the video display. The auxiliary video signal can be delayed by a fraction of one field period in the field memory and expanded in the line memory. The synchronization of the sub-video data with the main video data is performed by using the video RAM 350 as a field memory and using a first-in first-out (FIFO) line memory device 354 for signal expansion. The size of the FIFO 354 is 2048 × 8.
The size of the FIFO is related to the lowest line storage capacity that is reasonably considered necessary to avoid read / write pointer collisions. Read / write pointer collisions occur when old data is read from the FIFO before new data can be written to the FIFO. Collision of the read / write pointer is, also, before you come when the old data is read from the FIFO, write it heavy the new data on the memory (overwr
It occurs at the time of (item).

8-bit DA from video RAM 350
TA_PIP data block, the same picture-in-picture as that used to sample the video data processor 3
6 40f _H clock 20, i.e., using a 640 f _H clock which is locked to the auxiliary signal rather than the main signal 2048
Written to × 8 FIFO 354. FIFO 354 is
10 locked to horizontal sync component of main video channel
It is read using the display clock of 24f _H. By using a multiple line memory (FIFO) with independent read and write port clocks, data sampled orthogonally at a first frequency can be displayed orthogonally at a second frequency. However, by reading and writing the two clocks have the asynchronous nature, it is necessary to take measures to avoid collision of read / write pointer.

The main signal path 304, the sub signal path 306, and the output signal path 312 of the gate array 300 are shown in block diagram form in FIG. The gate array also has a clock /
It includes a synchronization circuit 320 and a WSP μP decoder 310. WSP DATA of WSP μP decoder 310
The data and address output lines indicated by are also supplied to the above-described main circuit and signal path as well as the in-screen screen processor 320 and the resolution processing circuit 370. Whether a circuit forms part of the gate array is almost a matter of convenience to facilitate the description of the configuration of the present invention.

The gate array acts to expand, compress, or truncate the main video channel as needed to implement different screen display formats. The luminance component Y_MN is a first-in-first-out (FIFO) time corresponding to the length of the interpolation of the luminance component.
It is stored in the line memory 356. The combined chrominance components U / V_MN are stored in FIFO 358. The luminance and chrominance components Y_PIP, U of the sub-signal
_PIP and V_PIP are generated by the demultiplexer 355. The luminance component is subjected to resolution processing by a circuit 357 if necessary, and is interpolated by an interpolator 3 if necessary.
Decompressed by 59 produces a signal Y_AUX as output.

In some cases, the sub-display may have the same size as the main signal display as shown in FIG. Due to the in-screen screen processor and memory limitations associated with video RAM 350, the number of data points, or pixels, may be insufficient to fill such a large area. In such a case, it is possible to use the resolution processing circuit 357 to recover a pixel to be replaced with a pixel lost during data compression or reduction to a sub-video signal. This resolution processing is performed by the circuit 370 shown in FIG.
Can be made to correspond to what is performed. For example, the circuit 370 is a dithering circuit, and the circuit 357 is
It can be Gyakude Izaringu circuit.

[0060] sub video input data is sampled at a frequency of 640 f _H, is stored in the video RAM 350. The sub data is read from the video RAM 350, and VRAM_
Shown as OUT. The PIP circuit 301 can also reduce the sub-screen asymmetrically in the horizontal and vertical directions, and can also reduce the sub-screen by a factor of the same integer. Referring to FIG. 10, the sub-channel data includes 4-bit latches 352A and 352B and a sub-FIFO.
354, a timing circuit 369 and a synchronization circuit 368 buffer and synchronize to the main channel digital video. The VRAM_OUT data is classified by the demultiplexer 355 into Y (luminance), U, V (color component), and FSW_DAT (high-speed switch data). FSW_DAT indicates which field type was written to the video RAM. The PIP_FSW signal is supplied directly from the PIP circuit and supplied to the output control circuit 321 to determine which field read from the video RAM should be displayed in the small screen mode.

[0061] subchannel is sampled at 640 f _H, whereas the main channel is sampled at 1024f _H. The sub-channel FIFO 354 converts the data from the sub-channel sample frequency to the main channel clock frequency. In this process, the video signal is 8/5
(1024/640) compression. This is greater than the 4/3 compression required to correctly display the subchannel signal. Therefore, the sub-channel must be expanded by the interpolator 359 in order to correctly display a 4 × 3 small screen. The interpolator 359 is controlled by the interpolator control circuit 371, and the interpolator control circuit 371 itself has the WSP
Respond to μP340. The amount of decompression required by the interpolator is 5/6. The expansion coefficient X is determined as follows.

X = (640/1024) * (4/3) = 5/6

Chrominance components U_PIP and V_PIP
Is delayed and matched by a circuit 367 to a length determined according to the content of the interpolation of the luminance component.
_AUX is generated as an output. The Y, U, and V components of the main signal and the sub-signal are FIFO 354, 356
358 by controlling the read enable signal of each multiplexer 3 in the output signal path 312.
15, 317 and 319. Multiplexers 315, 317, 319 are responsive to output multiplexer control circuit 321. The output multiplexer control circuit 321 includes an in-screen screen processor and a WSP μP340.
Signal CLK, line start signal SOL, H_C
Responds to the OUNT signal, the vertical blanking reset signal, and the output of the high speed switch. Multiplexed luminance and chrominance components Y_MX, U_MX and V
_MX is the respective digital / analog converter 36
0, 362 and 364. As shown in FIG. 4, the digital-analog converters 360, 362, 3
64, the low-pass filters 361 and 3
63 and 365 are connected. The various functions of the in-screen screen processor, gate array and data reduction circuit
By SP μP340 that are controlled. W SP μP3
40 is a TV μP connected to this via a serial bus.
Responds 216. This serial bus can be a four-line bus having lines for data, clock signals, enable signals, and reset signals, as shown. W
SP μP 340 communicates with various circuits of the gate array through WSP μP decoder 310.

In one case, it is necessary to compress 4 × 3 NTSC video by a factor of 4/3 in order to avoid distortion of the display screen aspect ratio. In another case,
Video may be decompressed to perform horizontal zooming, which usually also involves vertical zooming. Horizontal zooming operations of up to 33% can be performed by reducing the compression to less than 4/3. The sample interpolator is S
Luminance video bandwidth of up to 5.5MHz in -VHS format, since the time of 1024F _H occupies a large percentage of the Nyquist folding frequency is 8 MHz, is used to recalculate the incoming video to a new pixel positions .

As shown in FIG. 6, the luminance data Y_
The MN is passed through an interpolator 337 in the main signal path 304 that recalculates sample values based on video compression or decompression. Switch, ie, route selector 32
The functions of 3 and 331 are FIFO 356 and interpolator 337.
Inverting the topology of the main signal path 304 with respect to the relative position of That is, these switches allow the interpolator 337 to provide
Choose whether to precede O356 or to make FIFO 356 precede interpolator 337, as required for decompression. Switches 323 and 331 respond to route control circuit 335, which in turn responds to WSP μP 340. In small screen mode,
It will be recalled that the secondary video signal is compressed for storage in video RAM 350 and only decompression is required for practical purposes. Therefore, switches corresponding to these are not required in the sub signal path.

The main signal path is shown in more detail in FIG. Switch 323 has two multiplexers 325 and 3
27. Switch 331 is embodied by multiplexer 333. These three
One multiplexer responds to the route control circuit 335,
The route control circuit 335 itself responds to the WSP μP 340. A horizontal timing / synchronization circuit 339 controls the operation of the latches 347 and 351 and the multiplexer 353, and generates a timing signal for controlling writing and reading of the FIFO. Clock signal CLK and line start signal SOL are generated by clock / synchronization circuit 320. The analog-to-digital conversion control circuit 369 has a Y_M
N, WSP μP 340, and respond to the most significant bit of UV_MN.

The interpolator control circuit 349 includes an intermediate pixel position value (K), an interpolator compensation filter weight (C), and clock gating information CG for luminance.
Clock gating information CG for Y and color components
Generates UV. Interruption (decimation) of FIFO data to prevent samples from being written at several clocks to perform compression, or to allow some samples to be read multiple times for decompression
Or, it is this clock gating information that causes repetition.

FIG. 15 shows such compression. LUMA
The line _RAMP_IN represents the luminance ramp video data being written to the FIFO. WR_EN_MN
The _Y signal is valid and high. That is, when this signal is high, it indicates that data is being written to the FIFO. 4
Individual samples are prevented from being written to the FIFO. The uneven line LUMA_RAMP_OUT is
FIFO if data was not interpolated first
Represents the luminance ramp data read from the memory. Note that the average slope of the ramp read from the luminance FIFO is 33% steeper than the input ramp. The effective read time required to read this lamp is 33% of the time required to write data.
I want to pay attention to the small number. As a result, 4/3 compression is performed. The recalculation of the luminance samples written in the FIFO so that the data read from the FIFO does not become uneven but becomes smooth is performed by the interpolator 337.
Function.

Decompression can be performed in a manner completely opposite to compression. In the case of compression, clock gating information is added to the write enable signal in the form of a prohibition pulse. For data decompression, clock gating information is applied to the read enable signal. This allows
As shown in FIG. 16, when data is read from FIFO 356, the data is interrupted. Line LUMA_R
AMP_IN represents data before being written to FIFO 356, and uneven line LUMA_RAMP_OUT represents data as it is being read from FIFO 356.
In this case, the reason why the sampled data is recalculated so as to be smooth from the state of the unevenness after the expansion is that the interpolator 337 at the position following the FIFO 356 during this processing.
Function. In the case of decompression, the data is FIFO 356
And must be interrupted when clocked into the interpolator 337. This is different from the case of compression where data is continuously clocked through the interpolator 337. In both compression and decompression cases, the clock gating operation can be easily performed in a synchronized manner. In other words, events occurring in the basis of the rising edge of the system clock 1024f _H.

This arrangement for luminance interpolation has a number of advantages. Clock gating operations, ie, data decimation and data repetition, can be performed synchronously. Without switching the interpolator and FIFO positions using the switchable video data topology, the write or read clock would have to be double clocked due to data interruption or repetition. The term "double clocked" means that two data points must be written to the FIFO during one clock cycle, or two data points must be read from the FIFO during one clock cycle. is there. As a result, the write or read clock frequency must be twice the system clock frequency, so that the circuit configuration cannot operate in synchronization with the system clock. In addition, this switchable topology requires only one interpolator and one FIFO for both compression and decompression purposes. Without the video switching arrangement described here, double clocking can be avoided only with two FIFOs to achieve both compression and decompression functions. In that case, one FIFO for decompression must be placed before the interpolator, and one FIFO for compression must be placed after the interpolator.

The interpolation of the sub signal is performed on the sub signal path 306. The PIP circuit 301 has 6 bits Y, U, V, 8:
The video RAM 350, which is a 1: 1 memory, is operated to store incoming video data. Video RAM 350 holds two fields of video data in a plurality of memory locations. Each memory location holds eight bits of data. Each 8 bit positions, one 6-bit Y (luminance) sample (which was sampled at 640 f _H) that there are two bits other. These other two bits are either fast switch data (FSW_DAT) or U or V samples (8
0f _H those samples) holds a part of either one of. The value of FSW_DAT indicates which type of field was written to the video RAM. Video R
Since two fields of data are stored in the AM 350 and the entire video RAM 350 is read during the display period, both fields are read during the display scanning period.
The PIP circuit 301 uses the high-speed switch data to determine which field is to be read from the memory and displayed. The PIP circuit always reads the type of field opposite to what is being written to solve the problem of motion fragmentation. If the type of the field being read is the opposite of that being displayed, the even field stored in the video RAM will delete the top line of that field when the field is read from memory. Inverted. As a result, the small screen maintains the correct interlace without disruption of motion.

The clock / synchronization circuit 320 is a FIFO 35
4, 356 and 358 necessary to operate the read, write and enable signals. The FIFOs for the primary and secondary channels are enabled to write data for storage for the portion needed to display after each video line. Data is written from one (but not both) of the primary and secondary channels required to combine the data from each source on the same one or more lines of the display. Secondary channel FI
The FO 354 is written in synchronization with the sub video signal, but is read out in synchronization with the main video signal. The main video signal component is synchronized with the main video signal and FIFOs 356 and 358
And read from the memory in synchronization with the main video. The frequency at which the read function is switched between the main and sub-channels is a function of the particular special effect selected.

The generation of another special effect, such as a truncated juxtaposed screen, is performed by manipulating the read and write enable control signals for the line memory FIFO. The processing for this display format is shown in FIGS.
In the case of the truncated juxtaposition display screen, the sub-channel 204
Write enable control signals for the 8 × 8FIFO354 (WR_EN_AX), as shown in FIG. 7, the display effective line period (1/2) * (5/6) = 5/12, i.e.,
About 41% (post speedup
d up)) or 67% of the effective line period of the sub-channel (pre speed up (pre speed)).
d up)). this is,
This corresponds to a truncation of about 33% (approximately 67% is a valid screen) and a signal extension of 5/6 by the interpolator. In the main video channel shown at the top of FIG. 8, 910 × 8 FIFO3
56 and 358 (WR)
_EN_MN_Y) is (１ ／) * of the display valid line period
(4/3) = 0.67, that is, active during 67%. This is about 33% truncated and 910x
This corresponds to a compression ratio of 4/3 applied to the main channel video by 8FIFO.

In each of the FIFOs, video data is buffered so that it is read at a particular point in time. The effective area of time during which data can be read from each FIFO depends on the display format chosen.
In the illustrated example of the side-by-side truncation mode, the main channel video is displayed on the left half of the display, and the sub channel video is displayed on the right half of the display. Any video portion of each waveform is different for the primary and secondary channels as shown. The main channel 910 × 8 FIFO read enable control signal (RD_EN_MN) is active for 50% of the display active line period of the display beginning at the beginning of the active video immediately following the video back porch. Sub-channel read enable control signal (RD_E
N_AX) is active for the remaining 50% of the display active line period beginning at the falling edge of the RD_EN_MN signal and ending at the beginning of the front porch of the main channel video. The write enable control signal is synchronized with the respective FIFO input data (primary or secondary),
On the other hand, the read enable control signal is synchronized with the main channel video.

The display format shown in FIG.
This is particularly desirable because almost all of the screens of the two fields can be displayed in a side-by-side format. This display is particularly effective and suitable for displaying a wide format display ratio, for example, 16 × 9. Most NTSC signals are represented in 4 × 3 format, which of course corresponds to 12 × 9. Two NTSC screens with a 4x3 format display ratio, these screens are cut down by 33% or 3
3% packed, same 16 with aspect ratio distortion introduced
It can be displayed on a display having a × 9 format display ratio. Depending on the user's preference, the ratio between screen truncation and aspect ratio distortion can be set to any point between the 0% and 33% limits. For example, two side-by-side screens can be displayed with a 16.7% reduction and a 16.7% reduction.

The horizontal display time required for displaying the display ratio of the 16 × 9 format is the same as that for displaying the display ratio of the 4 × 3 format. This is because the length of the normal line is 62.5 μsec in both cases. Therefore, the NTSC video signal must be speeded up by a factor of 4/3 to maintain the correct aspect ratio without causing distortion. This factor of 4/3 is the ratio of the two display formats,

## EQU2 ## It is calculated as 4/3 = (16/9) / (4/3). To speed up the video signal, a variable interpolator is used in accordance with aspects of the present invention. In the past, FIFOs with different clock frequencies at the input and output have been used to perform similar functions. For comparison, if two NTSC × 3 format display ratio signals are displayed on one 4 × 3 format display ratio display, each screen will be distorted, truncated, or both by 50%. Must be combined. There is no need for speedups equivalent to those required for widescreen.

In all of the above-mentioned operation modes, for example, in the juxtaposed screen mode, the PIP or the POP mode, the main screen can be zoomed, that is, enlarged in the horizontal direction, the vertical direction, or both directions. In a mode where the screen is zoomed horizontally to a point where it is unavoidably truncated, it would be advantageous to allow the user to control the horizontal pan so that the user can select the part of the screen that he wants to view at any time. It is. As described in detail in connection with FIG. 6, control of horizontal pan is desirable for both expansion (zoom main screen) and compression (side-by-side screen) modes. In the upper left corner of FIG.
A selectable interconnection between 356 and main interpolator 337 is shown. The main signal path is shown in detail in FIG. As shown in these figures, the topology of the main signal path depends on whether the system is operating in a decompression mode or a compression mode. The horizontal pan circuit shown here is independent of these modes and can operate with each mode. The following description is made only for the main luminance channel for convenience. The same pan configuration is equally valid for the main chrominance (U, V) channels.

Of course, panning only the main video signal makes sense only when the main screen is truncated during compression in side-by-side screen mode or during expansion in zoom mode. The effect of horizontal pan is shown in FIG. Zooming the screen to the center reveals most of the humans and dinosaurs on the screen, and truncates some of the right and left sides of the screen. When panned to the right, most of the dinosaurs are visible, but humans only see their hind legs. Also, when you pan left, you can see most humans and most dinosaurs, but not the dinosaur tail.

The FIFOs in the main signal path each have independent write and read enable signals. By doing so, both what part of the video signal is stored in the memory and when that part is displayed can be controlled independently of each other. Generally, if the signal is decompressed and truncated, the truncation can be done with a write enable signal. In this way, only the video to be displayed is stored in the FIFO. further,
Horizontal panning can be done simply by manipulating the write enable window during the valid video period, i.e., the period during which writing to the FIFO can be performed. This is shown in FIG. 18 and FIG. FIG. 18 shows a zoomed video signal corresponding to, for example, the screen of FIG. This video signal does not directly represent an actual waveform. FIG. 19 (a) shows the write enable window timed to perform horizontal panning to the right. FIG. 19 (b) shows the write enable window timed to pan horizontally to the center. FIG. 19C shows a write enable window time-adjusted to horizontally pan left. If writing is enabled early, the effect will be similar to the effect of panning the camera to the left, and the displayed video will appear to scroll to the right of the display. Conversely, if writing is enabled late,
The effect is as if the camera had panned to the right, and the displayed video would appear to scroll to the left of the display.

If the signal is compressed and truncated, the truncation may be by a write enable signal or by FIG.
The output multiplexer control circuit 321 shown in FIG. In the side-by-side screen mode, truncation is performed by switching to the sub-channel, but panning of the main signal can still be performed by manipulating the write enable window, as described above.

By operating the read enable window or the combination of the read enable window and the write enable window according to the display position of the main video and the amount of horizontal overscan of the display, a fixed amount of horizontal pan is performed. be able to.
However, if the read enable window is set correctly, then operation of the write enable window should be sufficient.

[Brief description of the drawings]

1 (a) to 1 (i) show various display formats of a wide screen television.

2 is a block diagram of those to work with horizontal scanning of various wide screen television 2f _H in accordance with an aspect of the present invention.

FIG. 3 is a block diagram of the wide screen processor shown in FIG. 2;

FIG. 4 is a block diagram showing details of a wide screen processor shown in FIG. 3;

FIG. 5 is a block diagram of an in-screen screen processor shown in FIG. 4;

6 is a block diagram of the gate array shown in FIG. 4, showing a main signal path, a sub signal path, and an output signal path.

FIG. 7 is a timing chart used to explain the generation of the display format shown in FIG. 1D using a sufficiently truncated signal.

FIG. 8 is a timing diagram used to explain the generation of the display format shown in FIG. 1D using a sufficiently truncated signal.

FIG. 9 is a block diagram showing the main signal path of FIG. 6 in more detail.

FIG. 10 is a block diagram showing the sub signal path of FIG. 6 in more detail;

11 is a timing chart of the in-screen screen processor of FIG. 5;
It is a block diagram of a control part.

12 is a block diagram of a circuit for generating the internal 2f _H signal in the 1f _H -2f _H conversion.

FIG. 13 is a combination block and a circuit diagram for the deflection circuit shown in FIG. 2;

FIG. 14 is a block diagram of an RGB interface shown in FIG. 2;

FIG. 15 is a waveform diagram used to explain video compression.

FIG. 16 is a waveform diagram used to explain video decompression.

FIG. 17 is a diagram for describing truncation of a screen by zooming.

FIG. 18 is a timing chart for explaining horizontal panning of a truncated video signal.

FIG. 19 is a timing chart for explaining horizontal panning of a truncated video signal.

[Explanation of symbols]

244 Video signal display means 304 Decompression / compression means 339 Means for generating signals for controlling writing and reading 340 Means for controlling control signal generation means 337 Interpolator 356 Line memory

Continued on the front page (72) Inventor Timothy William Seager 46260 Indianapolis, Nashville, A.D., U.S.A. 8318 (72) Inventor Nataniel Hulk Artes, U.S.A. Japanese Unexamined Patent Publication No. Hei 5-91435 (JP, A) Japanese Unexamined Patent Publication (Kokai) No. 2-292978 (JP, A) International Publication No. 5-507832 (JP, A) International Publication No. 91/19394 (WO, A1)

Claims (3)

(57) [Claims] 1. A for displaying the processed video signal, the display means having a wide format display ratio (24
4) and at least one input video signal (Y_M ) representing an image.
N) operating the data to generate the processed video signal, wherein the first area of the image is clipped and the second area of the image represents the processed video signal. in at least one display mode where the write to to truncate the image selectively, asynchronous writing and reading are performed
Signal processing means (304) including memory means (356) having read and read ports; and a write control signal (W ) for said memory means (356) .
The R_EN_MN_Y), at least with respect to the synchronization component of one input video signal to a phase selectable, and by duration selectably generating, which portion of the image, the second area in said at least one display mode means for determining whether to form a (33
9) A video system for a television device, comprising: Wherein for displaying the processed video signal, the display means having a wide format display ratio (24
4) and at least one input video signal (Y_M ) representing an image.
N) operating the data to generate the processed video signal, wherein the first area of the image is clipped and the second area of the image represents the processed video signal. in at least one display mode where the write to to truncate the image selectively, asynchronous writing and reading are performed
Signal processing means (304) including memory means (356) having read and read ports; and writing to said memory means (WR_EN_MN_
Y) and a read-out control signal (RD_EN_MN_Y) each being phase selectable with respect to the synchronization component of the at least one input video signal and each being duration selectable, so that which part of the image is Means (339) for determining whether to form the second area in at least one display mode. 3. A display means (244) having a wide format display ratio and a predetermined size for displaying the processed video signal; represented by data in at least one input video signal (Y_MN). Signal processing means for generating the processed video signal by selectively truncating an image and defining a subset of the image to perform a plurality of display modes, the plurality of display modes comprising: A first display mode (FIGS. 1 (b) and (e)) , wherein the subset represents a portion of the image that has been expanded corresponding to the predetermined size; The image is truncated and the subset fills a portion of the display means that is smaller than the predetermined size. De and (FIG. 1 (d)), including signal processing means (304)
If; when all of the image is not represented in said processed video signals, to determine which subset of the image represented by the processed video signal, wherein
Phase for at least one sync component of the input video signal
A control signal (WR) that is selectable and has a selectable duration.
_EN_MN_Y) to the signal processing means, and a microprocessor (WSP μP340) .