JP3242226B2 - Full adder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a full adder.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional full adder. This full adder is completely divided into a sum output circuit and a carry output circuit, and includes an NMOS transfer gate transistor having a threshold voltage of 0 V,
It has an output buffer inverter.

The added value is A, the added value is B, the respective negations are A # and B #, the carry from the lower order is C, and the negation is C #. The sum output is S, its negation is S #, the carry output is C ₀ , and its negation is C ₀ #.

[0004] The sum output S and its negative S # are performed as follows. First, a logical product of A and B (hereinafter, a logical product is described as AB) by a transfer gate N101, N102
Generates (AB) #, the logical value of the node S101 is AB + (AB) # (hereinafter, the logical sum is described as A + B), that is, the negation of the exclusive OR of A and B (hereinafter, the exclusive OR) Is written as (A * B) #). Similarly, A # B is generated by N103 and AB # is generated by N104, and the logical value of the node S102 is an exclusive OR of A and B (hereinafter, the exclusive OR is described as A * B). This is the first stage.

In the second stage, A * B and (A * B) #,
By using the carry C and C # from the lower part, the configuration exactly the same as that of the above-described circuit is adopted, so that the transfer gates N105, N105
(A * B * C) # is added to the contact S103 by N
107, N108, N109 make contact A
* B * C is generated. Thereafter, in the third stage, the data is output to the outside via the inverters 1101 and 1102 as buffers.

Similarly, the carry outputs C ₀ and C ₀ # are supplied to the contact S109 at (A # B + (BC) #) A + ((AB)
# + BC #) A #, contact S101IF (AB + B # C)
A + (AB # + BC) A # is generated. They are,
(AB + C (A * B)) #, AB + C (A * B), that is, the same value as the carry output. Finally, like the sum output,
Output to the outside via the buffer inverter.

[0007]

However, the full adder having the configuration according to the above-mentioned prior art has the following problems.

That is, the NMO is used to construct the full adder.
As many as twenty-four elements, 24 S elements and four PMOS elements, are needed. In addition, at this time, since an NMOS having a threshold voltage of 0 V is used, current continues to flow even in a steady state.

In order to suppress the above current, an ordinary NMOS
, But in this case, NMOS
, The signal on the high potential side drops about twice the threshold voltage. In this state, when a signal of high potential side came into the inverter, since NMOS, always ON state also PMOS,
Through current always flows, and power consumption increases. Further, when the power supply voltage is lowered, the gate input of the output buffer becomes lower than the threshold voltage, which may cause a malfunction. For this reason, it is necessary to set the voltage on the high potential side to be a power supply, so that four more PMOSs are required for the pull-up circuit, and a total of 32 transistors are required. This is disadvantageous for high integration.

[0010]

According to the present invention, the added value is represented by A,
Complementary path where the value to be added is B and the carry from the lower order is C
In the full adder by the gate logic, the addition value A signal
And the augmented value B signal, the exclusive OR of A and B (A *
B) Generate a signal and exclusive-OR NOT (A * B) # signal
And a first circuit generated by the first circuit.
* B) signal, (A * B) # signal, and carry C signal from lower order
From the carry signal and the sum output signal, respectively.
A second circuit for generating the signal and a third circuit for generating the signal.
The circuit, the second circuit and the third circuit are constituted by the same circuit.
A full adder is provided. In addition, the present invention
Is that the second circuit calculates the exclusive OR of A and B and C
Logical product, logical product of A and negation of exclusive OR of B and A
A carry output signal is generated from the logical sum of
The logical product of the logical disjunction and the negation of C, and the exclusive theory of A and B
Carry out the logical sum of the negation of the logical sum and the logical product of the negation of A
2. A signal for generating a negative signal of an output signal.
And a full adder according to (1).

[0011]

In the full adder according to the present invention, the first stage circuit is used as a circuit for outputting an exclusive OR / negation of the exclusive OR, and is shared between the sum output and the carry output. Thus, the number of elements can be reduced from 28 to 26.

A full-swing operation is performed by always providing a pull-up circuit of PMOS immediately after one stage of NMOS transfer gate.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The full adder according to the present invention will be described below in detail with reference to embodiments.

FIG. 1 is a circuit diagram of a full adder according to the present invention. This full adder includes an adder A and an adder B
Exclusive OR (A * B) and negation of exclusive OR (A *
B) The first stage of making #, A * B made by the first stage,
(A * B) # and a second stage for generating carry outputs C ₀ and C ₀ # and sum outputs S and S # from the carry signal C from the lower order, and a third stage including an inverter as an output buffer.

In the first stage, the addition value A and its negation A #
And the addition value B and its negation B # are input to the transfer gates N1 and N2 as shown in FIG. 1, so that the node S1 indicates A # B + AB #, that is, A * B. Similarly, (A * B) # appears at the node S2 by the transfer gates N3 and N4. Now, here, nodes S1 and S
2 has a voltage drop by the threshold voltage of the transfer gate, and if it is input to the next gate as it is, a further voltage drop will occur there and a through current will flow through the third stage inverter. I will. Therefore, as a pull-up circuit between S1 and S2, PMOS
, The voltage on the high potential side is raised to the power supply voltage.

From the sum output S, S # F, and the logical expression, the exclusive OR of A * B and C can be obtained as it is, so that the same configuration as in the first stage can be used. Nodes S5 and S6 are respectively
(A * B * C) #, A * B * C. As in the first stage, the nodes S5 and S6 after passing through the transfer gate
Since a voltage drop occurs, a through current flows when the high potential side is input to the inverter. To prevent this, the first
Pull-ups P5 and P6 are provided in the same manner as the stage, and the high potential side is set to the power supply voltage to prevent a through current. The sum signals S and S # are the third signals
The signal is output to the outside through an inverter as a buffer in the stage.

Next, the carry signals C ₀ and C ₀ #, the exclusive OR of the addition value A and the addend B, the negation of the exclusive OR, the addition value A and its negation A #, From carry C and its negation C #, (A * B) C + (A * B) #A,
(A * B) #A # + (A * B) C #, and when deformed, they are (AB + C (A * B)) # and AB + C (A
* B). Accordingly, as shown in FIG. 1, the logical value of the node S3 is changed to C by the transfer gates N5 and N6.
₀ #, node S4 by transfer gates N7 and N8
Is C ₀ . As with the sum signal, output inverter 1
1 and 12, so that the pull-up circuit P
The voltage on the high potential side is raised to the power supply voltage by the MOSs, P3 and P4.

[0018]

As is apparent from the above description, the full adder according to the present invention is composed of 24 NMOS transistors and 4 PMOS transistors of the prior art.
A total adder is composed of a total of 28 NMOS transistors and a total of 26 PMOS transistors and a smaller number of elements compared to a conventional full adder having a total of 32 transistors when a normal transistor is used. it can. Although the number of PMOS elements is larger than that of the conventional type, it does not require a driving force and is small in size because it is used for pull-up. Further, since the signal makes a full swing at all nodes, almost no power is consumed in a steady state.

Therefore, it is possible to provide a full adder capable of reducing the area occupied by the full adder on a chip and reducing power consumption.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of a full adder according to the present invention.

FIG. 2 is a diagram showing a circuit configuration of a conventional adder.

[Explanation of symbols]

A, A # Addition value and its negation B, B # Addition value and its negation C, C # Carry from lower order and its negation S, S # Sum output and its negation C ₀ , C ₀ # Carry output N1 to N12 NMOS transfer gates P1 to P6 PMOSs for pull-up I1 to I4 Output inverters S1 to S6 Nodes N101 to N120 NMOS transfer gates I101 to I104 Output inverters S101 to S110 Nodes

Claims (2)

(57) [Claims] 1. A full adder using complementary pass gate logic in which an adder value is A, an addend value is B, and a carry from the lower order is C, an A signal is obtained from an adder A signal and an adder value B signal. And exclusive of B
Logical OR (A * B) signal and exclusive OR NOT (A * B)
# Signal, a (A * B) signal generated by the first circuit, and (A *
B) Carry out from # signal and carry C signal from lower
Second circuit for generating a force signal and a sum output signal, respectively
And a third circuit, wherein the first circuit, the second circuit, and the third circuit are operated in the same circuit.
A full adder characterized by comprising a road . 2. The second circuit according to claim 1, wherein: an exclusive OR of A and B and a logical product of C;
Carry from negation of logical disjunction and disjunction of logical product of A
Generating an output signal ; ANDing the exclusive OR of A and B with the negation of C;
Of the exclusive negation of n and the negation of negation of A
And generating a carry output negation signal from
The full adder according to claim 1.