JP3244342B2 - Wireless receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio receiver having an integrated circuit for synchronizing control operations with a clock signal from a microprocessor or the like, and more particularly to a radio receiver for reducing reception interference due to unnecessary radiation of a harmonic of a clock signal. It relates to a wireless receiver that has been used.

[0002]

2. Description of the Related Art Harmonics of a clock signal for synchronizing a control operation of an integrated circuit are undesirably radiated, and this undesired radiation may be received by an antenna to cause reception interference. For example, if the reception frequency is 464.00 MHz and the clock signal is 4.000 MHz, the 116th harmonic of the clock signal matches the reception frequency.

As a technique for reducing reception interference due to unnecessary radiation of harmonics of the clock signal, it is desirable to reliably perform shielding to reduce unnecessary radiation. However, it is difficult to perform sufficient shielding in a miniaturized wireless receiver.

Japanese Patent Application Laid-Open No. 62-272629 discloses a technique in which the frequency of a clock signal is changed according to the reception frequency so that its harmonics do not match the reception frequency. Briefly describing the prior art disclosed in Japanese Patent Laid-Open No. 62-272629, data relating to a clock signal whose harmonics do not match the reception frequency is set in advance, and a new reception frequency is set in the radio receiver. When set, a clock signal having a frequency at which the harmonics do not match is set according to the relational data.

[0005]

Problems to be Solved by the Invention
The prior art disclosed in Japanese Patent No. 2629 is excellent because it does not require sufficient shielding and can reduce reception interference due to harmonics of a clock signal.

However, if the clock signal is output at an accurate frequency in accordance with the relevant data, the above-described excellent operation is obtained. However, if the frequency of the clock signal shifts due to the influence of temperature or the like, an unexpected situation occurs. A change in the frequency of the clock signal may rather cause a problem that the reception is disturbed.

For example, if the receiving frequency is 464,000 MH
When z, the frequency of the clock signal is 3.9999
If the frequency is set to MHz, the harmonic does not match the reception frequency and does not cause reception interference. However, the frequency of the clock signal increases by 100 Hz due to the influence of the temperature and the like, and the frequency of the actually output clock signal becomes 4.00.
As described above, there is a possibility that reception interference may occur at 00 MHz.

Therefore, in the above-mentioned prior art, in order to obtain a reliable operation and effect, a temperature compensating means or the like that does not shift the frequency of the clock signal is required, and is not suitable for miniaturization. In addition, it is necessary to previously set related data for setting a clock signal with respect to the reception frequency, and it is difficult to correspond to a reception frequency that is arbitrarily set in a wide range.

The present invention has been made in view of the circumstances of the prior art as described above. By changing the frequency of a clock signal in accordance with the determination of the presence or absence of reception interference, it is possible to reliably prevent reception interference due to harmonics of the clock signal. It is an object of the present invention to provide a wireless receiver capable of reducing the number of wireless receivers.

[0010]

In order to achieve the above object, a radio receiver according to the present invention comprises a radio receiver having an integrated circuit for synchronizing a control operation with a clock signal output from clock oscillation means. Modulation means for modulating a clock signal with a modulation signal, shift means for changing the frequency of the clock signal output from the clock oscillation means, and detection means for detecting the modulation signal contained in a received demodulated signal, And wherein the shift means changes the frequency of the clock signal when the detection means detects the modulation signal.

The detecting means may be configured to determine whether or not the received demodulated signal includes a signal that matches a reference signal preset at the same frequency as the modulation signal. .

Further, the modulation means may be operated for a fixed period in response to a change in a reception frequency or a reception mode or a change in the frequency of the clock signal by the shift means.

[0013]

[Operation] Since the clock signal is modulated by the modulation signal, if it is detected that the received demodulation signal includes the modulation signal, it can be determined that the reception disturbance is caused by the harmonic of the clock signal. . Therefore, if the modulation signal is included in the received demodulated signal, the reception disturbance can be reduced by changing the frequency of the clock signal.

If the detecting means determines whether or not the received demodulated signal includes a signal that matches the reference signal set to the same frequency as the modulation signal, the detecting means uses a PLL circuit or the like. And can be easily configured.

Further, if the setting of the radio receiver changes, such as a change in the receiving frequency, the modulating means is operated only for a certain period of time to determine whether or not reception interference has occurred. The clock signal is not modulated in an unnecessary period after the completion.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block circuit diagram of an embodiment of the wireless receiver of the present invention, and FIG. 2 is a flowchart for explaining the operation.

In FIG. 1, a radio receiver comprises an antenna 10, a high-frequency amplifier 12, a frequency converter 14, a local oscillator 16, an IF / demodulator 18, a low-frequency amplifier 20, and a speaker 22. The wireless receiver is appropriately controlled by an integrated circuit 24 such as a microprocessor.

The integrated circuit 24 is connected to a clock oscillating means 26 for outputting a clock signal for synchronizing the control operation. The clock oscillating means 26
Includes a variable capacitance diode 28 as a component, and a modulation signal output from a modulation oscillator 30 is applied to a cathode thereof to modulate a clock signal. In addition,
Modulation means is formed by the modulation oscillator 30 and the variable capacitance diode 28. Further, a shift circuit 34 is connected to the clock oscillation means 26 via a capacitor 32. The shift circuit 34 has a switch function of opening or grounding the other end of the capacitor 32, and is provided with a shift means for changing the frequency of the clock signal output from the clock oscillation means 26.

Then, a part of the received demodulated signal output from the IF / demodulator 18 is given to the detecting means 36. The detecting unit 36 includes an oscillator that oscillates a reference signal set in advance at the same frequency as that of the modulation oscillator 30, and determines whether or not the received demodulated signal includes a signal that matches the reference signal. If it is determined that a matching signal is included, the built-in latch circuit is latched, and the output signal is provided to the shift circuit 34 as a detection signal. The detection means 30 is composed of, for example, a PLL circuit, and supplies a reference signal and a received demodulated signal to a phase comparator, and can determine whether or not the PLL circuit is locked. The detecting means 36
A portion of the modulation signal of the modulation oscillator 30 is provided as shown by the broken line in FIG.
It may be determined whether or not the received demodulated signal includes a signal that matches the modulation signal.

Further, the detecting means 36 receives a reset signal from the integrated circuit 24 when the receiving frequency and the receiving mode of the radio receiver are changed, and when the frequency of the clock signal output from the clock oscillating means 26 is changed. Initial state. Further, a timer is built in the integrated circuit 24, the timer is started when the reception frequency and the reception mode of the radio receiver are changed, and the timer is restarted when the frequency of the clock signal is changed. 30 is activated only for a predetermined period.

In such a configuration, the integrated circuit 24 determines whether the reception frequency of the radio receiver has been changed or whether the reception mode has been changed (FIG. 2 step). The state is set and the timer is started (step). When the timer is started, the modulation oscillator 30 is activated, and the clock signal is modulated (step). In response to the modulation of the clock signal, the detection means 36 determines whether or not the received demodulated signal includes a modulation signal (step). If not detected, it is determined that the timer has counted a predetermined period. Until (step), step,
, Are repeated. When the timer has counted a certain period (step), the operation of the modulation oscillator 30 is stopped, the modulation of the clock signal is stopped (step), and the process returns to the step. When it is detected in step that the received demodulated signal includes a modulation signal, a detection signal is supplied to the shift circuit 34, the other end of the capacitor 32 is grounded, and the output is output from the clock oscillation unit 26. The frequency of the clock signal is changed (step), and the process returns to the step and restarts the timer.

As described above, the present invention changes the frequency of a clock signal when a modulation signal is detected in a received demodulated signal, that is, when reception interference is caused by harmonics of the clock signal. As in this type of technology, reception interference can be reliably reduced without being affected by temperature or the like. Further, it can correspond to a wide range of arbitrary reception frequencies. Further, it is not necessary to set data or the like for changing the clock signal in advance.

In addition, the higher the level of reception interference,
Since the detection by the detecting means is reliable and easy, the structure for blocking unnecessary radiation of the harmonics of the clock signal can be simple and suitable for a miniaturized wireless receiver. In addition,
In the above embodiment, the modulating means converts the clock signal to FM.
Since the modulation is performed, the modulation signal can be demodulated by a radio receiver, which is an FM receiver. However, the present invention is not limited to this. It will be easy to understand.

Further, in the above embodiment, the modulation of the clock signal is performed only for a predetermined fixed period when the reception frequency is changed, but the clock signal may always be modulated. Further, the integrated circuit 24 determines the change of the reception frequency or the like in order to operate the modulation oscillator 30. The modulation oscillator 30 is linked to other appropriate means such as a switch operation for changing the reception frequency. May be operated.

[0025]

As described above, since the radio receiver according to the present invention is constituted, the following special effects can be obtained.

In the radio receiver according to the first aspect, when it is detected that the received demodulated signal includes a modulation signal obtained by modulating the clock signal, the frequency of the clock signal is changed. The frequency of the clock signal is changed according to the presence or absence of the reception interference, and the reception interference can be reliably reduced without being affected by the frequency shift of the clock signal due to a change in temperature or the like. Further, the wireless receiver can exert the effect of reducing reception interference according to the present invention in a wide range of arbitrary reception frequencies. In addition, if reception interference occurs, the frequency of the clock signal is changed to reduce the reception interference, so that the structure for shielding unnecessary radiation of harmonics of the clock signal is simple and suitable, and is suitable for miniaturization.

In the wireless receiver according to the second aspect, it is determined whether or not the received demodulated signal includes a modulation signal.
The detection can be reliably performed using a PLL circuit or the like, and the detection means can be simply configured, which is suitable for mass production.

Furthermore, in the radio receiver according to the third aspect, when the setting status of the radio receiver changes, such as a change in the reception frequency, it is determined whether or not reception interference has occurred for a certain period. Therefore, the clock signal is not modulated during an unnecessary period after the reception interference is reduced.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of an embodiment of a wireless receiver according to the present invention.

FIG. 2 is a flowchart illustrating an operation.

[Explanation of symbols]

 24 Integrated Circuit 26 Clock Oscillator 28 Variable Capacitance Diode 30 Modulator Oscillator 32 Capacitor 34 Shift Circuit 36 Detector

Claims (3)

(57) [Claims] 1. A radio receiver having an integrated circuit for synchronizing control operations with a clock signal output from a clock oscillating means, comprising: a modulating means for modulating the clock signal with a modulating signal; and a signal output from the clock oscillating means. Shift means for changing the frequency of the clock signal, and detection means for detecting the modulation signal included in the received demodulated signal, wherein the shift means is provided when the detection means detects the modulation signal. Wherein the frequency of the clock signal is changed. 2. The radio receiver according to claim 1, wherein said detecting means determines whether or not the received demodulated signal includes a signal that matches a reference signal set in advance to the same frequency as the modulation signal. A radio receiver characterized in that it is configured to determine 3. The radio receiver according to claim 1, wherein the modulating means operates for a certain period in response to a change in a reception frequency or a reception mode or a change in the frequency of the clock signal by the shift means. A wireless receiver characterized by comprising.