JP3246327B2 - Sound signal processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform an efficient eliminating operation of soundless portion by providing a detecting means for detecting a small sound lower than a predetermined signal level to include a soundless state and a means for interrupting the progress of write addresses. SOLUTION: When an input signal is lower than a predetermined level, a small sound detecting section 34 outputs a small sound status signal SM in a high level state (small sound state) to a monostable multivibrator MM 19. In this case, when the signal SM changes from its low level state to a high level state (small sound portion or soundless portion), the MM 19 is triggered, a pulse SMu is outputted and supplied as a reset signal Pr2 from an OR circuit OR 22 to a set/reset flip flop RSFF 24. When a small sound state including non-sound is realized, by interrupting the progress of write addresses, a series of long block time listening processing is efficiently performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention reproduces information recorded on a recording medium on which an acoustic signal is recorded in a shorter time than the time required for recording, thereby performing signal processing on the acoustic signal having a higher pitch. The present invention relates to an audio signal processing apparatus for obtaining a reproduced signal that can be heard well.

[0002]

2. Description of the Related Art To reproduce recorded information on a recording medium on which an information signal is recorded in a time shorter than the time required for recording, for example, when reproducing from a video tape recorder (VTR) or a tape recorder, etc. It is well known that it has been widely used in the past. That is, a so-called helical scan type video in which a magnetic tape wound around a part of a peripheral surface of a drum is run at a predetermined running speed and a recording and reproducing operation is performed using a rotating magnetic head.・ Tape recorder (VTR) [or video
In the cassette recorder (VCR)], the rotation locus of the rotating magnetic head is 90 degrees with respect to the reference edge of the running magnetic tape.
In a helical scan type VTR configured to perform recording / reproduction in a state of showing an inclination angle of less than or equal to one degree, a video signal for one field period is recorded on one recording trace. When the playback speed is higher than the running speed of the magnetic tape at the time, the so-called high-speed playback operation is performed, and even if a high-speed playback operation is performed, a reproduced image that can confirm the image content recorded on the magnetic tape is viewed. In order to make it possible to confirm the image content recorded on the magnetic tape within a short time compared to the time required for recording the image, a high-speed reproduction operation has been performed. .

Incidentally, the pattern of the recording trace formed on the magnetic tape according to the rotation locus of the rotary magnetic head of the helical scan type VTR as described above depends on the diameter of the drum, the number of rotations of the rotary magnetic head, the number of rotations of the rotary magnetic head. Since it is determined by various conditions such as the rotation direction, the running speed of the magnetic tape, the running direction of the magnetic tape, the track angle, the head track width, and the recording area width of the magnetic tape, the operation mode of the VTR (normal playback mode, high-speed playback mode, etc.) By changing the various trick play operation modes), for example,
When the conditions such as the running direction and the running speed of the magnetic tape change, the pattern of the rotation locus of the rotary magnetic head drawn on the magnetic tape by the rotary magnetic head changes.

Therefore, during normal recording / reproducing (normal recording / reproducing), the rotating locus of the rotating magnetic head drawn on the magnetic tape by the rotating magnetic head and the rotating magnetic head drawn on the magnetic tape by the rotating magnetic head during trick play. The rotation locus of the head intersects. Therefore, the signal level of the frequency modulated wave signal of the reproduced signal reproduced at the time of trick play changes greatly every time the rotating magnetic head crosses the recording trace, and the frequency modulated wave of the reproduced signal in one vertical scanning period is changed. Looking at the signal envelope, large undulations occur during one vertical scanning period. Therefore, as a reproduced image at the time of trick play, only a reproduced image of poor quality having noise bars in the image can be obtained. .

In order to solve the above-mentioned problem, it is only necessary to make the rotation locus of the rotary magnetic head coincide with the recording trace of the magnetic tape T. Conventionally, as an actuator in an open loop control circuit or a closed loop control circuit, A rotating magnetic head is attached to the electro-mechanical transducer used, and the rotating magnetic head is displaced by the electro-mechanical transducer so that the rotating magnetic head can be traced to the recording mark of the magnetic tape. As disclosed in JP-A-63-34126 and JP-A-61-158633, the rotating drum on which the rotating magnetic head is mounted and the lower drum are integrally inclined so that the rotating head is A magnetic tape for a drum can be traced, for example, as disclosed in JP-B-61-22376. By changing the height of guides for limiting the height in the width direction of the magnetic tape provided on the entrance side and the side where the magnetic tape is released from the drum, the rotating head can track the recording trace of the magnetic tape T. Various solutions have been proposed, such as
An upper drum having a sliding surface with respect to a magnetic tape wound around a part of the peripheral surface of the upper and lower drums, a rotating magnetic head, and an extended surface of the sliding surface of the magnetic tape on the upper drum; In addition to the magnetic tape sliding contact surface, the lower drum, which is provided coaxially with the upper drum, and the rotation track surface of the rotating magnetic head are aligned with the recording marks formed on the magnetic tape. First tilt drive means for tilting the central axes of the upper and lower drums and the rotary magnetic head by a predetermined angle; and the lower and upper drums being separate from the upper and lower drums. A guide member for regulating the position of the reference edge of the magnetic tape, the guide member for regulating the position of the reference edge of the magnetic tape, which is disposed close to the outer peripheral surface of the small diameter portion formed at the lower part of the magnetic tape, and the position of the magnetic tape Replace the regulating guide member with a magnetic Flop magnetic recording and reproducing apparatus comprising a second inclined drive means for tilting to match the reference edge position of has been proposed.

[0006] By applying the various solutions as described above, a VTR capable of obtaining a good reproduced image without bar noise even in the high-speed reproduction mode has been provided. In addition, if it is realized that the quick preview by the high-speed reproduction image of good image quality without noise is realized,
It seems that something is not enough that no sound is attached to the reproduced image, and in addition to the sound signal accompanying the video signal, the sound signal is reproduced when the magnetic tape is played at high speed. However, since it is possible to expand various uses if the information content can be clearly understood, it has been demanded that an audio signal can be reproduced even during high-speed reproduction.

On the other hand, in a tape recorder, by increasing the running speed of the magnetic tape during reproduction as compared with the running speed of the magnetic tape during recording, a long recording content can be compared with the time required during recording. Listening within a short period of time has conventionally been performed. However, since the acoustic signal reproduced from the magnetic tape when the high-speed reproduction is performed as described above is in a state where the pitch is converted to a higher frequency, the running speed of the magnetic tape is simply recorded. Digital data obtained by sampling and quantizing a time-axis compressed audio signal that has been played back from a magnetic tape at high speed with a short sampling cycle can not be grasped satisfactorily just by making it faster than usual. Is stored in a memory, and the digital data of the time-axis compressed sound signal is read out at a period longer than the sampling period to reduce the frequency and perform pitch conversion to obtain an original sound signal that can be heard well. A tape recorder and a VTR equipped with an audio signal processing device have been proposed.

In the above-described audio signal processing apparatus, for each block of the time-axis compressed audio signal divided for each predetermined time, only a short cycle of the time-axis compressed audio signal within a time shorter than the predetermined time is used. The digital data obtained by sampling and quantization is stored in a memory, and the digital data of the time-axis compressed acoustic signal is read at a period longer than the sampling period over the predetermined time, and the pitch conversion is performed. Since the sampling and quantization are performed, the sampling and quantization operation for the time axis compressed sound signal of a certain block is completed, and the time axis from the start of the sampling and quantization for the time axis compressed sound signal of the next one block is started. The compressed sound signal is discarded. The digital data obtained by sampling and quantizing the time-axis compressed audio signal of each block is usually stored as a series of signals from a minimum address to a maximum address of a memory. In some cases, the digital data stored in the memory is 1
In the time axis compressed sound signal of the block, for example, if a silent period is included, the series of signals becomes short,
There is a problem that the reproduced signal is hard to hear. Therefore, during a silent period, a device which makes it easier to hear the contents of a series of signals without writing to a memory (for example, Japanese Patent Laid-Open No.
No. 5656) has been proposed.

[0009]

According to the above-mentioned conventional apparatus, a silent sound portion is not written in a memory, and a continuous sound content is extended to obtain a reproduced sound signal which is easy to hear. That was achieved, but it was difficult to achieve both the problem of how to set the criterion for the detection of silence, and the good balance between good silence removal and audio processing suitable for image scenes. There was a problem. Next, the above problem will be specifically described. As described above, in order to delete a silent part, it is necessary to detect a silent part. As the silent portion detecting device, a device that does not make a determination based on the level of an acoustic signal with respect to a certain threshold value is used. However, the sound signal to be recorded usually contains not only the voice of conversation but also surrounding sounds and the like, and further, the signal contains noise. Therefore, the threshold value to be set in the silent portion detecting device is not set so that the silent state is determined based on the state of the signal level 0, but is set to a minute value close to 0. An acoustic signal smaller than the value is determined to be silent.

FIG. 6 is a block diagram of a conventional apparatus. FIG.
Is an input terminal of a time-axis compressed sound signal reproduced at high speed, and the time-axis compressed sound signal supplied to the input terminal 1 is supplied to an analog-to-digital converter (ADC) 3 via a low-pass filter (LPF) 2. Is entered. The time-axis compressed sound signal is sampled and quantized at high speed at a predetermined sampling period in the analog-to-digital converter 3, and digital data based on the time-axis compressed sound signal is written into the memory 10. Digital data read from the memory 10 at a predetermined period longer than the above-described sampling period is converted into a digital-to-analog converter (DA).
C) After being converted into an analog signal by 4, it is sent to an output terminal 6 via a low-pass filter (LPF) 5.

Reference numeral 9 denotes a control circuit (CTL). The control circuit 9 includes a memory write address counter (WCNT).
A signal CK serving as a reference signal for the thirteen clock signals WCK
1. A signal CK2 serving as a reference signal of a clock signal RCK of a memory read counter (RCNT) 16, a write / read selection signal RW and a memory control signal CS, a clock signal ADCK of the analog-digital converter 3, and a clock signal of the digital-analog converter 4. A signal DACK and other necessary signals are generated. In FIG. 6, WAD indicates a write address value, and RAD indicates a read address value. Reference numeral 17 denotes a comparator (CMP).
Outputs a high-level signal EQ (see FIG. 7D) when the write address value WAD matches the read address value RAD.

Reference numeral 11 denotes an address selection circuit (SEL),
This address selection circuit 11 receives a write / read selection signal RW
Is at a high level, the read address value RA
D, and supplies it to the memory 10 as an address signal ADR.
Is at a low level, the write address value W
AD is selected and supplied to the memory 10 as an address signal ADR. Reference numeral 7 denotes a silence detection unit. When the input signal falls below a predetermined level, the silence detection unit 7
Silence state signal SI in a high level state (indicating a silence state)
[See (b) of FIG. 7] is output. The silence state signal S
When I becomes a low level state (indicating a sound state), the write enable signal WEN output from the inverter 8 is output.
[See (c) of FIG. 7] becomes a high level state, whereby the reference signal C of the memory write address counter 13 is changed.
K1 is used as a clock signal WCK of the memory write address counter 13 via the AND circuit 12, and is input to the memory write address counter 13 to advance the address. When the silent state signal SI is at a high level, the clock signal WCK of the memory write address counter 13 is not generated.

When the silent state signal SI is high (silent state), the write address value WAD matches the read address value RAD, and the output signal EQ of the comparator 17 becomes high. When this happens, the read enable signal REN (see FIG. 7 (e)) output from the NAND circuit (NAND) 14 is at a low level, the output signal RCK of the AND circuit 15 is at a low level, and memory read is performed. The counting operation of the counter 16 stops. The read enable signal REN output from the NAND circuit 14 is at a high level under other conditions. When the read enable signal REN is at the high level, the reference signal CK2 is used as the clock signal RCK of the memory read counter 16 via the AND circuit 15, whereby the memory read counter 16 advances the address.

FIG. 7 shows a change state of a memory address in a case where the conventional apparatus shown in FIG. 6 performs signal processing of a time axis compressed acoustic signal reproduced from a recording medium at a speed twice as fast as a recording speed at the time of recording. [(A) of FIG. 7] and a silent state signal SI among output signals of each component of the device [FIG.
(B)], the write enable signal WEN [(c) in FIG. 7] output from the inverter 8, the output signal EQ [(d) in FIG. 7] of the comparator 17, and the read enable output from the NAND circuit 14. 8 is a time chart illustrating a change state of a signal REN [(a) of FIG. 7].

In the example shown in FIG. 7, it is assumed that the device starts a write operation and a read operation at time t1. First, during the period from time t1 to time t4, since the silent state signal SI is a sounded portion indicating a low level state, the write enable signal WEN output from the inverter 8 is at a high level state. Therefore, since the clock signal WCK of the memory write address counter is being supplied to the memory write address counter 13 via the AND circuit 12, the memory write address counter is supplied over the period from the time t1 to the time t4. The counter 13 continues the counting operation. The manner of change of the write address value WAD by the counting operation of the memory write address counter 13 over the above-mentioned sound portion period from the time t1 to the time t4 is shown in FIG. …… Is indicated by a straight line drawn by a broken line connecting points リ, ヌ, →, ヲ. In FIG. 7A, a solid line indicated by a drawing symbol RAD indicates a read address value R.
The state of the change of AD is shown, and MIN at the left end of the figure shows the start address value of the memory, and MAX shows the end address value of the memory.

Next, during a period from time t4 to time t5, a silent section in which the silent state signal SI indicates a high level state, and during this silent section, the write enable signal WEN output from the inverter 8 is supplied. It is in a low level state. Since the supply of the clock signal WCK of the memory write address counter from the AND circuit 12 to the memory write address counter 13 is stopped during the silent period, the silence period between the time t4 and the time t5 is reduced. The memory write address counter 13 does not perform a counting operation. Therefore, the write address value WAD during the silent period from the time t1 to the time t4 retains the same value as shown by the straight line connecting the points ヲ → W in FIG. 7A. ing.

Next, at time t5, the silence state signal SI becomes a sounded portion indicating a low level state, so the write enable signal WE output from the inverter 8 at time t5.
N goes into a high level state, and the memory write address counter 13 restarts the counting operation. Then, the counting operation of the memory write address counter 13 is continued over a sound part period from time t6 when the silent state signal SI changes from a low level to a silent part indicated by a high level. Thus, the write address value WAD obtained by the counting operation of the memory write address counter 13 over the sound period from the time t5 to the time t6.
7 is indicated by a straight line drawn by a broken line connecting points W, F, Y, and T in FIG. 7A.

During the period from time t6 to time t8, the silent state signal S
I is a silent portion indicating a high level state. During this silent portion period, since the memory write address counter 13 does not perform a counting operation as described above, the silent portion from the time t6 to the time t8 is The write address value WAD during the unit period keeps the same value as shown by the straight line connecting the point to the point in FIG. 7A. In the illustrated operation example, as shown in FIG. 7D, the output signal EQ of the comparator 17 is output at time t1, time t2, time t3, and time t3.
The state changes to a high level from 7 to time t8. Since the silence state signal SI is at the low level at the times t1, t2, and t3, the read enable signal REN output from the NAND circuit 14 remains at the high level.

The memory write address counter 13 stops counting during the silent period from time t6 to time t8. However, since the silent period from time t6 to time t8 is long, the write address The value WAD and the read address value RAD have the same address value, and the output signal EQ of the comparator 17 is at a high level. So time t
7, the read enable signal REN output from the NAND circuit 14 is at a low level, and at time t7, the AND condition of the AND circuit 15 is not satisfied.
Is not supplied to the memory read counter 16, and the counting operation of the memory read counter 16 stops at time t7.

At time t8, the silence state signal SI becomes a sounded portion indicating a low level state, the write enable signal WEN output from the inverter 8 becomes a high level state, and the clock signal of the memory write address counter is output. WCK is supplied to the memory write address counter 13 via the AND circuit 12, and the memory write address counter 13 starts counting operation from the time t8. FIG. 7 shows how the write address value WAD changes due to the counting operation of the memory write address counter 13 during the sound period from the time t8.
(a) It is shown by a straight line indicated by a broken line connecting points d → d → d → d → d → d.

In the conventional apparatus described so far with reference to FIGS. 6 and 7, when the input signal falls below a predetermined level, the high-level silence state signal S is output.
When the period in which the silent state is determined by the silent state determination unit 7 that outputs I is long, such as the period from time t6 to time t8 shown in FIG. 7, at time t7 in the above-mentioned period. Write address value WAD and read address value R
When AD has the same address value, the output signal EQ of the comparator 17 is at a high level, the read enable signal REN output from the NAND circuit 14 is at a low level, and at time t7, the AND circuit 15 Since the condition is no longer satisfied, the clock signal RCK of the memory read counter is no longer supplied to the memory read counter 16 at time t7, and the counting operation of the memory read counter 16 stops at time t7, so that the period shown from time t7 to time t8 In the memory 10, the operation of repeatedly writing digital data based on the time axis compressed acoustic signal sequentially output from the analog-to-digital converter 3 to the same address and reading the written digital data is performed. Become.

By the way, the silence judgment by the silence judging section 7 is performed by setting a certain threshold value to determine whether the input signal has fallen below a predetermined level. Even when the silent state is determined by the unit 7, since there are many cases where an acoustic signal such as an ambient sound equal to or less than the threshold is included, the silent state is determined by the silent state determining unit 7. During the period from the time t7 to the time t8 during the period from the time t6 to the time t8,
As a result of the reading operation, an acoustic signal having a very small signal level in a state where the time axis is not extended is output. Then, the sound reproduced in the above state becomes noise of unknown meaning.

The above problem is that the writing operation and the reading operation of the memory 10 are stopped during the period from the time t7 to the time t8 during the period from the time t6 to the time t8 when the silent state is judged by the silence judging section 7. However, if such a means is applied, the period from the time t7 to the time t8 becomes a completely non-signal state, giving a great sense of discomfort to the viewer. In particular, in a VTR equipped with a function that enables a quick view, a situation may occur in which a completely silent state suddenly occurs despite that there should be ambient sounds while a reproduced image is displayed. Gives a very unnatural feeling. In order to prevent such an unnatural state from occurring, for example, it is conceivable to set the threshold value in the silence determination unit 7 to a very low level. It becomes difficult to remove the unnecessary sound, and the problem is that the original purpose, that is, the efficient silence removal operation cannot be performed.

In the conventional device, if there are many silent parts,
The silence elimination operation results in a longer continuous processing time, but if there is less silence, the read address is immediately overtaken by the write address, and further writing is performed on information that has already been written and has not been read. However, in the method of comparing the write address with the read address, a serious malfunction (for example, a new write is interrupted due to a non-integer multiple speed process or a phase shift of a clock signal). (The data read once is output over the signal of one block). Therefore, an acoustic signal processing device free from the above-mentioned various problems has been demanded.

[0025]

SUMMARY OF THE INVENTION According to the present invention, a time axis compressed audio signal reproduced from a recording medium at a speed higher than the recording speed at the time of recording is sampled and quantized at a predetermined sampling period to obtain an audio signal. Analog-to-digital conversion means for obtaining digital data of the above, a memory for writing and storing the digital data of the above-mentioned acoustic signal at the above-mentioned predetermined sampling period, and a read-out period longer than the above-mentioned sampling period, Means for reading the digital data of the acoustic signal read from the memory, and digital-to-analog converting means for converting the digital data of the acoustic signal read from the memory from digital to analog and outputting it as an audio signal in the form of an analog signal In the signal processing device, the reading of the digital data of the acoustic signal from the memory described above,
Means for performing a cyclic operation from the first address to the last address of the memory, and unread data for detecting an unread state data amount of digital data of the audio signal written in the memory. Means for detecting the amount of data, means for detecting that the amount of unread data is within a predetermined lower limit, and detecting that the amount of unread data is within a predetermined upper limit. Means for detecting, a low-tone state detection means for detecting a low-tone state below a predetermined signal level including a silent state,
Means for stopping the progress of the write address when the unread data amount falls within the predetermined upper limit range, and when the unread data amount falls within the predetermined lower limit range Means for resuming the progress of the write address, means for interrupting the progress of the write address when a low tone state below a predetermined signal level including a silent state, and a predetermined state including a silent state If the amount of unread data falls within a predetermined lower limit while the progress of the write address is stopped due to a low tone level below the signal level, the progress of the write address is restarted. Means for causing a write address and a read address to be set when a loud state equal to or higher than the predetermined signal level is reached after the progress of the write address is resumed. To provide an acoustic signal processing apparatus comprising a means for matching or near value and a scan.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific contents of an audio signal processing device according to the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a block diagram showing an embodiment of an audio signal processing apparatus according to the present invention. In the sound signal processing apparatus of the present invention shown in FIG. 1, reference numeral 1 denotes an input terminal of a time-axis compressed sound signal reproduced at high speed. The time-axis compressed sound signal supplied to the input terminal 1 is a low-pass filter (LPF) 2 Is input to an analog-to-digital converter (ADC) 3 via the. The time-axis compressed sound signal is converted by the analog-to-digital converter 3 into
High-speed sampling and quantization at a predetermined sampling period,
Digital data based on the time axis compressed sound signal is written into the memory 10. Digital data read from the memory 10 at a predetermined period longer than the above-described sampling period is converted into an analog signal by a digital-to-analog converter (DAC) 4 and then converted to a low-pass filter (L).
PF) 5 to an output terminal 6.

Reference numeral 9 denotes a control circuit (CTL), which is a memory write address counter (WCNT).
p) Signal C serving as a reference signal for clock signal WCK of 27
K1, a clock signal RCK of a memory read counter (RCNT) 31, a write / read selection signal RW, a memory control signal CS, and a clock signal A of the analog-to-digital converter 3.
It generates DCK, the clock signal DACK of the digital-to-analog converter 4, and other necessary signals. In FIG. 1, WAD indicates a write address value, and RAD indicates a read address value. The above-mentioned memory write address counter (WCNTp) 27 is a counter with a preset function. When the preset signal PR given to the memory write address counter 27 becomes a high level, the memory write address counter 27 reads out as described later. Load address value RAD.

Reference numeral 11 denotes an address selection circuit (SEL). When the write / read selection signal RW is at a high level, the address selection circuit 11 selects a read address value RAD and uses it as an address signal ADR. When the write / read select signal RW is at a low level, the write address value WAD is selected and supplied to the memory 10 as an address signal ADR. Reference numeral 34 denotes a low-pitched sound detecting section. The low-pitched sound detecting section 34 outputs a low-pitched sound signal SM (indicating a low-pitched sound state) when the input signal falls below a predetermined level [see FIG. (E), see (b) of FIG. 4].

FIG. 2 is a block diagram showing an example of the configuration of the above-mentioned small sound detector 34, and FIG. 4 is a waveform diagram for explaining the operation of the small sound detector 34 shown in FIG. In the example of the configuration of the small sound detector 34 shown in FIG. 2, 35 is a rectifier circuit (RCT).
The time-axis compressed acoustic signal Sa as shown in FIG. 3A supplied to the input terminal 34a of the small-tone detector 34 is rectified by the rectifier circuit 35 and is then rectified in FIG.
The signal Sb is as shown in FIG. The output signal Sb of the rectifier circuit 35 is supplied to the voltage comparator 37. The voltage comparator 37 is supplied with a threshold voltage Vc generated by a reference voltage generation circuit (REF).

In the above-mentioned voltage comparator 37, the output signal Sb of the rectifier circuit 35 shown in FIG. 3B output from the rectifier circuit 35 and the reference voltage generator 37 generate the output signal Sb. By comparing the threshold voltage Vc with the threshold voltage Vc, a pulse train Pd as shown in FIG. 3C is output and supplied to the retrigable monostable multivibrator 38 as a trigger signal. The retriggerable monostable multivibrator 38 is retriggered when the interval between trigger signals sequentially supplied thereto is within a predetermined time, as shown in FIG. 3D. When the signal level of a sound signal falls below a predetermined level,
When the signal level becomes low and the signal level of the sound signal exceeds a predetermined level, a pulse Pe that becomes high level is generated and supplied to the inverter 39. Thus, as shown in FIG. 3 (e), when the signal level of the acoustic signal falls below a predetermined level, the inverter 39 enters a high level state (indicating a small sound state). When the signal level of the sound signal becomes equal to or higher than a predetermined level, a low sound level signal SM (indicating a loud sound state) is transmitted to the output terminal 34b.

In FIG. 1, reference numeral 28 denotes a written / unread data amount counter (WDCNT) 28 which is constituted by a presettable up / down counter, and the written / unread data amount counter 28 (unread data amount counter 28). Then, the amount of data that has been written to the memory 10 but has not been read yet is counted. Thus, the output signal WT from the unread data amount counter 28 is
D is a count value indicating the amount of data that has been written and not yet read. By the way, in order to prevent a malfunction that has occurred in the above-described conventional device, it is necessary to control so that the amount of data that has been written and not yet read always falls within a predetermined range.

Therefore, in the embodiment of the audio signal processing apparatus shown in FIG. 1 of the present invention, the unread data amount counter 2
8 is output to a lower limit range detector (LWRD).
ET) 29 and an upper limit range detector (UPRDET) 30. In the lower limit range detector 29, the unread data amount indicated by the output signal WTD from the unread data amount counter 28 is predetermined. When it is within the lower limit range, the lower limit amount detection signal LWR is output and supplied to the AND circuit 20. In the upper limit range detector 30, the output signal WTD from the unread data amount counter 28 is used. When the indicated unread data amount is within a predetermined upper limit range, upper limit amount detection signal UP
R is output and supplied to the OR circuit 22.

Now, as an example, it is assumed that the memory 10 has a size of 8 × 32 Kbytes and has a 15-bit address. The lower limit range detector 29 and the upper limit range detector 30 shows an example of the configuration.
First, the lower limit range detecting section 29 stores the above-mentioned memory 1
Of the 15-bit address of 0, the upper 8 bits are "0
In the state of “00000000”, the lower limit amount detection signal LWR of the high level state is output, and the upper limit range detector 30 sets the upper 8 bits of the 11-bit address of the memory 10 to “11111110”. ”, The upper limit amount detection signal UPR in the high level state is output. FIG. 5 shows a predetermined lower limit range for outputting the lower limit amount detection signal LWR from the lower limit range detection unit 29 and a predetermined upper limit range for outputting the upper limit amount detection signal UPR from the upper limit range detection unit 30. The dead zone in the figure is provided so as to prevent malfunction due to noise mixing or other causes.

The reference signal CK1 of the memory write address counter becomes the clock WCK of the memory write address counter via the AND circuit 26, and is input to the memory write address counter 27 to advance the address. Further, the memory read counter 31 constantly performs an adding operation cyclically from the start address to the end address of the memory 10 to advance the address. The manner in which the write address value WAD indicated as the count value of the memory write address counter 27 changes is indicated by a broken line WA in FIG.
As exemplified by D, the data is not linear on the time axis according to the amount of written / unread data that has been generated based on the state of change in the signal level of the original audio signal.

The read address value RAD indicated as the count value of the memory read counter 31 is shown in FIG.
As illustrated by a solid line RAD therein, a change such that the read address value RAD changes from the start address to the end address of the memory 10 and then changes again from the start address to the end address of the memory 10 on the time axis. , The memory read counter 31 cyclically changes the read address value RAD from the start address to the end address of the memory 10 as described above. I have.

FIG. 4 shows a change in memory address when the above-described acoustic signal processing apparatus performs signal processing on a time-base compressed acoustic signal reproduced from a recording medium at twice the recording speed during recording. State [(a) of FIG. 4]
5 is a time chart illustrating a state of a change in an output signal of each component of the apparatus [(b) to (n) of FIG. 4]. In the example shown in FIG. 4, the operation start pulse PRS is supplied to the terminal 32 of the acoustic signal processing device at time t1.
When [(m) in FIG. 4] is input, the acoustic signal processing device starts the writing operation and the reading operation at time t1. When the operation start pulse PRS described above is input to the preset terminal of the memory write address counter 27 via the OR circuit 33, the memory write address counter 27 loads the read address value RAD and writes the read address value WA.
D is made to match the read address value RAD.

As described above, since the write address value WAD and the read address value RAD are the same at time t1, the lower limit range detector 29 outputs the lower limit amount detection signal LWR at time t1 ((f in FIG. 4). )] Is output, and the lower limit detection signal LWR is output from the OR circuit 21 and the AND circuit 2
0 and given. By the way, at time t1 which is a sound part, since the low-pitched sound state signal SM [(b) in FIG. 4] indicates a low level state, the above-mentioned lower limit detection signal LWR is output from the AND circuit 20. Not done. On the other hand, the lower limit detection signal LWR output from the lower limit range detector 29 at time t1 is output via the OR circuit 21 to the set signal PWR.
The set / reset flip-flop 24 given to the set terminal S as s2 outputs the write enable signal WEN from the Q terminal at time t1, and supplies it to the AND circuit 26.

The AND circuit 26 supplies the reference signal CK1 of the clock signal WCK of the memory write address counter supplied from the control circuit 9 to the memory write address counter 27 as the clock signal WCK of the memory write address counter. Then, the memory write address counter 27 starts the counting operation from time t1. In the example shown in FIG. 4A, the write address value WAD and the read address value RAD at time t1 indicate an address value corresponding to the point A. The aforementioned memory write address counter 27
Of the memory write address counter 27
Is changed on a straight line WAD indicated by a broken line connecting points A, B, C, D, E, and E in FIG. 4A. go. on the other hand,
As described above, the memory read address counter 31 outputs the read address value RAD that constantly changes between the start address value and the end address value of the memory 10. The state of the change of the read address value RAD is indicated by a solid line indicated as RAD in FIG.

The above-mentioned memory write address counter 27
A write address value WAD output from the memory write address counter 27 which has been changed by the counting operation of
A lower limit range detector 29 and an upper limit range detector receiving an output signal WTD from a written / unread data amount counter 28 to which a read address value RAD changed by the counting operation of the memory read address counter 31 is supplied. An upper limit range detection unit 30 of the unit 30 detects that the unread data amount falls within a predetermined upper limit range at time t2, and outputs a high level upper limit amount detection signal UPR [FIG. 4 (e)] is output. The upper limit amount detection signal UPR is supplied from the OR circuit 22 to (i) of FIG.
Is applied to the reset terminal R of the set / reset flip-flop 24 to reset the set / reset flip-flop 24 at time t2.

Thus, the aforementioned set, reset,
The write enable signal WEN output from the Q terminal of the flip-flop 24 changes to a low level state at time t2 and the AND circuit 26 closes the gate.
The clock signal WCK that has been supplied from the AND circuit 26 to the memory write address counter 27 until that time is no longer provided to the memory write address counter 27, and the counting operation of the memory write address counter 27 stops at time t2. Since the reading of digital data from the memory 10 is continued after the time t2, the amount of unread data in the memory 10 is equal to the time t2.
Then it gradually decreases. The lower limit range detector 29 to which the output signal WTD from the written / unread data amount counter 28 is provided detects that the unread data amount falls within the predetermined lower limit range at time t3. Then, the lower limit range detecting section 29 outputs the time t3
And outputs a high-level lower limit detection signal LWR [(f) in FIG. 4] to the AND circuit 20 and the OR circuit 2.
1 and supply.

The lower limit detection signal LWR in the high level state supplied to the OR circuit 21 is the OR circuit 2
1 to the set terminal P of the set / reset flip-flop 24 as a set signal Ps2 shown in FIG. 4 (h). The write enable signal WEN in the state of
6 Then, the AND circuit 26 operates at time t.
The write enable signal WE in a high level state from 3
The gate is opened by N, and the clock signal WCK of the memory write address counter is supplied to the memory write address counter 27 from time t3, whereby the memory write address counter 27 starts counting operation from time t3.

In the example shown in FIG. 4A, at time t3
Is a write address value WAD corresponding to the point t in the figure [the time t indicated by the point e in FIG.
2 is the same as the address value corresponding to the write address value WAD]. Then, by the counting operation of the memory write address counter 27, the write address value WAD output from the memory write address counter 27 is output.
Changes on a straight line WAD indicated by a broken line connecting points G, H, R, and N in FIG. 4A. Time t4
The low tone state signal SM [(a) in FIG. 4] output from the low tone detection unit 34 at the low level state (the sound part,
The monostable multivibrator 19 triggers when the low-level state signal SM changes from a low-level state to a high-level state. The pulse SMu shown in FIG. 4B is generated from the monostable multivibrator 19 at time t4.

The pulse SMu generated at the time t4 from the monostable multivibrator 19 is used as the reset signal Pr2 shown in FIG. 4 (i) by the OR circuit 22 to reset the set / reset flip-flop 24. By being supplied to the terminal R, the set / reset flip-flop 24 is reset at time t4. As a result, the write enable signal WEN output from the Q terminal of the set / reset flip-flop 24 changes from the high level state to the low level state at time t4, and the AND circuit 26 closes the gate. And the clock signal W which has been supplied from the AND circuit 26 to the memory write address counter 27 until then.
CK is no longer provided to the memory write address counter 27, and at time t4, the memory write address counter 2
The counting operation of 7 stops.

At time t5, the low-pitched sound state signal SM (FIG. 4A) output from the low-pitched sound detection section 34 changes from a high level state (small part, silent part) to a low level state (large part). When the above-mentioned low tone state signal SM changes from a high level to a low level, the signal output from the inverter 8 changes from a low level to a high level. The monostable multivibrator 18 is triggered to change to the state at time t5.
From the monostable multivibrator 18 at time t
5 generates the pulse SMd shown in FIG. The pulse SMd output from the monostable multivibrator 18 passes through the OR circuit 21 and the set / reset flip-flop 24 given to the set terminal S as the set signal Ps2 receives the write enable signal from the Q terminal at time t5. WEN is output and supplied to the AND circuit 26. Then, the AND circuit 26 supplies the clock signal WCK of the memory write address counter to the memory write address counter 27, whereby the memory write address counter 27 starts counting operation from time t5.

The pulse SMd output from the monostable multivibrator 18 at time t5 is also supplied to the reset terminal R of the set / reset flip-flop 23. Reference numeral 23 denotes a set / reset flip-flop 2 at time t5 because it has not been set yet.
The pulse SMd supplied to the reset terminal R of No. 3 does not change the operation state of the set / reset flip-flop 23, and the Q bar terminal of the set / reset flip-flop remains at the high level even at time t5. Is done.

As described above, the write address value WAD output from the memory write address counter 27 which has restarted the counting operation at the time t5 is calculated as shown in FIG. A straight line WA indicated by a broken line connecting the points of power
It changes on D. At time t6, the small sound detector 34
Low-pitched sound state signal SM [(b) in FIG. 4]
Changes from the low-level state (sound part, loud part) to the high-level state (small part, silent part), and the low-tone state signal SM changes from the low-level state to the high-level state. At the time of change, the monostable multivibrator 19 is triggered, and the pulse SMu output from the monostable multivibrator 19 at the time t6 is output from the OR circuit 22 as the reset signal Pr2 shown in FIG. , Reset terminal R of set / reset flip-flop 24
Given to.

As a result, the set / reset flip-flop 24 is reset at time t6, and the write enable signal WEN output from the Q terminal changes from a high level to a low level at time t6. As a result, the AND circuit 26 closes the gate, and the clock signal WCK that has been supplied from the AND circuit 26 to the memory write address counter 27 is no longer supplied to the memory write address counter 27. At time t6, the memory write address counter 27 The counting operation stops. By the way, during the low-tone period started at time t6, the low-tone state signal SM output from the low-tone detection unit 34 next.
For a long period from time t8 when the state changes from the high level state (small sound section and silent section) to the low level state (loud section and sound section).

The above-mentioned memory write address counter 2
7 keeps the memory 10 after the time t6 when the counting operation is stopped.
Since the reading of the digital data from the memory 10 is continuously performed, the memory 10 gradually decreases after time t6.
At time t7 before time t8 when the low-pitched portion period started at time t6 changes to a loud period,
The unread data amount may fall within a predetermined lower limit. As described above, when the unread data amount falls within the predetermined lower limit range, the lower limit range detection unit 29 to which the output signal WTD from the written and unread data amount counter 28 is applied is turned on at time t7. It is detected that the unread data amount falls within the predetermined lower limit range, and the lower limit range detection unit 29 outputs the high-level lower limit amount detection signal LWR at time t7 [(f) of FIG. And outputs it to the AND circuit 20 and the OR circuit 21.

The lower limit detection signal LWR in the high level state supplied to the OR circuit 21 is
1 to 4 (h) is applied to the set terminal S of the set / reset flip-flop 24 as the set signal Ps2, so that the Q terminal of the set / reset flip-flop 24 is output from the time t7. The write enable signal WEN at the high level is output and supplied to the AND circuit 26. So the AND circuit 26
Opens the gate with the write enable signal WEN at the high level from time t7, and supplies the clock signal WCK of the memory write address counter to the memory write address counter 27 from time t7, whereby the memory write address counter 27 The counting operation starts at time t7. At time t7, the low-pitched sound state signal SM [(b) in FIG. 4] output from the low-pitched sound detection section 34 is in a high-level state (small and silent sections). At time t7, the lower limit range detector 29
From the high-level lower limit detection signal LW
R [(f) in FIG. 4] is given as a signal Pw [(g) in FIG. 4] to the set terminal S of the set / reset flip-flop 23, whereby the set / reset flip-flop 23 is set. .

The write address value WAD output from the memory write address counter 27 which has started the counting operation as described above corresponds to each of the following points in FIG. It changes on the straight line WAD indicated by the dashed line, but the period from the time t7 to the time t8 is the time t6.
Since this is a period during the small-tone period from to t8, the time-axis compressed acoustic signal written to the memory 10 during the period from the time t7 to the time t8 during the small-tone period is
This is a time-axis compressed sound signal having a small signal level during a small sound period. That is, in the acoustic signal processing device of the present invention, a small signal of a predetermined signal level or less from the head address of the memory 10 to the maximum address for a longer time than the time required for the read address value WAD to change. In the case of the low-pitched sound period in which the level audio signal continues, the time axis compressed audio signal based on the audio signal of the paired signal level which is not originally targeted for writing is written in the memory 10, and By reading the compressed time-base sound signal from the memory 10 in a state where the predetermined time-base expansion has been performed, it is possible to prevent a situation in which the reproduction sound is interrupted even when the small sound period is long. .

At time t8, the low tone state signal SM ((b) in FIG. 4) output from the low tone detection section 34 changes from the high level state (small part and silent part) to the low level state (large part). (A sound part, a sound part), the signal output from the inverter 8 changes from a low level state to a high level state.
Is triggered and the monostable multivibrator 18 is
Generates a pulse SMd shown in FIG. 4D at time t8. The pulse SMd output from the monostable multivibrator 18 is supplied to the set terminal S of the set / reset flip-flop 24 as the set signal Ps2 via the OR circuit 21. Is set at time t7 as described above, so that the set signal Ps2 at time t8 does not change the operation state of the set / reset flip-flop 24.

The pulse SMd output from the monostable multivibrator 18 at the time t8 is supplied to the reset terminal R. The set / reset flip-flop 23 is reset at the time t8, and the low level is applied from the Q bar terminal thereof. A signal P that changes from a high-level state to a high-level state
wt [(k) in FIG. 4] is output. The above signal Pwt
Triggers the monostable multivibrator 25, the monostable multivibrator 25 outputs a signal PRx, and the signal PRx [(l) in FIG.
3 as a preset signal PR [(n) in FIG. 4] of the preset terminal P of the memory write address counter 27.
Given to RT. As a result, the memory write address counter 27 reads the read address value R at time t8.
AD, and the write address value WAD is changed from the state where the write address value WAD matches the read address value RAD.
The counting operation of AD is restarted.

By the counting operation of the memory write address counter 27 started from the time t6 in the small tone period, the write address value WAD output from the memory write address counter 27 becomes a point Y in FIG. It changes on a straight line WAD indicated by a broken line that connects the points of → point → point → point. On the other hand, the memory read address counter 31
As described above, the read address value R which constantly changes cyclically between the start address value and the end address value of the memory 10
AD is output, and the state of change of the read address value RAD is indicated by a solid line indicated as RAD in FIG.

Now, when the amount of unread data in the memory 10 falls within a predetermined lower limit range at time t7 before time t8 when the low-pitched portion period started at time t6 changes to a loud-tone period. In the acoustic signal processing apparatus of the present invention, the time axis compressed acoustic signal having a small signal level during the small sound period is written in the memory 10 also during the period from time t7 to time t8 during the small sound period. However, even in the case where the small sound period is long, it is possible to prevent a situation where the reproduced sound is interrupted. However, when the small sound period changes from the small sound period to the large sound period at time t8, the content of the reproduced image and the reproduction sound Unless deviation from the content occurs, it is easy for the viewer to feel uncomfortable. That is, in the audio signal processing apparatus including the audio signal processing apparatus of the present invention, in which the time axis compressed audio signal is expanded on the time axis to obtain a reproduced audio signal, signal processing is performed based on the operation principle. Regarding the head of a series of blocks of the audio signal, the audio signal has the content corresponding to the image content of the reproduced image accompanied by the audio signal subjected to the signal processing described above. The reproduced sound reproduced in the state where the time axis is expanded is gradually delayed from the reproduced image content in the fast forward state.

By the way, even when an audio signal is being reproduced in the above-described state, a viewer who is watching the VTR at a glance can see that if the signal level of the reproduced audio continues in a uniform state, It is usual that you do not notice even if there is a slight time lag between the playback sound being played in a state where the time axis is expanded and the playback image content in the fast forward state, while watching without worrying about After the reproduction sound of the small signal level continues as described above, when the reproduction sound suddenly changes to the high signal level, if there is a difference between the contents of the reproduction sound and the contents of the reproduction image, This will make the viewer feel awkward. For example, the above point will be described as follows, taking as an example a case where a golf scene is reproduced at a high speed on a VTR. When a loud sound is generated by hitting the ball after a quiet period of time, no sound is produced even though the ball hits the golf club on the image,
If a hammering sound is heard late, the viewer will feel uncomfortable.

When the amount of unread data in the memory 10 is approaching the upper limit range due to the writing of digital data in the above-mentioned low-pitched period, the low-pitched period changes from the low-pit interval to the loud-pit period. If you do
While only a small amount of audio signal data during a loud section having important information content is written into the memory, the unread data amount in the memory 10 falls within the upper limit range, and the loud section having important information content It is also conceivable that the audio signal data of the period is not written.

Therefore, in the acoustic signal processing device of the present invention,
As described above, when the period changes from the period in which the time axis compressed acoustic signal of the small signal level in the small sound period is written to the memory 10 during the small sound period to the large sound period, the write address value WAD is changed. The read address value RAD at that time is forcibly changed so as to match or be close to the read address value RAD. That is, as described above, the write address value WAD output from the memory write address counter 27 is obtained by the counting operation of the memory write address counter 27 started from the time t6 in the small tone period.
However, as described above, point y → point → point → in FIG.
When changing from the low-pitched period to the high-pitched portion at the time t8 while changing on the straight line WAD indicated by the broken line connecting the points of the point S, (FIG. 4) at the time t8 a) The write address value WAD indicating the address value corresponding to the point S in FIG. 4A is forcibly changed to the read address value RAD indicating the address value corresponding to the point S in FIG. After time t8, it changes on a straight line WAD indicated by a broken line connecting points S, S, S, S, and S in FIG. 4A. As a result, when the audio level suddenly changes from the low-level audio to the high-level audio, the reproduced video and the reproduced audio of the VTR can be made to match, and the sense of discomfort can be reduced. In addition, by performing the above-described operation, the memory
The time for writing to 0 is maximized so that a signal that is easy to hear can be obtained.

[0058]

As is apparent from the above description, the acoustic signal processing apparatus of the present invention interrupts the progress of the write address when a low tone state including silence occurs, thereby improving the efficiency. It is possible to realize an easy-to-listen process with a long series of block times, and if the progress of the write address is stopped in a low-pitched state including silence, the written / unread information amount falls within the lower limit range. When
By resuming the progress of the write address, even if a low-level sound signal continues, the low-level signal is forcibly written to the memory, which causes an unnatural situation such as sudden complete silence. Further, as described above, when the period changes from the period in which the time axis compressed acoustic signal of the small signal level in the small sound period is written into the memory during the small sound period to the large sound period, the write address value is changed. Is forcedly changed so as to match or be close to the read address value at that time, so that the start of the video and the sound can be matched by the VTR so that the sense of discomfort can be reduced. Since the next writing is prohibited until the information is read, even if there are few low-pitched sound parts, an excellent effect is obtained, such as a long series of times and the output of easy-to-listen sound. Than it is. Further, according to the present invention, when a large-level audio signal and a small-level audio signal are properly mixed, the small-level signal is removed and the large-level audio signal is written into the memory, so that efficient audio processing is performed. A series of processing times are realized to output a sound signal that is easy to hear by extending the processing time. If a low-level sound signal continues, the low-level signal is forcibly written to the memory and suddenly enters a completely silent state. Such an unnatural phenomenon does not occur. In particular, since the processed audio signal is output in any case as the processing for the VTR, the atmosphere with the video can be adjusted, which is optimal. If the information is written once, the next write is prohibited until the information written once is read.
It is possible to output a sound that is easy to hear because the length of the series is long, and it is easy to set the low-pitched sound detection level, enabling reliable operation, and for non-integer multiple speed processing and clock timing deviation. However, a stable operation can be realized, and the apparatus can be provided at a low cost because it can be implemented with a simple circuit. According to the present invention, the above-mentioned problems in the conventional apparatus can be solved well. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example configuration of an audio signal processing device according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a small sound detection unit.

FIG. 3 is a waveform diagram for explaining the operation of the small sound detector.

FIG. 4 is a waveform diagram for explaining the operation of the acoustic signal processing device of the present invention.

FIG. 5 is a diagram for explaining a configuration of a written / unread amount counter.

FIG. 6 is a block diagram illustrating a configuration of a conventional acoustic signal processing device.

FIG. 7 is a waveform diagram for explaining the operation of the conventional acoustic signal processing device.

[Explanation of symbols]

2, 5 low-pass filter, 3 analog-to-digital converter, 4 digital-analog converter, 7 silent section detector
8 ... inverter, 9 ... control circuit, 10 ... memory, 11 ...
Address selection circuit, 12, 15, 20, 26 ... AND circuit, 13, 27 ... Memory write address counter, 14
... Nand circuit, 16, 31 ... Memory read counter, 1
7: comparator, 18, 19, 25: monostable multivibrator, 21, 22, 33: OR circuit, 23, 24: set / reset flip-flop, 28: written / unread amount counter, 29: lower limit range Detecting unit, 30: upper limit range detecting unit, 34: small sound detecting unit,

Continuation of the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G11B 20/00-20/04 G10L 3/02

Claims (1)

(57) [Claims] 1. An analog-to-digital converter that obtains digital data of an audio signal by sampling and quantizing a time-axis compressed audio signal reproduced from a recording medium at a speed higher than a recording speed at the time of recording at a predetermined sampling period. A conversion unit, a memory for writing and storing the digital data of the audio signal at the predetermined sampling cycle, and a read cycle longer than the sampling cycle, for converting the audio signal from the memory at the read cycle longer than the sampling cycle. A sound signal processing apparatus comprising: means for reading digital data; and digital-to-analog conversion means for converting digital data of an acoustic signal read from a memory into digital-to-analog and outputting as an audio signal in the form of an analog signal. The reading of the digital data of the acoustic signal from the memory is performed from the above-mentioned first address of the memory to the last address. Means for performing a cyclic operation until the data is read, an unread data amount detecting means for detecting an unread state data amount in the digital data of the audio signal written in the memory, and an unread data amount. A means for detecting that the data amount is within a predetermined lower limit range, a means for detecting that the unread data amount is within a predetermined upper limit range, and a silent state. A low-tone state detecting means for detecting a low-tone state below a predetermined signal level; and stopping the advance of the write address when the unread data amount falls within a predetermined upper limit range. Means for resuming the progress of the write address when the amount of unread data falls within a predetermined lower limit, and a signal level lower than a predetermined signal level including a silent state. Means for interrupting the progress of the write address in the case of a low tone state, and a state in which the progress of the write address is stopped due to a low tone state below a predetermined signal level including a silent state, Means for resuming the progress of the write address when the unread data amount falls within a predetermined lower limit range, and the predetermined signal level after the progress of the write address is resumed. Means for causing the write address and the read address to coincide with or be close to each other when the above-mentioned loud sound condition occurs.