JP3246462B2 - Function synthesizing method using C language circuit model and recording medium storing the program - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a function synthesizing method for converting a program described in a general-purpose program language (for example, C language) into an electronic circuit having an operation indicated by the program, and a recording medium on which the program is recorded. About.

[0002]

2. Description of the Related Art As a method of designing the function of a logic circuit,
Express the desired function not as a circuit image but as a processing flow (flowchart), and express this flowchart using a general-purpose programming language, for example, C language, and describe it in the same way as describing a C language source program. Has been done. Then, this source program (hereinafter referred to as “C language model”) is converted into an executable object by a C compiler and executed, and when the result matches the initially intended result, It is determined that there is no bug in the functional design, and the C language model is converted to an RTL circuit using a function synthesizing tool. Note that it is practically impossible to write a non-hierarchical flowchart when the entire circuit scale is large. Therefore, a group of processes is defined by one subroutine (function), and the entire circuit is described using this function. That is being done. Therefore, the C language model is generally composed of a plurality of functions. In addition, the C language model may be stored in one file, or may be stored separately for a plurality of files. Further, in the conventional method, the function synthesized C
The TOP RTL model used to configure a language model (RTL model) into one circuit has been manually created by referring to variables used in each C language model.

[0003]

The above-described flowchart represents the flow of processing in a sequential manner, and a C language model describing the flow can be described only by sequential processing. Therefore, when an existing function synthesis tool is applied to a C language model, the corresponding hardware also performs RTL that moves sequentially.
It becomes a circuit. However, as an actual circuit,
There are processes that can be performed in parallel instead of sequentially. In such a case, there is a problem that the operation speed is reduced.

On the other hand, an example of an apparatus for solving the above-mentioned problem is described in Japanese Patent Application Laid-Open No. H10-149382. In this device, a function that performs parallel operation in a circuit described in a general-purpose program language is specified, and a program for causing the specified function to operate in parallel is additionally generated.

However, in this apparatus, when “specifying a function that performs parallel operation”, all combinations of functions in a program must be simulated (whether or not parallel operation is possible). Therefore, there is a problem that a huge amount of processing is required, and as a result, it takes a long time to synthesize the functions.

The present invention has been made under such a background, and a program described in a general-purpose program language is processed by simple processing while considering the parallel operation of circuits indicated by the program (ie, It is an object of the present invention to provide a function synthesizing method that can be converted into an electronic circuit (in a short time) and a recording medium that records the program.

[0007]

According to the first aspect of the present invention,
In a function synthesizing method for converting a C language model in which a processing flow of a logic circuit is described using a C programming language into an RTL circuit model, a first step of selecting one function in the C language model; A second step of dividing a set of statements which can operate in parallel from each other as one group from among a plurality of program statements constituting the function selected in the step, and the second step A third step of converting each divided group into an RTL circuit model using a function synthesizing tool.

According to a second aspect of the present invention, in the function synthesizing method according to the first aspect, the group divided by the second step is a set of remaining sentences excluding sentences that cannot operate in parallel with each other. Features.

According to a third aspect of the present invention, in the function synthesizing method according to any one of the first and second aspects, the second step selects sentences which cannot be operated in parallel with each other and remains without being selected. If there is a sentence, group them, and until all sentences have been grouped,
The method is characterized by repeating the selection and grouping.

According to a fourth aspect of the present invention, there is provided the function synthesizing method according to any one of the first to third aspects, wherein the C
When there are a plurality of functions in the language model, the functions are first combined into one, and the combined functions are subjected to the processing of the first step and thereafter.

According to a fifth aspect of the present invention, in the function synthesizing method according to any one of the first to fourth aspects, in each C language model, a variable on a right side of an assignment statement is an input, and a left side of the assignment statement is an input. Is an output, a variable used in the comparison of if statements is an input, a list of these inputs and outputs, and a TO that connects the inputs and outputs.
After the P RTL model is generated and converted by the function synthesizing tool, the RTL circuit model is configured into one circuit in accordance with the connection relation described in the TOP RTL model.

According to a sixth aspect of the present invention, in the function synthesizing method according to any one of the first to fifth aspects, the fourth step comprises the step of selecting the maximum number of cycles among the number of cycles of each RTL circuit model. Is determined, and it is determined whether a sharable circuit element exists between a plurality of RTL circuit models. If there is a sharable circuit element, the circuit elements determined to be sharable operate simultaneously. Judge whether or not
When the circuit elements determined to be sharable operate simultaneously, it is determined whether or not the sum of the number of cycles of the RTL circuit model having the circuit element determined to be sharable is smaller than the maximum number of cycles. If the sum of the numbers is smaller than the maximum number of cycles, the RTL circuit models having the circuit elements determined to be sharable are combined into one group, and the combined group is subjected to function synthesis again. It is characterized by.

A seventh aspect of the present invention is characterized in that a program for causing a computer to execute the first aspect of the present invention is recorded. An eighth aspect of the invention is characterized in that a program for causing a computer to execute the second aspect of the invention is recorded. A ninth aspect of the present invention is characterized in that a program for causing a computer to execute the third aspect of the present invention is recorded. Claim 1
The invention according to claim 0 is characterized in that a program for causing a computer to execute the invention according to claim 4 is recorded. The invention according to claim 11 provides the computer with claim 5
A program for executing the described invention is recorded. A twelfth aspect of the invention is characterized in that a program for causing a computer to execute the sixth aspect of the invention is recorded.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS §1. 1. Outline of Embodiment FIG. 1 is an explanatory diagram illustrating an example of an outline of an embodiment of the present invention. In this figure, the above-mentioned C language model is stored in the input C model. When the scale of the entire circuit is large, the entire circuit is described by dividing it into a plurality of parts, and each is stored in a separate file. Therefore, a plurality of input C model files may exist. The parameta file is an optional description for manually dividing from outside when a place to be divided in one function is known in advance. For example, it is a control file that instructs “from what line to what line of the function A.” The “re-partitioning” process of FIG. 1 divides a part that can be processed in parallel with each other into one group with respect to the input C language model description based on the description described later.
The C language model divided for each group is output. Also,
After converting each of the divided output C language models into an RTL model, the TOP RTL model indicates how to connect these obtained RTL circuit elements and configure the entire circuit. is there. This TOP
The RTL model is automatically generated at the time of the above subdivision.

The specific method of automatically generating the TOP RTL model is as follows. When one function is extracted from the C language model and the function is divided, a variable on the right side of the assignment statement becomes an input and a variable on the left side becomes an output. Also, variables used in comparison of if statements are input. The input and the output are listed, and an RTL model that connects the input and the output is generated. For example, consider the case where the following program is divided into two modules. a = b; module (1) if (a == c) ｛module (2) x = 1; {else} x = 0;｝ In this case, the input of module (1) is b, The output is a. Further, the input of the module (2) becomes a and c, and the output becomes x. Then, the output a of the module (1) and the input a of the module (2) are connected. The inputs b and c and the output x are provided from outside the modules (1) and (2), and thus become external terminals (see FIG. 2).

§2. First Embodiment Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a flowchart illustrating an example of the function synthesizing method according to the first embodiment. The function synthesizing method according to the present embodiment is, for example, a CPU (Central Processing Unit).
And its peripheral circuits. The computer device executes the following function synthesizing method using a control program stored in a predetermined recording medium such as a ROM (Read Only Memory) or a hard disk device.

Here, first, when the operator specifies a program including a plurality of functions described in the general-purpose program language using an input device connected to the computer device, the processing of the CPU is performed as shown in FIG. The process proceeds to Step S1 of Step 3. In the present embodiment, the general-purpose program language is assumed to be a C language, for example. In step S1, one function is extracted from the designated program, and the process proceeds to step S2.

In step S2, it is determined whether or not there is a variable used in a plurality of sentences in the function extracted in step S1 (hereinafter, referred to as "processing target function").
If the result of this determination is “YES”, that is, if there is a variable used in a plurality of sentences, the process proceeds to step S3.

In step S3, the for statement, while statement, and case statement in the function to be processed are converted into an assignment statement or if statement equivalent to these statements, and the flow advances to step S4. By the processing in step S3, the processing target function is a notation using only the assignment statement and the if statement. Here, the “conversion into an assignment statement or an if statement” is performed as follows.

(1) In the case of a for statement or a while statement A statement in the parentheses of a for statement or a while statement (hereinafter referred to as an “executable statement”) is defined by a conditional expression (of the for statement or the while statement). Convert to a statement to be executed the number of times. That is, for example, In the case of the sentence a, a = a + 1; a = a + 1; a = a + 1;

(2) In the case of a case sentence Convert to an if sentence corresponding to each conditional expression. That is, for example, Statement, Into multiple sentences.

In step S4, the function to be processed after the conversion is divided into sentences, and the flow advances to step S5. Step S
In step 5, the first sentence (hereinafter, referred to as “head sentence”) is extracted from the division result in step S4, and
Proceed to 6. In step S6, the first sentence is compared with the remaining sentences (that is, other than the first sentence) (hereinafter, one sentence to be compared with the first sentence is referred to as a "comparison sentence"), and the remaining sentences are compared. Are excluded from the statements that cannot operate in parallel with the first sentence, and the process proceeds to step S7. Here, the “sentence that cannot be operated in parallel” is determined based on the following criteria.

(1) When the first sentence is an assignment statement Regardless of the type of statement (assignment statement or if statement), statements using the same variable cannot be operated in parallel. (2) When the first sentence is an if statement Regardless of the type of statement (assignment statement or if statement), statements using the same variable are not allowed to operate in parallel. if statement and the same variable is used only in both conditional expressions).

Next, in step S7, the head sentence and the sentences not excluded in step S6 are combined into one group (hereinafter, referred to as "grouping").
Proceed to 8. In step S8, it is determined whether there is any ungrouped sentence. If the result of this determination is "YES", that is, if there are ungrouped sentences, the process returns to step S5. In this case, steps S5 to S
Operation 7 is performed again. That is, in step S5, the first sentence (head sentence) is extracted from the ungrouped sentences, and in step S6, the head sentence is compared with the remaining (ungrouped) sentences. From the remaining sentences, sentences that cannot be operated in parallel with the head sentence are excluded. In step S7, the head sentence and the sentences not excluded in step S6 are grouped into one group, and the process proceeds to step S8.

On the other hand, the judgment result of step S8 is "NO"
, That is, if all statements are grouped,
Proceed to step S9. Also, if the determination result of step S2 is "NO", that is, if there is no variable used in a plurality of statements in the processing target function, step S9
Proceed to.

In step S9, it is determined whether or not the processing in steps S1 to S8 has been performed for all functions in the processing target program. If the result of this determination is “NO”, that is, if there is a function that has not yet been processed,
It returns to step S1. On the other hand, if the result of the determination in step S9 is "YES", that is, if the processing has been performed for all functions, the process proceeds to step S10.

In step S10, each group generated in step S7 is subjected to function synthesis to form a block (hereinafter, referred to as RTL level) indicating a sentence in each group.
“RTL block” is generated, and step S1
Proceed to 1. In step S11, the RTL block generated in step S10 is scheduled, and all processing ends.

FIG. 4 is a flowchart showing an example of the scheduling performed in step S11. In this figure, in step S101, the number of cycles of each RTL block generated in step S10 is checked, and the maximum number of cycles is obtained from the number, and the process proceeds to step S102.

In step S102, each RTL block generated in step S10 is compared, and it is determined whether a sharable circuit element (adder, comparator, memory, etc.) exists between a plurality of RTL blocks. . A sharable circuit element is a circuit element that has the same input signal item, performs the same processing on a signal input inside the circuit element, and returns a value. For example, a comparator, an adder, a multiplier or the like having the same number of input / output bits. If the result of this determination is “NO”, that is, if there is no sharable circuit element between the plurality of RTL blocks, the scheduling ends as it is. On the other hand, if the determination result of step S102 is “Y
ES ", that is, when the sharable circuit element is a plurality of RTs.
If it exists between the L blocks, the process proceeds to step S103.

In step S103, step S102
It is determined whether the circuit elements determined to be sharable at the same time are operating at the same time. Shareable circuit elements (for example, the same bi
t), a plurality of Rs generated by functional synthesis
Exist in the TL model and their RTL mode
l operate in the same cycle, their RTL m
Since the sharable circuit elements included in the “odel” need to be operated at the same time, they are required for each existing circuit.
If the result of this determination is “NO”, that is, if the circuit elements determined to be sharable are not operating at the same time, there is no need for scheduling, and the process ends. On the other hand, the determination result of step S103 is “YES”
In other words, if the circuit elements determined to be sharable operate at the same time, it is necessary to perform scheduling so that these circuit elements do not temporally collide, and the process proceeds to step S104.

In step S104, step S102
It is determined whether or not the sum of the number of cycles of the RTL block having the circuit element determined to be sharable is smaller than the maximum number of cycles (determined in step S101).
If this determination result is “NO”, that is, if the sum of the number of cycles of the RTL block having the circuit element determined to be sharable is larger than the maximum number of cycles, the maximum number of cycles becomes large as a result of scheduling. Therefore, the scheduling ends. On the other hand, if the determination result in step S104 is “YES”, that is,
If the sum of the cycle numbers is smaller than the maximum cycle number, the process proceeds to step S105.

In step S105, step S102
In the RTL block having the circuit element determined to be sharable in (1), the (original) group functionally combined with the RTL block is combined into one group, and the combined group is combined with the function again and the scheduling is performed. finish.

Next, the function synthesizing method according to the first embodiment of the present invention will be described with a specific example. In step S1 of FIG. 3, it is assumed that the following function func1 is extracted. Here, each variable is a global variable.

In step S2, since the variables a, x1, and x2 are used in a plurality of sentences in the function func1, the process proceeds to step S3.

In step S3, the for statement in the function func1 is equivalently converted into an assignment statement, and the flow advances to step S4. As a result, the function func1 becomes a function func1 ′ shown below.

In step S4, the function func1 '
Is divided into the following sentences, and the process proceeds to step S5. Here, for simplicity, the if sentence is represented by one line without line breaks. a = a + 1;.. a = a + 1;... if (a == b) ｛x1 = b;｝ else ｛x1 = 0;｝... if (a == d) ｛x2 = d; {else} x2 = 0;｝ ... c = x1 &&x2;

In step S5, the first sentence is taken out of the above-mentioned sentences (1) to (6), and the flow advances to step S6. In step S6, the above sentence is compared with the remaining sentences ~.
A sentence that cannot operate in parallel with the sentence is excluded from the remaining sentences. Here, the statement is a comparison between the assignment statement and the assignment statement, and the statement cannot operate in parallel with the statement because the same variable (a) is used in both.
For the same reason, a sentence cannot operate in parallel with a sentence. The sentence is a comparison between the assignment sentence and the if sentence, and
Since the same variable (a) is used in both, the sentence cannot operate in parallel with the sentence. For the same reason, a sentence cannot operate in parallel with a sentence. On the other hand, a statement is a comparison between an assignment statement and an assignment statement, and the same variable is not used in both, so that the statement can operate in parallel with the statement. As described above, in this example, the sentence 〜 is excluded as a sentence that cannot operate in parallel with the sentence. Next, step S7
Proceed to.

In step S7, one sentence (sentence) extracted in step S5 and a sentence (sentence) not excluded in step S6 are grouped, and the flow advances to step S8. In step S8, since the sentences are not grouped, the process returns to step S5.

In step S5, the first sentence is extracted from the ungrouped sentences (sentences), and the process proceeds to step S6. In step S6, the above sentence and the remaining sentences are compared, and a sentence that cannot operate in parallel with the sentence is excluded from the remaining sentences. Here, the statement is a comparison between the assignment statement and the assignment statement, and the statement cannot operate in parallel with the statement because the same variable (a) is used in both. In addition, a sentence is a comparison between an assignment sentence and an if sentence, and since the same variable (a) is used in both, the sentence cannot operate in parallel with the sentence. For the same reason, a sentence cannot operate in parallel with a sentence.
As described above, in this example, all the remaining sentences ~
It is excluded as a statement that cannot operate in parallel with the statement. Next, the process proceeds to step S7.

In step S7, since all of the remaining sentences (1) to (4) cannot operate in parallel with the sentences, one sentence (sentence) extracted in step S5 is grouped into a single sentence, and the process proceeds to step S8. In step S8, since the sentences are not grouped, the process returns to step S5.

In step S5, the first sentence is extracted from the ungrouped sentences (sentences), and the process proceeds to step S6. In step S6, the sentence is compared with the remaining sentences, and a sentence that cannot operate in parallel with the sentence is excluded from the remaining sentences. Here, the sentence is a comparison between the assignment sentence and the if sentence, and since the same variable (a) is used in both, the sentence cannot operate in parallel with the sentence. For the same reason, a sentence cannot operate in parallel with a sentence. As described above, in this example, all the remaining sentences are excluded as sentences that cannot operate in parallel with the sentences. Next, the process proceeds to step S7.

In step S7, all of the remaining sentences cannot operate in parallel with the sentences.
The one sentence (sentence) extracted by is grouped by a single sentence, and the process proceeds to step S8. In step S8, since the sentences are not grouped, the process returns to step S5.

In step S5, the first sentence is extracted from the ungrouped sentences (sentence,), and the flow advances to step S6. In step S6, the above sentence is compared with the remaining sentences. Here, a sentence and a sentence are a comparison between an if sentence and an if sentence, and since the same variable (a) is used only in a conditional expression in both cases, the sentence can operate in parallel with the sentence. Next, the process proceeds to step S7.

In step S7, one sentence (sentence) extracted in step S5 and a sentence (sentence) not excluded in step S6 are grouped, and the flow advances to step S8. In step S8, all the sentences have been grouped, so the process proceeds to step S9. As described above, steps S5 to S8
By repeating the above processing, the above sentence
Divided into two groups. Sentence …… Group A sentence …… Group B sentence …… Group C sentence …… Group D

In step S9, it is determined whether or not the processing in steps S1 to S8 has been performed for all the functions in the program.
If there is unc2), the process returns to step S1, and the same processing (steps S1 to S8) is performed on the function. When the processes in steps S1 to S8 are performed for all the functions, the process proceeds to step S10.

In step S10, RTL blocks as shown in FIG. 5 are generated by synthesizing the functions of the groups generated in step S7, and the flow advances to step S11. In step S11, the blocks generated in step S10 are scheduled so that the required number of circuit elements is minimized. That is, step S10 in FIG.
1 and the process proceeds to step S101.
The number of cycles of each RTL block generated in step 10 is checked, and the maximum number of cycles is obtained from the number. In the example of FIG. 5, each of the groups A to C has one cycle and the group D has four cycles, so the maximum cycle is four cycles.

Next, in step S102, step S
The RTL blocks generated in step 10 are compared to determine whether a sharable circuit element exists between the plurality of RTL blocks. In the example of FIG. 5, it is determined that the groups A to C have sharable circuit elements (“+1” adders),
Proceed to step S103.

Next, in Step S103, Step S
It is determined whether the circuit elements determined to be sharable in 102 are operating simultaneously. In the example of FIG.
It is determined that the C circuit elements (“+1” adders) are operating at the same time, and the process proceeds to step S104.

In step S104, step S102
It is determined whether or not the sum of the number of cycles of the RTL block having the circuit element determined to be sharable is smaller than the maximum number of cycles (determined in step S101).
In the example of FIG. 5, since the sum of the cycles of the groups A to C (3 cycles) is smaller than the maximum cycle (4 cycles), the process proceeds to step S105.

In step S105, step S102
For the RTL block having the circuit element determined to be sharable in (1), the (original) group functionally combined with the RTL block is combined into one group, and the combined group is combined with the function again. In the example of FIG. 5, it is determined that the “+1” adders of the groups A to C can be shared, and as a result, the groups A to C are functionally combined into one RTL block as shown in FIG.

As described above, in the first embodiment, the processing flow (function) described hierarchically at the time of design, that is,
Subdivision is performed for each function of the hierarchical function module. Note that, in the above method, after all functions are functionally synthesized into an RTL block, the above-described TOP RTL model is used.
All RTL blocks are configured into one circuit according to the connection relation of the circuit elements of the RTL block described in (1).
Here, a method of configuring a circuit based on the TOP RTL model is the same as the conventional method.

§3. Second Embodiment Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a flowchart illustrating an example of the function synthesizing method according to the second embodiment. The flowchart shown in FIG. 7 is different from the flowchart shown in FIG.
1 and S9 are deleted, and step S0 is added instead.

Here, in step S0, a plurality of functions in the program are combined into one function. More specifically, all the sentences in each function are extracted from each function and collected into a function having a predetermined name. That is, in the first embodiment, statements (in each function) are grouped for each function in the program, whereas in the second embodiment, each function in the program is regarded as one function. , (In the function that is grouped together). The operation of the remaining steps (steps S2 to S8, S10, S11) in FIG. 4 is the same as the operation of the step shown in FIG.
Here, the description is omitted.

Next, the function synthesizing method according to the second embodiment of the present invention will be described with a specific example. The C language model to be processed in the present embodiment includes functions f1 and f2 described below, and is assumed to be called from other functions in the order of function f1 → function f2 when executing a program. Here, each variable is a global variable.

First, in step S0, a plurality of functions in the program are combined into one function. Thus, the functions f1 and f2 are combined into the following function f0.

Next, in step S2, in the function f0, since the variables a, b, c, y, and z are used in a plurality of sentences, the process proceeds to step S3. In step S3,
In the above function f0, for statement, while statement, cas
Since there is no e-statement, the process directly proceeds to step S4.

In step S4, the function f0 is divided into the following statements (1) and (2), and the flow advances to step S5. In addition,
Here, for simplicity, if sentences are described in one line without line breaks. a = a + 1;... if (a == b) ｛x = y;｝ else ｛x = 0;｝ if (a == c) ｛z = 1;｝ else ｛z = 0;｝ if (b == s) ＝ a = 0; b = z; if (c == x) ｛y = z;｝ else ｛y = 1;｝ ｃ c = c + 1; if (C == d) ｛y = 0;｝ else ｛y = e;｝ b = b + y;

In step S5, the first sentence is extracted from the above sentences 1 to 6, and the flow advances to step S6. In step S6, the above-mentioned “criterion for a statement that cannot be operated in parallel”
Is compared with the remaining sentences based on, and a sentence that cannot operate in parallel with the sentence is excluded from the remaining sentences. As a result, in this example,,,... Are excluded as statements that cannot operate in parallel with the statement. Next, the process proceeds to step S7.

In step S7, one sentence (sentence) extracted in step S5 and a sentence (sentence) not excluded in step S6 are grouped, and the flow advances to step S8. In step S8, since the statements,... Are not grouped, the process returns to step S5.

In step S5, the first sentence is extracted from the ungrouped sentences (sentences,,...), And the flow advances to step S6. In step S6, the sentence and the remaining sentences,... Are compared based on the above-mentioned “criterion of sentences that cannot operate in parallel”, and the remaining sentences,
, To exclude sentences that cannot operate in parallel with the sentence. As a result, in this example,,, are excluded as sentences that cannot operate in parallel with the sentence. Next, step S7
Proceed to.

In step S7, one sentence (sentence) extracted in step S5 and a sentence (sentence) not excluded in step S6 are grouped, and the flow advances to step S8. In step S8, since the sentences and are not grouped, the process returns to step S5.

In step S5, the first sentence is extracted from the ungrouped sentences (sentence ,,), and the flow advances to step S6. In step S6, the sentence and the remaining sentences are compared based on the above-mentioned "criterion of sentences that cannot be operated in parallel", and it is determined that the remaining sentences can be operated in parallel with the sentence. Next, the process proceeds to step S7.

In step S7, one sentence (sentence) extracted in step S5 and a sentence (sentence) not excluded in step S6 are grouped, and the flow advances to step S8. In step S8, since all the sentences have been grouped, the process proceeds to step S10. As described above, step S
By repeating the processing of 5 to S8, the above sentence
It is divided into the following three groups. Sentence, ... group E sentence, ... group F sentence, ... group G

In step S10, RTL blocks as shown in FIG. 8 are generated by synthesizing the functions of the groups generated in step S7, and the flow advances to step S11. In step S11, the same scheduling as in the first embodiment is performed on the blocks generated in step S10 so that the required number of circuit elements is minimized, and all the processing ends.

As described above, in the second embodiment, the C language model of the whole circuit described hierarchically is temporarily converted to the C language model of the whole circuit developed in a solid (non-hierarchical) manner. Subdivide. In the second embodiment, since the entire circuit is re-divided, the degree of parallelism is higher than in the first embodiment, and a common circuit element is found in the entire circuit, so that the physical circuit area is also reduced.

§4. Supplement Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to the embodiment, and there may be a design change or the like without departing from the gist of the present invention. Even this is included in the present invention. For example, in the above-described embodiment, the general-purpose program language is C language. However, the program language to which the present invention is applied is not limited to C language, and other program languages (Pascal, BAS) may be used.
IC etc.). In the above-described embodiment, in the division in step S4, the function is divided in units of a sentence. However, the division unit is not limited to one sentence, and may be divided in arbitrary units such as every two sentences or every three sentences. No problem.

[0067]

As described above, according to the present invention, sentences that cannot be operated in parallel are sorted out before synthesizing functions.
It is no longer necessary to simulate all combinations of functions in the program (whether or not parallel operation is possible),
As a result, a program described in a general-purpose programming language can be converted into an electronic circuit by simple processing (that is, in a short time) while considering the parallel operation of the circuit indicated by the program.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an example of an outline of an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of connection between modules.

FIG. 3 is a flowchart illustrating an example of a function synthesizing method according to the first embodiment of the present invention.

FIG. 4 is a flowchart illustrating an example of scheduling performed in step S11 of FIG. 3;

FIG. 5 is an explanatory diagram illustrating an example of an RTL block generated according to the first embodiment.

FIG. 6 is an explanatory diagram showing an example of an RTL block after scheduling.

FIG. 7 is a flowchart illustrating an example of a function synthesizing method according to a second embodiment of the present invention.

FIG. 8 is an explanatory diagram illustrating an example of an RTL block generated according to the second embodiment.

Claims (12)

(57) [Claims] 1. A function synthesizing method for converting a C language model in which a processing flow of a logic circuit is described using a C programming language into an RTL circuit model, a first step of selecting one function in the C language model And dividing a set of statements that can operate in parallel from each other into one group from among a plurality of program statements constituting the function selected in the first step.
And a third step of converting an RTL circuit model into a RTL circuit model using a function synthesis tool for each of the groups divided by the second step, and a fourth step of scheduling the RTL circuit model. Function synthesis method. 2. The function synthesizing method according to claim 1, wherein the group divided in the second step is a set of remaining sentences excluding sentences that cannot operate in parallel with each other. . 3. The function synthesizing method according to claim 1, wherein in the second step, sentences which cannot be operated in parallel with each other are selected. A grouping of the sentences, and repeating the selection and the grouping until the grouping of all the sentences is completed. 4. The function synthesizing method according to claim 1, wherein when there are a plurality of functions in the C language model, first,
A function synthesizing method, wherein the functions are combined into one, and the processing after the first step is performed on the combined functions. 5. The function synthesizing method according to claim 1, wherein in each C language model, a variable on the right side of the assignment statement is an input, and a variable on the left side of the assignment statement is an output. , If statements are inputs, a list of these inputs and outputs is generated, and a TOP RTL model that connects the inputs and outputs is generated. After conversion by the function synthesis tool, the TOP RTL mo
A function synthesizing method, wherein an RTL circuit model is configured into one circuit in accordance with a connection relation described in "del". 6. The function synthesizing method according to claim 1, wherein in the fourth step, a maximum number of cycles is obtained from among the number of cycles of each RTL circuit model, and the function is sharable. It is determined whether the circuit element exists between a plurality of RTL circuit models. If there is a sharable circuit element, it is determined whether the circuit elements determined to be sharable are operating simultaneously. When the circuit elements determined to be sharable operate simultaneously, it is determined whether or not the sum of the number of cycles of the RTL circuit model having the circuit element determined to be sharable is smaller than the maximum number of cycles; If the sum of the cycle numbers is smaller than the maximum cycle number, the RTL having the circuit element determined to be sharable
A function synthesizing method, comprising: combining circuit models into one group; and synthesizing the combined group again. 7. A computer is provided with a C language model that describes the processing flow of a logic circuit using a C programming language.
A recording medium storing a program for executing a conversion to a TL circuit model, a first step of selecting one function in the C language model, and a function selected in the first step For a plurality of program statements, a set of statements that can operate in parallel from each other is divided into one group.
And a third step of performing a step of converting into an RTL circuit model using a function synthesizing tool for each of the groups divided by the second step. 8. The recording medium according to claim 7, wherein the group divided in the second step is a set of remaining sentences excluding sentences that cannot operate in parallel with each other. 9. The recording medium according to claim 7, wherein in the second step, sentences that cannot be operated in parallel with each other are selected, and if there is a sentence that has not been selected, A recording medium comprising the steps of grouping the sentences and repeating the selection and grouping until the grouping of all the sentences is completed. 10. The recording medium according to claim 7, wherein when there are a plurality of functions in the C language model, first,
A recording medium characterized by combining those functions into one and performing the processing after the first step on the combined functions. 11. The recording medium according to claim 7, wherein in each C language model, a variable on the right side of the assignment statement is an input, and a variable on the left side of the assignment statement is an output, The variables used in the comparison of the if statement are inputs, the input and the output are listed, a TOP RTL model that connects the input and the output is generated, and the TOP RTL model is converted by the function synthesizing tool.
A recording medium comprising an RTL circuit model formed into one circuit in accordance with a connection relationship described in "del". 12. The recording medium according to claim 7, wherein in the fourth step, a maximum cycle number is obtained from a cycle number of each RTL circuit model, and the sharable circuit is obtained. Determining whether the element exists between a plurality of RTL circuit models; if there is a sharable circuit element, determining whether the circuit elements determined to be sharable are operating simultaneously; When the circuit elements determined to be sharable operate simultaneously, it is determined whether or not the sum of the number of cycles of the RTL circuit model having the circuit element determined to be sharable is smaller than the maximum number of cycles; If the sum of the numbers is smaller than the maximum number of cycles, the RTL having the circuit element determined to be sharable is used.
A recording medium comprising combining circuit models into one group, and synthesizing the combined group again.