JP3247592B2 - Method for manufacturing compound semiconductor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor substrate on which a compound semiconductor device such as a semiconductor light emitting device is formed, and more particularly to an improvement in a sapphire substrate capable of improving a yield in a manufacturing process.

[0002]

2. Description of the Related Art Conventionally, sapphire is well known as a substrate used for a blue light emitting device, particularly, a gallium nitride compound semiconductor. Sapphire substrate is 330μ thick
m is used. The reason why such a thickness is required is that, when the sapphire substrate is thin, the substrate is broken by the temperature rise and the temperature decrease when the crystal is grown on the substrate. On this substrate, the general formula In _X Al
_{Y Ga 1-XY N (0} ≦ X <1,0 ≦ Y <1) is laminated gallium nitride-based compound semiconductor represented by. As a method of cutting chips for a light emitting element from a wafer on which the semiconductor material is laminated, a dicing method is used in which a street of the wafer is cut or a kerf is cut by an ultra-thin outer peripheral blade attached to a tip of a spindle rotating at a high speed. saw)
In order to divide the wafer into individual dies, it is common to use scribing or the like for making a scratch using a diamond cutter or the like by using cleavage.

[0003]

However, the wafer on which the gallium nitride-based compound semiconductor is laminated is a very hard material having a Mohs hardness of about 9 for both the sapphire substrate and the gallium nitride-based compound semiconductor. Also, due to the nature of the sapphire crystal of hexagonal system, since it does not have cleavage properties, when a wafer using a substrate having a conventional thickness (80 to 330 μm) is cut, cracks and chipping (irregular shaped) (Breakage) is likely to occur, making it impossible to cut neatly, resulting in frequent chip (die) defects.

As a result, the performance of the semiconductor element itself is not sufficiently exhibited, and for example, the efficiency of the light emitting element is reduced. The number of chips that cannot be used increases, and the product yield decreases. In particular, when an expensive sapphire substrate is used, the yield greatly affects the product price.

Accordingly, it is an object of the present invention to reduce cracks and chipping generated on a cut surface when cutting a wafer.

It is another object of the present invention to improve the efficiency of a light emitting device by separating chips neatly.

Another object of the present invention is to improve the yield of a semiconductor device using a sapphire substrate.

[0008]

In order to achieve the above object, a method for producing a compound semiconductor according to the present invention has a thickness of 20 μm.
Raising the temperature of a sapphire substrate having a thickness of about 60 μm at a rate of 40 ° C. to 60 ° C./min, forming a compound semiconductor device by growing a crystal on the sapphire substrate by a CVD method, and forming the sapphire substrate after growing the crystal. 20 ° C ~ 3
Lowering the temperature at 0 ° C./min.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, a compound semiconductor material such as a gallium nitride-based compound is laminated on a sapphire substrate (20 μm ≦ thickness t ≦ 60 μm) manufactured in advance. In this laminating process, in order to prevent the thin sapphire substrate from cracking in the (MO) CVD process performed in a high temperature environment,
The transition to the lamination process by the (MO) CVD method and the exit from the lamination process are performed under a gentle temperature change. That is,
When the thickness of the sapphire substrate is 20 μm to 60 μm, the temperature is raised at a rate of 40 to 60 ° C./min or less, and the temperature is lowered by further considering that element films having different thermal expansion coefficients and the like are laminated on the substrate. By performing the cooling at a rate of 20 to 30 ° C./min or less, it is possible to prevent the substrate from being cracked even if it is thin. When the substrate is made this thin, it can be neatly separated into chips when the wafer is cut, and the efficiency of the light emitting element is improved and the yield is improved.

An embodiment of the present invention will be described below with reference to the drawings. First, the relationship between the thickness of the sapphire substrate and the yield of chip processing was examined. FIG. 1 shows a graph of chip yield when dicing a substrate on which a compound semiconductor device is formed. In the figure, the horizontal axis indicates the thickness of the sapphire substrate (a wafer having a diameter of 2 inches) during crystal growth, and the vertical axis indicates the yield (due to cracking and tapping). The blade conditions for the sapphire substrate are diamond blade for blade type, blade thickness of 50 μm, and cut speed of 2 mm / sec. The same graph is obtained when the cutting speed is set to 5 mm / sec.

From FIG. 1, the thickness t of the wafer is set to 20 μm ≦
It can be seen that the sample of the example in which the compound semiconductor device was formed with t ≦ 60 μm had a yield of 95% or more. The yield decreases as the thickness of the wafer is increased under the same manufacturing conditions, and 89% of the conventional products use a 330 μm substrate. That is, the thickness of the wafer is 20 μm
By setting the thickness to μ60 μm, the yield is improved by 5% or more. Conversely, the wafer thickness is 10 μm under the same manufacturing conditions.
Then, before scribing, the wafer itself breaks due to the warpage of the wafer, and the yield is greatly reduced.

However, thin wafers having a thickness of 20 μm to 60 μm are not conventionally used because they are broken by heating and cooling the substrate in a CVD (crystal growth) process.

Therefore, the relationship between the thickness of the substrate and the crack in the conventional process was examined. FIG. 2A illustrates an example of a temperature profile in a conventional process of forming (crystal growing) a light emitting element on a sapphire substrate 9 (thickness: 330 μm). A temperature increasing process a is performed in which the temperature of the substrate atmosphere is increased from room temperature to 1150 ° C. at a rate of 150 ° C./min, and a thermal cleaning process b is performed at 1150 ° C. for a predetermined time. Next, a step c of lowering the ambient temperature to 550 ° C. is performed, and a step d of growing a GaN buffer layer on the substrate is performed. Atmospheric temperature is 11
Through a process e of raising the temperature to 50 ° C., a process f of sequentially forming an N-type GaN layer and a P-type GaN layer on the GaN buffer layer of the substrate is performed. A process g is performed in which the ambient temperature is reduced from 1150 ° C. and the heat is released to room temperature at a temperature decreasing speed of 50 ° C./min.

The heating speed is set by controlling the output of the heating device, and the cooling speed is set by changing the supply amount of the atmospheric gas to the CVD device. Atmosphere gas is
As in the case of ordinary crystal growth, hydrogen is used for raising the temperature, ammonia + hydrogen + nitrogen is used for lowering the temperature, and the internal pressure of the chamber of the CVD apparatus is set to normal pressure.

FIGS. 3 (a) to 3 (d) show the same conditions for the steps b to f, and for the substrates of various thicknesses, the heating time, the cooling time, 3 shows the results of examining the occurrence of cracks in the sapphire substrate when various values were set.

FIG. 3A shows a sapphire substrate having a thickness of 20 mm.
When the temperature rise time from normal temperature to 1150 ° C. is 30 minutes or more, and the temperature fall time from 1150 ° C. to normal temperature is 30 minutes or more, no cracking of the substrate occurs. The heating rate in this case is about 40 ° C./min (1
150 ° C./30 minutes), and the cooling rate is about 40 ° C./min (1
150 ° C./30 minutes). It can be seen that when the thickness of the substrate is 20 μm, it takes about 30 minutes to raise and lower the temperature, and it is necessary to slowly shift to the target temperature.

FIG. 3B shows that the sapphire substrate has a thickness of 6 mm.
The graph shows the case of 0 μm. When the temperature rise time from normal temperature to 1150 ° C. was 20 minutes or more and the temperature fall time from 1150 ° C. to normal temperature was 30 minutes or more, no cracking of the substrate occurred. In this case, the heating rate is about 60 ° C./min.
(1150 ° C / 20 minutes), the temperature drop rate is about 40 ° C / min
(1150 ° C./30 minutes).

FIG. 3C shows that the thickness of the sapphire substrate is 1
The case of 00 μm is shown. When the temperature rise time from normal temperature to 1150 ° C. is 10 minutes or more and the temperature fall time from 1150 ° C. to normal temperature is 30 minutes or more, no cracking of the substrate occurred. In this case, the heating rate is about 115 ° C./mi.
n (1150 ° C./10 minutes), the temperature drop rate is about 40 ° C./mi
n (1150 ° C./30 minutes).

FIG. 3 (d) shows a case where the thickness of the sapphire substrate is 330 μm, which is a conventional one, from normal temperature to 1150 μm.
When the temperature rise time to 5 ° C. was 5 minutes or more and the temperature fall time from 1150 ° C. to normal temperature was 20 minutes or more, no cracking of the substrate occurred. The heating rate in this case is about 230 ° C /
min (1150 ° C / 5 minutes), temperature drop rate is about 60 ° C / m
in (1150 ° C./20 minutes). It can be seen that the sapphire substrate is more resistant to temperature changes as the thickness of the substrate increases. According to FIGS. 3A and 3B, the thickness is 20 μm.
It can be seen that a thin sapphire substrate needs to have a temperature rise rate (temperature rise) of 40 ° C./min or less. 60 ° C / min for thin sapphire substrate of 60 μm
It turns out that it is necessary to make the following temperature rise rates. In addition, in the case of the substrates of 20 μm and 60 μm, it can be seen that the temperature reduction rate may be about 40 ° C./min or less when only the substrate is used (in a state where the elements are not stacked). However, actually, since the temperature is lowered after the element is formed on the sapphire substrate, it is empirically preferable to suppress the temperature lowering rate to about half of the temperature increasing rate in consideration of the fact that materials having different coefficients of thermal expansion and the like are laminated. . Therefore, in the case of a 20 μm substrate, the temperature reduction rate is set to 20 ° C./min or less when the elements are stacked. In the case of a 60 μm substrate, the temperature reduction rate is 30 ° C./min or less when the elements are stacked.

3 (a) to 3 (d), the measurement was performed with the cooling time being longer than the heating time, because the GaN or the like and the sapphire substrate had a thermal expansion coefficient and a lattice constant. It is considered that the temperature change after growing a crystal such as GaN on the substrate has a greater effect on the cracking of the substrate, and it is necessary to lower the temperature slowly. The reason is that the temperature drop takes a long time because the temperature is close to the radiation cooling.

Therefore, even for a thin sapphire substrate such as 20 μm to 60 μm, the temperature increasing speed in the first temperature increasing step a in the CVD process and the temperature decreasing rate in the temperature decreasing step g after the crystal growth are set to 40 to 40 μm depending on the thickness of the substrate. 60 ° C
If the heat treatment is performed at a temperature of 20 to 30 ° C./min or less, cracking of the substrate can be prevented.

As described above, the thickness of the sapphire substrate is set to 20.
2 μm to 60 μm, and as shown in FIG.
In the process D, the temperature rising speed in the first temperature rising process a is set to 40 to 60 ° C./min or less, and the temperature rising speed in the temperature falling process g for terminating the high temperature process is raised in consideration of the formation of the element layer on the substrate. 20 ~ 30 ℃ which is about 1/2 of the speed
By setting the temperature gradient to be gentler at not more than / min, it is possible to prevent cracking and clipping in wafer cutting and prevent cracking of the substrate in the CVD process.

An example of manufacturing a compound semiconductor device by the temperature profile crystal growth process will be described. FIG. 4 illustrates a structural example of a light emitting element as an example of a compound semiconductor device. In the figure, 1 is a sapphire substrate, 2 is a GaN (gallium nitride) buffer layer, 3 is N-type GaN
The layers 4, 4 are P-type GaN layers, 5 is an Au / Ni (gold / nickel) electrode, and 6 is a Ti / Al (titanium / aluminum) electrode.

FIGS. 5 to 11 show an example of a manufacturing process of the light emitting device shown in FIG. As described above, a sapphire wafer having a thickness selected within a range of 20 μm ≦ t ≦ 60 μm is used as a semiconductor substrate.

In the temperature profile shown in FIG.
A crystal is grown on the substrate by a CVD apparatus. First,
The temperature in the chamber of the MOCVD apparatus accommodating the sapphire substrate 1 was raised to 40 ° C./mi in a reducing hydrogen gas atmosphere.
n (when t is 20 μm) to 60 ° C./min (when t is 60 μm)
(at m), the temperature rises relatively slowly to 1150 ° C. (a in FIG. 2B), and the substrate is thermally cleaned for a predetermined time (b in FIG. 2). Next, the temperature in the chamber was lowered to 550 ° C. (FIG. C), and (0001)
An amorphous GaN layer 2 having a thickness of about 0.04 μm is formed on a sapphire substrate 1 having a crystal structure by MOCVD (FIG. 4D). The temperature is increased to 1150 ° C. (FIG. 3E), and an N-type GaN layer 3 to which an N-type impurity is added is formed to a thickness of about 4.0 μm by MOCVD. Further, a P-type GaN layer 4 to which a P-type impurity is added is sequentially formed to a thickness of about 1.0 μm (f in the figure). As a result, as shown in FIG. 5, a GaN buffer layer 2, an N-type GaN layer 3, a P-type GaN
The layers 4 are sequentially stacked by crystal growth.

Next, an SiO 2 (silicon oxide) film 7 is deposited to a thickness of 500 nm on the GaN layer 4 by a CVD method (FIG. 6). After that, the temperature in the chamber is lowered at a temperature reduction rate of 20 ° C. in an atmosphere of ammonia + hydrogen + nitrogen gas.
/ Min (t is 20 μm) to 30 ° C./min (t is 60 μm)
m), the temperature slowly decreases to room temperature (g in the figure), and the substrate is removed from the chamber. A photoresist is applied to the SiO2 film 7, pattern exposure and development are performed, and a resist mask 8 is formed.
Is formed (FIG. 7). SiO 2 using resist 8 as a mask
2 Etch the film 7 with an HF (hydrogen fluoride) solution,
An iO2 mask 7a is formed (FIG. 8).

Using the SiO 2 mask 7a as a mask, 180
P-type GaN layer 4 and N-type Ga by hot phosphoric acid
A part of the N layer 3 is etched to expose a part of the N-type GaN layer 3. The amount of etching can be controlled by the etching time (FIG. 9). The SiO2 mask 7a is selectively etched with an HF solution and removed (FIG. 10).

Next, on the P-type GaN layer 4, A
On the u / Ni layer 7 and the N-type GaN layer 3, Ti is used as an N electrode.
/ Al layer 8 is formed by vapor deposition (FIG. 11).

After the compound semiconductor device is formed on the sapphire substrate in this way, dicing is performed. That is,
Scratches (working grooves) are made by scribing from the sapphire substrate 1 side by a diamond cutter device, cracks are made along the scratches of the wafer by wafer breaking equipment, and the wafer is divided into dies.

The thickness t of the substrate is set to 20 μm ≦ t ≦ 60.
In order to set the thickness in the range of μm, the substrate can be thinned after forming an element using a substrate having a thickness that does not cause cracking in the MOCVD process, for example, a conventional substrate having a thickness of 80 to 330 μm. For example, after crystal growth on the substrate, the wafer is fixed to a jig with the back side of the wafer facing up, and polished from the back surface of the wafer to a thickness of the substrate in the above range using an abrasive such as boron carbide.

[0031]

As described above, according to the present invention, a sapphire substrate having a thickness of 20 .mu.m to 60 .mu.m is used in the production of a compound semiconductor, and the first temperature increase and the crystal growth in the crystal growth process (high temperature process) are performed. Since the temperature profile of the subsequent temperature decrease is performed at a specific gentle slope, it is possible to improve the yield at the time of dicing as compared with the conventional product while suppressing cracking of the wafer in the CVD process.

[Brief description of the drawings]

FIG. 1 is a graph showing the relationship between the thickness of a substrate and the yield of chip formation.

FIG. 2 is an explanatory diagram for explaining a difference in a temperature profile between the present invention and a conventional example.

FIG. 3 is an explanatory diagram for explaining the relationship between the thickness of the substrate and cracking of the substrate due to temperature rise and fall.

FIG. 4 is an explanatory diagram illustrating a structural example of a compound semiconductor device.

FIG. 5 is a first process chart showing a manufacturing process of the compound semiconductor device.

FIG. 6 is a second process chart showing a manufacturing process of the compound semiconductor device.

FIG. 7 is a third process chart showing a manufacturing process of the compound semiconductor device.

FIG. 8 is a fourth process chart showing the manufacturing process of the compound semiconductor device.

FIG. 9 is a fifth process chart showing the manufacturing process of the compound semiconductor device.

FIG. 10 is a sixth view showing the manufacturing process of the compound semiconductor device;
FIG.

FIG. 11 is a seventh diagram showing the manufacturing process of the compound semiconductor device;
FIG.

[Explanation of symbols]

 Reference Signs List 1 sapphire substrate 2 GaN buffer layer 3 N-type GaN layer 4 P-type GaN layer 5 Au / Ni electrode 6 Ti / Al electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/205 C30B 25/10 C30B 29/38 H01L 27/12 H01L 33/00

Claims (2)

(57) [Claims] A step of raising a temperature of a sapphire substrate having a thickness of 20 μm to 60 μm at a rate of 40 ° C. to 60 ° C./min; and a step of forming a compound semiconductor device by growing crystals on the sapphire substrate by a CVD method. After the crystal growth, the sapphire substrate is kept at 20 ° C. to 30 ° C.
A step of lowering the temperature at a rate of / min. 2. The method according to claim 1, wherein said CVD method is a MOCVD method.