JP3248403B2 - Digital convergence device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for correcting convergence of a color image receiver, and more particularly to a digital convergence apparatus capable of performing high-accuracy correction with reduced mutual interference between correction data between the inside and outside of an effective screen. It is.

[0002]

2. Description of the Related Art In general, in a projection type color image receiver for enlarging and projecting onto a screen using three projection tubes emitting three primary colors, the angle of incidence of the projection tube on the screen is different for each projection tube. Color shift occurs. The so-called convergence, in which these three primary colors are superimposed, is a method of creating a convergence correction waveform in an analog manner in synchronization with the horizontal and vertical scanning periods, changing the size and shape of the waveform, and adjusting the waveform. There is a problem in convergence accuracy. Therefore, as a method capable of coping with various signals and having high convergence accuracy, for example, a digital convergence device disclosed in Japanese Patent Application Laid-Open No. Sho 60-13028 has been proposed.

In FIG. 7, 1 is a phase comparator, and 2 is a LP.
F, 3 are VCOs, 5 is a 1 / M frequency divider, 6 is a digital correction data generation circuit, 9 is a video circuit, 10 is a D / A converter, 11 is an LPF, 12 is an output amplifier, and 13 is a convergence coil. , 14 are synchronization signals synchronized with the deflection current cycle, and 15 is a synchronization signal reproduced from the synchronization signal 14. FIG. 2 is a block diagram of the digital correction data generation circuit 6.

In FIG. 2, 18 is a write address control unit, 19 is a read address control unit, 20 is a multiplexer, 21 is a control panel, 22 is a data reversible counter, 23 is a frame memory, 24 is a register, 2
Reference numeral 5 denotes a scanning line number detection unit, 26 denotes an adjustment point number setting unit, 27 denotes a coefficient calculation unit, 28 denotes a cross hatch generator, and 29 denotes a vertical adjustment point processing unit. The operation of the conventional digital convergence device configured as described above will be described below.

In FIGS. 7 and 2, a synchronizing signal 15 synchronized with the deflection current period is applied to one input of a phase comparator 1, and the phase comparison result output of the phase comparator 1 is smoothed by an LPF 2, and the smoothed output is obtained. Input to the VCO 3. The VCO 3 oscillates a clock obtained by multiplying the input synchronization signal 15 by M times. The clock multiplied by the VCO 3 is frequency-divided by the 1 / M frequency divider 5, and the reproduced horizontal synchronizing signal 15 is input to the other side of the phase comparator 1. This 1 / M
M of the frequency divider 5 corresponds to the number of adjustment points in the horizontal direction. Also,
The reproduced horizontal synchronization signal 15 and reproduced clock 17
Drives the read address control unit 19. The cross hatch generator 28 is driven by using the pulse from the read address control unit 19, and the video circuit 12 projects the cross hatch pattern on the projection screen.

On the other hand, a cross point (for example, point A in FIG. 3) at a position where convergence correction is required is designated by an address key of the control panel 21, and a position address is set in the write address control unit 18.

Next, the correction amount is written to the frame memory 23 through the reversible counter 22 while looking at the screen, using a red data write key provided for the color to be corrected, for example, the control panel 21. Usually, this frame memory 2
Since writing to 3 is controlled by the multiplexer 20 so as to be performed during the blanking period of the video signal, the reading of the frame memory 23 is not impaired. In this way, the same operation is performed at each adjustment point.

Next, the reading of the frame memory 23 is performed by the read address control unit 19 for each adjustment point position on the screen.
The correction amount processing in the vertical scanning direction between the adjustment points is performed by the processing unit 29 between the adjustment points in the vertical direction via the register 24 driven by the control unit 9.

In order to correspond to various image signal sources,
It is necessary to perform processing between adjustment points according to the number of scanning lines. Therefore, the synchronization signal 15 is supplied to the number-of-scanning-lines detecting section 25, detects the number of scanning lines in one field, and is applied to the number-of-adjustment-points setting section. The number-of-adjustment-points setting unit 26 calculates the number of scanning lines P in one field and the number Q of adjustment points in the vertical direction from
= P / (Q + 1) number of scanning lines R of the number between adjustment points are obtained,
It is added to the coefficient calculator 27. Further, the output of the adjustment point number setting unit 26 is applied to the write address control unit 18 and the read address control unit 19, and the operation is switched to every R lines.

Further, when reading data between each adjustment point, each scan line correction data is created by a vertical interpolation operation. However, data of scan lines of the entire screen is previously subjected to a vertical interpolation operation, and all data are read out from a frame memory. , And the data is read from the frame memory to perform correction.

As described above, independent convergence correction can be performed for each image signal source for each adjustment point.

[0012]

However, in the above-described conventional configuration, independent convergence correction can be performed for each adjustment point, but a clock and correction data for driving an adjustment pattern generator (cross hatch generator) can be obtained. Since the clock for driving the generator is the same, if no measures are taken, the hatch width of the adjustment pattern becomes large, and the accuracy of the convergence adjustment deteriorates. Since the hatch width of the adjustment pattern is dependent on the number of adjustment points, there is a method of increasing the number of adjustment points and taking measures.However, in this case, since the number of convergence adjustment points is increased, there is a problem that the convergence adjustment time becomes longer. I was

When the digital convergence device is adapted for multi-scan, the conventional configuration requires a VCO
However, the corresponding frequency range is limited because the oscillation frequency range is limited. At this time, when the digital convergence device is used outside the oscillation frequency range of the VCO, there are methods of changing the frequency division ratio of the frequency divider according to the frequency or switching the VCO according to the frequency by using a multi-stage VCO. In the case of (1), since the number of adjustment points changes according to the frequency, the adjustment accuracy varies depending on the corresponding signal source. On the other hand, in the latter case, a control circuit for switching the VCO is required, and constant switching of the LPF may occur in some cases.
Factors of performance degradation (jitter, variation in response speed) as a circuit increase, and in any case, a problem occurs.

[0014]

In order to solve the above-mentioned conventional problems, a digital convergence apparatus according to the present invention comprises:
In claim 1, an automatic frequency discriminating unit which receives a synchronization signal synchronized with the deflection current cycle as an input, a phase comparator which receives the synchronization signal as one input, and L which receives an output thereof as an input.
PF and VCO input with output smoothed by LPF
A 1 / N divider that divides the oscillation output by 1 / N and is controlled by the automatic frequency discriminating unit, and a 1 / M divider that further divides the divided output by 1 / M. Container and this 1 /
The synchronization signal reproduced by the M frequency divider is input to the other of the phase comparators, and the reproduced synchronization signal is input to the phase comparator.
An adjustment pattern generator that uses the oscillation clock oscillated by the VCO as an input clock, a video circuit that receives the output pattern thereof, and the reproduced synchronizing signal that is input, and is divided by the 1 / N divider. Correction data generating unit using the divided output thus obtained as an input clock, a D / A converter receiving the digital correction data output, an LPF receiving an analog output of the D / A converter, and an output thereof And a convergence coil driven by the amplified output.

According to a second aspect of the present invention, there is provided an automatic frequency discriminating unit which receives a synchronization signal synchronized with the deflection current cycle, a phase comparator which receives the synchronization signal as one input, and an LPF which receives the output thereof as an input. A VCO to which the output smoothed by the LPF is input, a 1 / N frequency divider whose oscillation output is frequency-divided by 1 / N and controlled by the automatic frequency discriminating unit, and the frequency-divided output is further divided by 1 A 1 / M frequency divider for dividing the frequency to / M, a synchronization signal reproduced by the 1 / M frequency divider is input to the other of the phase comparators, and the reproduced synchronization signal is input to the other of the phase comparators; An adjustment pattern generator that uses an oscillation clock of the VCO and an output signal of a delay element that receives the oscillation clock as an input clock, a video circuit that receives the output pattern as an input, and the reproduced synchronization signal,
A correction data generator that uses the output of the 1 / N divider as an input clock, a D / A converter that receives the digital correction data output, and an LPF that receives the analog output of the D / A converter And an output amplifying unit for inputting and amplifying the output, and a convergence coil driven by the amplified output.

According to a third aspect of the present invention, there is provided an automatic frequency discriminator which receives a synchronization signal synchronized with a deflection current cycle, a phase comparator which receives the synchronization signal as one input, and an LPF which receives the output thereof as an input. A VCO to which the output smoothed by the LPF is input, a 1 / N frequency divider which divides the oscillation output by 1 / N and is controlled by the automatic frequency discriminating unit, and a divided frequency output which is divided Further, a 1 / M frequency divider for dividing the frequency by 1 / M and a synchronization signal reproduced by the 1 / M frequency divider are input to the other of the phase comparators. An adjustment pattern generator that uses the oscillation clock of the VCO as an input clock, a video circuit that receives the output pattern thereof, and a divided output of the 1 / N divider that receives the reproduced synchronization signal. A correction data generator that serves as a clock, A digital filter having a digital correction data output as input and an oscillation clock of the VCO as an input clock, a D / A converter having the output of the digital filter as input, and an output amplifying section having as input and amplifying the analog output; And a convergence coil driven by the amplified output.

[0017]

According to the structure of the present invention, in the conventional digital convergence device, the operation clock of the adjustment pattern generator and the operation clock of the correction data generator are the same.
Other than increasing the number of adjustment points, it was difficult to accurately adjust convergence with a simple configuration, but by using the above configuration, highly accurate convergence adjustment could be realized with a small-scale circuit configuration. Become.

In addition, since the frequency divider has a two-stage structure and incorporates an automatic frequency discriminating unit, when multi-scan is supported, the accuracy of the adjustment pattern changes according to the synchronization frequency of the external signal source. As a result, convergence accuracy can be improved.

[0019]

An embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of a digital convergence apparatus according to the first embodiment of the present invention. In FIG. 1, 32 is an automatic frequency discriminator, 1 is a phase comparator, 2 is an LPF, 3 is a VCO, 4 is a 1 / N divider,
5 is a 1 / M frequency divider, 7 is an adjustment pattern generator, 9 is a video circuit, 8 is a correction data generator, 10 is a D / A converter, 1
1 is an LPF, 12 is an output amplifier, and 13 is a convergence coil. Reference numeral 14 denotes a synchronization signal synchronized with the deflection current cycle, reference numeral 15 denotes a reproduced synchronization signal, reference numeral 30 denotes an output signal of the adjustment pattern generation unit 7, and reference numeral 31 denotes an output signal of the correction data generation unit 8.

The operation of the digital convergence device according to the first embodiment of the present invention will be described below with reference to FIGS. 1, 2 and 3.

In FIG. 1, the phase of the synchronizing signal 14 synchronized with the deflection current cycle and the phase of the output signal 15 of the 1 / M frequency divider 5 are compared by the phase comparator 1, and the output is input to the LPF 2.
The DC output smoothed by the LPF 2 is input to the VCO 3. The output clock oscillated by the VCO 3 is input to the 1 / N frequency divider 4, the frequency-divided output is input to the 1 / M frequency divider, and the output 15 is fed back to the phase comparator 1 so that the PLL is output. Configure the circuit.

At this time, the frequency division ratio M of the 1 / M frequency divider 5 depends on the number of adjustment points in the horizontal direction, and the frequency division ratio M is independent of the synchronization signal frequency of the externally connected signal source. By making the frequency constant, it is possible to perform adjustment without increasing the number of adjustment points even when the synchronization signal frequency of the externally connected signal source changes. On the other hand, the frequency dividing ratio N of the 1 / N frequency divider 4 is controlled by the automatic frequency discriminating unit 32. As the set value is increased, a more precise adjustment pattern is generated, and as a result, the convergence adjustment accuracy is improved. . FIG. 3 shows an example of the phase relationship between the clock waveforms 16 and 17 with respect to the lattice point A of the adjustment pattern (cross hatch) (example: N = 3, N =
5). Thus, by fixing the frequency division ratio M and changing only the frequency division ratio N, the accuracy of the adjustment pattern can be improved without increasing the number of adjustment points, and the accuracy of the convergence adjustment can be improved. . In addition, when multi-scan is supported, the oscillation frequency of the VCO 3 can always be kept within a certain range by changing the frequency division ratio N according to the synchronization frequency of an external signal source, and the oscillation frequency has a wide range. The multi-scan correspondence can be easily realized by this configuration without using a VCO.

The reproduction synchronizing signal 15 reproduced by the above-described PLL circuit is input to the adjustment pattern generator 7 and the correction data generator 8. Here, an oscillation clock 16 of the VCO 3 is used as a clock for driving the adjustment pattern generation unit 7,
The clock for driving the correction data generator 8 uses the frequency-divided output 17 of the 1 / N frequency divider 4. This adjustment pattern generator 7
The operation principle of the correction data generation unit 8 has been described as the digital correction data generation circuit 6 in the section of the conventional example, and therefore will not be described here. However, in the digital correction data generation circuit 6, the read address control unit 19 and the cross hatch generator 28 correspond to the adjustment pattern generation unit 7. The output signal 30 of the adjustment pattern generator 7 is input to the video circuit 9, and the adjustment pattern is projected at the time of convergence adjustment. On the other hand, the digital correction data output signal 31 of the correction data generator 8 is input to the D / A converter 10 and the output converted to the analog correction amount is input to the LPF 11 to smooth the analog correction waveform, and the output is amplified. The signal is input to the section 12 and amplified. Here, the convergence coil 13 is driven based on the amplified correction amount.

As described above, according to the present embodiment, the frequency divider in the PLL circuit is divided into two by the 1 / N frequency divider 4 and the 1 / M frequency divider 5.
With the step configuration, the accuracy of the convergence adjustment can be improved as compared with the conventional configuration.

(Embodiment 2) FIG. 4 is a block diagram of a digital convergence apparatus according to a second embodiment of the present invention. In FIG. 4, 32 is an automatic frequency discriminator, 1 is a phase comparator, 2 is an LPF, 3 is a VCO, 4 is a 1 / N divider,
5 is a 1 / M frequency divider, 34 is a delay element, 7 is an adjustment pattern generator, 9 is a video circuit, 8 is a correction data generator, 10 is a D / A converter, 11 is an LPF, and 12 is an output amplifier. , 13
Is a convergence coil. 14 is a synchronization signal synchronized with the deflection current cycle, 15 is a reproduced synchronization signal,
Reference numeral 30 denotes an output signal of the adjustment pattern generator 7, reference numeral 31 denotes an output signal of the correction data generator 8, and reference numeral 35 denotes an output signal of the delay element.

The operation of the digital convergence device according to the second embodiment of the present invention will be described below with reference to FIGS.

In FIG. 4, the phase of the synchronization signal 14 synchronized with the deflection current cycle and the phase of the output signal 15 of the 1 / M frequency divider 5 are compared by the phase comparator 1, and the output is input to the LPF 2.
The DC output smoothed by the LPF 2 is input to the VCO 3. The output clock oscillated by the VCO 3 is input to the 1 / N frequency divider 4, the frequency-divided output is input to the 1 / M frequency divider, and the output 15 is fed back to the phase comparator 1 so that the PLL is output. Configure the circuit.

At this time, the frequency division ratio M of the 1 / M frequency divider 5 depends on the number of adjustment points in the horizontal direction, and the frequency division ratio M is independent of the synchronization signal frequency of the signal source connected to the outside. By making the frequency constant, it is possible to perform adjustment without increasing the number of adjustment points even when the synchronization signal frequency of the externally connected signal source changes. On the other hand, the frequency dividing ratio N of the 1 / N frequency divider 4 is controlled by the automatic frequency discriminating unit 32. As the set value is increased, a more precise adjustment pattern is generated, and as a result, the convergence adjustment accuracy is improved. . However, in the configuration of the first aspect, the upper limit of the frequency division ratio N is limited by the upper limit of the oscillation frequency of the VCO 3, and as a result, the accuracy of the convergence adjustment is limited. Therefore, in the present invention, the output of the 1 / N divider 4 is input to the delay element 34, and the delayed output clock 35 and the VCO 3
The oscillation clock 16 is input as a clock of the adjustment pattern generation unit 7 and time-division processing is performed, so that a more accurate adjustment pattern can be generated, and the adjustment accuracy can be further improved. Here, the same effect can be obtained with the delay element 34 whether it is a digital element or an analog element. FIG. 5 shows an example of the phase relationship between the clock waveforms 17, 16 and 35 with respect to the lattice point A of the adjustment pattern (cross hatch). As described above, by operating the circuit in the adjustment pattern generation unit by time division processing, the accuracy of the convergence adjustment can be further improved.

The reproduction synchronization signal 15 reproduced by the PLL circuit as described above is input to the adjustment pattern generator 7 and the correction data generator 8. Here, the clock for driving the adjustment pattern generator 7 uses the oscillation clock 16 of the VCO 3 and the output delay clock of the delay element 34 to which the oscillation clock 16 is input, and the clock for driving the correction data generator 8 is 1 / N. The frequency division output 17 of the frequency divider 4 is used. The principle of operation of the adjustment pattern generator 7 and the correction data generator 8 has been described as the digital correction data generator 6 in the section of the conventional example, and thus will not be described here. However, in the digital correction data generation circuit 6, the read address control unit 19 and the cross hatch generator 28 correspond to the adjustment pattern generation unit 7, and perform a time-division operation using two types of clocks. The output signal 30 of the adjustment pattern generator 7 is input to the video circuit 9, and the adjustment pattern is projected at the time of convergence adjustment. On the other hand, the digital correction data output signal 31 of the correction data generator 8 is input to the D / A converter 10 and the output converted to the analog correction amount is input to the LPF 11 to smooth the analog correction waveform, and the output is amplified. The signal is input to the section 12 and amplified. Here, the convergence coil 13 is driven based on the amplified correction amount.

As described above, according to the present embodiment, the frequency divider in the PLL circuit is divided into two by the 1 / N frequency divider 4 and the 1 / M frequency divider 5.
The convergence adjustment accuracy can be further improved as compared with the conventional configuration by using a stage configuration and performing the time-division processing on the adjustment pattern generating unit 7 with clocks having different phases.

(Embodiment 3) FIG. 6 is a block diagram of a digital convergence apparatus according to a third embodiment of the present invention. In FIG. 6, 32 is an automatic frequency discriminator, 1 is a phase comparator, 2 is an LPF, 3 is a VCO, 4 is a 1 / N divider,
5 is a 1 / M frequency divider, 7 is an adjustment pattern generator, 9 is a video circuit, 8 is a correction data generator, 36 is a digital filter, 10 is a D / A converter, 12 is an output amplifier, and 13 is convergence. Coil. 14 is a synchronization signal synchronized with the deflection current cycle, 15 is a reproduced synchronization signal, 30
Is an output signal of the adjustment pattern generator 7, and 31 is an output signal of the correction data generator 8.

The operation of the digital convergence device according to the third embodiment of the present invention will be described below with reference to FIG.

In FIG. 6, the phase of the synchronization signal 14 synchronized with the deflection current cycle and the phase of the output signal 15 of the 1 / M frequency divider 5 are compared by the phase comparator 1, and the output is input to the LPF 2.
The DC output smoothed by the LPF 2 is input to the VCO 3. The output clock oscillated by the VCO 3 is input to the 1 / N frequency divider 4, the frequency-divided output is input to the 1 / M frequency divider, and the output 15 is fed back to the phase comparator 1 so that the PLL is output. Configure the circuit.

At this time, the division ratio M of the 1 / M frequency divider 5 depends on the number of adjustment points in the horizontal direction, and this division ratio M is independent of the synchronization signal frequency of the signal source connected to the outside. By making the frequency constant, it is possible to perform adjustment without increasing the number of adjustment points even when the synchronization signal frequency of the externally connected signal source changes. On the other hand, the frequency dividing ratio N of the 1 / N frequency divider 4 is controlled by the automatic frequency discriminating unit 32. As the set value is increased, a more precise adjustment pattern is generated, and as a result, the convergence adjustment accuracy is improved. . Thus, the division ratio M
Is fixed, and only the dividing ratio N is changed, the accuracy of the adjustment pattern can be improved without increasing the number of adjustment points, and the accuracy of the convergence adjustment can be improved.

The reproduction synchronization signal 15 reproduced by the PLL circuit as described above is input to the adjustment pattern generator 7 and the correction data generator 8. Here, an oscillation clock 16 of the VCO 3 is used as a clock for driving the adjustment pattern generation unit 7,
The clock for driving the correction data generator 8 uses the frequency-divided output 17 of the 1 / N frequency divider 4. This adjustment pattern generator 7
The operation principle of the correction data generation unit 8 has been described as the digital correction data generation circuit 6 in the section of the conventional example, and therefore will not be described here. However, in the digital correction data generation circuit 6, the read address control unit 19 and the cross hatch generator 28 correspond to the adjustment pattern generation unit 7. The output signal 30 of the adjustment pattern generator 7 is input to the video circuit 9, and the adjustment pattern is projected at the time of convergence adjustment. On the other hand, the digital correction data output signal 31 of the correction data generator 8 is input to a digital filter 36 using the oscillation clock 16 of the VCO 3 as an input clock, where the correction between the respective adjustment points is performed digitally, and the output is output. Is input to the D / A converter 10 and converted into an analog correction amount. Here, since the accuracy of the digital filter 36 is determined by the frequency division ratio N of the 1 / N frequency divider 4,
By increasing N, the filter accuracy for smoothing the correction data in the horizontal direction can be easily improved. This D / A converter 1
The analog output of 0 is input to the output amplifier 12 and amplified.
Here, the convergence coil 13 is driven based on the amplified correction amount.

As described above, according to the present embodiment, the frequency divider in the PLL circuit is divided into two by the 1 / N frequency divider 4 and the 1 / M frequency divider 5.
By using a stage configuration and using a digital filter, it is possible to improve the accuracy of the adjustment pattern and the accuracy between the horizontal adjustment points of the convergence correction data as compared with the conventional configuration.

[0038]

As described above, in the conventional digital convergence apparatus, independent convergence correction can be performed for each adjustment point, but the clock and correction data generation section for driving the adjustment pattern generator (cross hatch generator) are provided. Since the driving clock is the same, the hatch width of the adjustment pattern becomes large, and the accuracy of the convergence adjustment deteriorates. Since the hatch width of the adjustment pattern depends on the number of adjustment points, there is a method of increasing the number of adjustment points and taking measures.
Since the number of convergence adjustment points is increased, there is a problem that the convergence adjustment time becomes long. Further, when the digital convergence device is compatible with multi-scan, the conventional configuration has a problem that the range of the corresponding frequency is limited because the oscillation frequency range of the VCO is limited.

According to the present invention, the above-described problems can be easily solved without increasing the number of adjustment points by configuring two types of frequency dividers in the digital convergence device. It will be easier. Further, in the configuration of claim 2, the accuracy of the convergence adjustment is further improved as compared with the configuration of claim 1, and in the configuration of claim 3, the accuracy of the adjustment pattern is improved and the distance between the horizontal adjustment points of the convergence correction data is improved. Improving accuracy is easily realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital convergence device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a digital correction data generation circuit in FIG. 1;

FIG. 3 is a phase relationship diagram of each signal in FIG. 1;

FIG. 4 is a block diagram of a digital convergence device according to an embodiment of the present invention.

FIG. 5 is a phase relationship diagram of each signal in FIG. 4;

FIG. 6 is a block diagram of a digital convergence device according to an embodiment of the present invention.

FIG. 7 is a block diagram of a conventional digital convergence device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 phase comparator 2 low-pass filter 3 voltage-controlled oscillator 4 1 / N frequency divider 5 1 / M frequency divider 6 digital correction data generator 7 adjustment pattern generator 8 correction data generator 9 video circuit 10 D / A Converter 11 Low-pass filter 12 Output amplification unit 13 Convergence coil 32 Automatic frequency discrimination unit 34 Delay element 36 Digital filter

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 9/12-9/31

Claims (3)

(57) [Claims] 1. A multi-scan compatible digital convergence apparatus, comprising: an automatic frequency discriminating unit which receives a synchronization signal synchronized with a deflection current cycle; a phase comparator which receives the synchronization signal as one input; Low-pass filter (hereinafter referred to as LPF) with the output of
A voltage-controlled oscillator (hereinafter, referred to as a VCO) to which an output smoothed by the LPF is input, and a 1 / N frequency divider that divides the output of the VCO by 1 / N and is controlled by the automatic frequency determination unit. A 1 / M frequency divider that divides the output of the 1 / N frequency divider by 1 / M, and inputs the synchronization signal reproduced by the 1 / M frequency divider to the other of the phase comparators An adjustment pattern generator which receives the reproduced synchronization signal as an input and the oscillation clock of the VCO as an input clock, and inputs the reproduced synchronization signal and outputs the frequency-divided output of the 1 / N frequency divider as an input clock. A digital convergence device comprising: a correction data generator configured as described above; and a D / A converter to which an output of the correction data generator is input. 2. A multi-scan compatible digital convergence device, comprising: an automatic frequency discriminating unit which receives a synchronization signal synchronized with a deflection current cycle; a phase comparator which receives the synchronization signal as one input; An LPF that receives the output of the VCO, a VCO that receives an output smoothed by the LPF, a 1 / N divider that divides the output of the VCO by 1 / N and is controlled by the automatic frequency discriminator. Divides the output of the 1 / N divider to 1 / M
A frequency divider and a synchronizing signal reproduced by the 1 / M frequency divider are input to the other of the phase comparators. The reproduced synchronizing signal is input, and an oscillation clock of the VCO and the oscillation clock are input. An adjustment pattern generator that uses the output signals of the delay elements as input clocks, and a correction data generator that receives the reproduced synchronization signal and uses the frequency-divided output of the 1 / N divider as an input clock. And a D / A converter to which an output of the correction data generator is input. 3. A multi-scan compatible digital convergence device, comprising: an automatic frequency discriminator that receives a synchronization signal synchronized with a deflection current period; a phase comparator that receives the synchronization signal as one input; An LPF that receives the output of the VCO, a VCO that receives an output smoothed by the LPF, a 1 / N divider that divides the output of the VCO by 1 / N and is controlled by the automatic frequency discriminator. Divides the output of the 1 / N divider to 1 / M
A frequency divider and an adjustment pattern in which the synchronization signal reproduced by the 1 / M frequency divider is input to the other of the phase comparators, the reproduced synchronization signal is input, and the oscillation clock of the VCO is an input clock. A generation unit, a correction data generation unit that receives the reproduced synchronization signal and uses the frequency-divided output of the 1 / N divider as an input clock, and an oscillation clock of the VCO that receives the output of the correction data generation unit as an input A digital convergence device, comprising: a digital filter using the input clock as an input clock; and a D / A converter using the output of the digital filter as an input.