JP3249362B2 - Clock recovery circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit, and more particularly, to a clock recovery circuit for generating a sampling clock for A / D conversion of a color video signal in a VTR or a TV set. The present invention relates to a clock recovery circuit.

[0002]

2. Description of the Related Art In order to sample a composite color video signal in synchronization with the color burst signal, conventionally,
Constituting a so-called burst PLL (phase locked loop),
The sampling clock is obtained from the output of the PLL. That is, referring to FIG. 3, the input composite color video signal is applied to A / D converter 3 through low-pass filter 1 and pedestal clamp circuit 2 for removing aliasing noise, and is generated by PLL 4.
A / D conversion is performed based on a sampling clock of Fsc (four times the frequency of the subcarrier).

In the PLL 4, a composite color video signal is applied to a band-pass filter 4a, where it is subjected to Y / C separation. The color signal component (burst signal) from the band pass filter 4a is provided to the phase comparator 4b. The composite color video signal is also provided to the sync separation circuit 4c.
The burst gate pulse generation circuit 4d creates a burst gate pulse based on the horizontal synchronization signal output from the synchronization separation circuit 4c, and the burst gate pulse activates the phase comparator 4b. Therefore, during the burst gate pulse period, the phase comparator 4b outputs the oscillation signal of the voltage controlled oscillator (VCO) 4e having the oscillation frequency of 4Fsc to 1
The phase of the output of the frequency dividing circuit 4f for dividing the frequency by / N (for example, 1/4) is compared with the burst signal. Phase comparator 4
The output of b is supplied to the voltage-controlled oscillator 4f via the low-pass filter 4g. Thus, the burst PL
L4 is configured.

The output of the A / D converter 3 is processed in a digital signal processor (DSP) 5 by a three-dimensional Y / C separation circuit 5a and the like, and then processed by a D / A converter 6a.
And 6b, and converted again into an analog luminance signal and an analog color signal. D / A converters 6a and 6
The output of b is further provided to a demodulation circuit (not shown) and demodulated by analog signal processing.

In the prior art shown in FIG. 3, an uncertain phase between the sampling clock and the burst signal supplied to the A / D converter 3 due to the temperature drift of the band-pass filter 4a and the pedestal clamp circuit 2 and the like. An error may occur. For this reason, color demodulation by digital signal processing cannot be performed well, and as shown in FIG.
Since the color demodulation is performed after the conversion into the analog color signal by the converter 6b, the circuit configuration is complicated and the signal processing efficiency is low.

The disadvantage of the prior art in FIG. 3 that an uncertain phase error occurs between the sampling clock and the burst signal can be eliminated by the prior art in FIG. In the prior art shown in FIG. 4, the DSP 5 is provided with a phase comparator 7 and a phase shifter 8, and a burst signal (burst data) converted into a digital signal by the A / D converter 3 and a sampling clock from the voltage controlled oscillator 4e. Is detected by the phase comparator 7, and the phase of the sampling clock from the voltage controlled oscillator 4e is changed by the phase shifter 8 in accordance with the phase error, and is supplied to the three-dimensional Y / C separation circuit 5a.

[0007]

In the prior art shown in FIG. 4, it is necessary to average burst data in one field, for example, in order to remove the influence of noise. Therefore, a large amount of burst data is stored. However, there is a disadvantage that a large capacity memory is required. Hence,
A main object of the present invention is to provide a clock recovery circuit capable of obtaining a clock signal synchronized with a digitized burst signal with a simple circuit configuration.

[0008]

SUMMARY OF THE INVENTION The present invention provides a variable frequency oscillator whose oscillation frequency is changed by a control signal,
A / D converter for A / D converting at least an intermittent reference frequency signal of a television signal based on an oscillation signal from a variable frequency oscillator, and sample data obtained by sampling an output from the A / D converter at a reference frequency , A comparison signal data generating means for generating comparison signal data at a constant level or a substantially constant level at least during a comparison period, a comparison means for comparing sample data with comparison signal data, and a control signal generating means for supplying a variable frequency oscillator control signal in the reference frequency signal period on the basis of the output of the comparison means, the control signal generator
The means is an analog low-pass filter for integrating the output of the comparing means.
Filter, output of comparison means and analog low-pass filter
And a reference frequency signal
Control the three-state switch according to the output of the comparison means during the period of
And a switch control means for controlling the clock recovery.

[0009]

The A / D converter performs A / D conversion of an intermittent reference frequency signal (burst signal) of a television signal with an oscillation signal of a variable frequency oscillator, and outputs burst data.
In the comparing means, the data (SI) obtained by sampling the burst data at the reference frequency, that is, the sub-carrier frequency (F _SC ), and the band elimination filter (B) from the burst data.
EF) or comparison signal data (RS) from which a color signal component has been removed by a low-pass filter is compared.

When the comparison signal data (RS) is larger (leading) than the data (SI), the comparison means
For example, a high-level signal (H) is output, and the high-level signal (H) is supplied to the variable frequency oscillator as a control signal by control voltage generating means including, for example, an analog low-pass filter. Specifically, the capacitor of the low-pass filter is charged by the high-level signal (H), and a control signal for reducing the oscillation frequency of the variable frequency oscillator is output.

On the other hand, when the comparison signal data (RS) is smaller (late) than the data (SI), for example, a low level signal (L) is output from the comparison means. , The capacitor of the low-pass filter is discharged. As a result, a control signal for increasing the oscillation frequency of the variable frequency oscillator is output from the low-pass filter.

[0012]

According to the present invention, a clock signal having a fixed phase relationship with respect to a digitized reference frequency signal can be generated with a simple circuit configuration. The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0013]

Referring to FIG. 1, a clock recovery circuit 10 of this embodiment includes a PLL 12 and a DSP 14. The composite color video signal input from the input terminal 16 is supplied to a low-pass filter 18, where the composite color video signal has a frequency lower than half the sampling frequency (Nyquist frequency) in order to prevent aliasing that occurs when an analog signal is converted into a digital signal. High frequency video signals are removed. That is, the low-pass filter 18 corresponds to a Y / C separation circuit,
The low-pass filter 18 outputs a luminance signal component of the input video signal and supplies the same to the clamp circuit 20.

The clamp circuit 20 is a so-called pedestal clamp for clamping at a pedestal level, and adjusts a black level of an input video signal. The video signal (luminance signal) whose pedestal level is fixed is
A / D converter 22 where the PLL 12
Are converted into digital signals in accordance with a sampling clock having a frequency of 4F _SC from the voltage controlled oscillator 24 included in.

The digitally converted video signal (video data) is applied to a three-dimensional Y / C separation circuit 26 included in the DSP 14, and to a sample circuit 28 and a band elimination filter (BEF) 30 in the same DSP 14. Can be In the three-dimensional Y / C separation circuit 26, the video data is a clock signal (4
F _SC = 14.3 MHz). Y
The luminance signal (Y) and the chrominance signal (C) from the / C separation circuit 26 are supplied to D / A converters 31a and 31b, and are subjected to analog conversion.

The digital video signal input to the sample circuit 28 is sampled at a subcarrier cycle (F _SC ), and the sample circuit 28 outputs sample data (SI) to the comparator 32. In the comparator 32, the sample data (SI) is compared with the luminance signal data (RS) from which the sub-carrier frequency component has been sufficiently removed by the band elimination filter 30.

The luminance signal data processed by the band elimination filter 30 is supplied to a sync separation circuit 34. A burst gate pulse generation circuit 36 generates a burst gate pulse based on the horizontal synchronization signal from the synchronization separation circuit 34. That is, the burst gate pulse generation circuit 36
Includes a counter (not shown) for counting the time from the horizontal synchronizing signal, and a decoder (not shown) for decoding the output from the counter.

The burst gate pulse (BGP) output from burst gate pulse generation circuit 36 is applied to control signal generation circuit 38, whereby the output from comparator 32 is applied to PLL 12 only during the burst period. That is, the control signal generating circuit 38 receives the inversion of the output signal from the comparator 32 and the burst gate pulse from the burst gate pulse generating circuit 36 as an input.
And a three-state switch 42 that can be switched between three states by the output of the AND gate 40, and the sample data (SI)
And the luminance signal data (RS) from the band elimination filter 30
The three-state switch 42 is turned on only during the burst period when there is a difference (phase difference) between the two. then,
An output signal from the comparator 32 is supplied to a low-pass filter 44 via a three-state switch 42.

The low-pass filter 44 includes a capacitor (not shown), and outputs both signal data (S) from the comparator 32.
A voltage corresponding to the phase error between I, RS) is output and given to the voltage controlled oscillator 24. More specifically, FIG.
(A) shows an input burst signal. And the comparator 32
At this time, the output signal data (RS) from the band elimination filter 30 shown in FIG. 2D is compared with the sample data (SI) from the sample circuit 28. And,
Data (RS) as shown in FIG.
(SI−RS = −ΔE),
That is, the data (RS) is used for the sample data (SI).
Is advanced, the comparator 32 outputs, for example, a high-level (H) signal to the three-state switch 42.

At this time, the comparator 32 also outputs AN
For example, a low level switching signal (L ') is output to D gate 40. The switching signal (L ′) is output when both signals (SI and RS) input to the comparator 32 have a phase error (SI ≠ RS). By this switching signal (L ') and the burst gate pulse (BGP) from the burst gate pulse generating circuit 36, the tri-state switch 42 is turned on, and the high level signal (H) from the comparator 32 is turned on. Is supplied to the low-pass filter 44. With this signal, the capacitor (not shown) of the low-pass filter 44 is charged. Therefore, the low-pass filter 44 outputs a control signal for reducing the oscillation frequency of the voltage controlled oscillator 24.

On the other hand, as shown in FIG. 2C, when the data (RS) from the band elimination filter 30 is smaller (slower) than the sample data (SI) (SI-RS
= ΔE), the comparator 32 outputs a low-level signal (L). As described above, the control signal generation circuit 38 becomes conductive during a burst period when both signals (SI and RS) input to the comparator 32 have a phase difference, and the control signal generation circuit 38 The level signal (L) is applied to the low-pass filter 44, and the low-pass filter 4
4 is discharged. Therefore, the low-pass filter 44 outputs a control signal for increasing the oscillation frequency of the voltage controlled oscillator 24.

In response to the control signal output from the low-pass filter 44, the voltage controlled oscillator 24 outputs a clock signal whose oscillation frequency has changed according to the phase error data (ΔE, −ΔE). That is, the low-pass filter 4
4, the phase error data generated between the two signals (SI and RS) is averaged. Therefore, a clock signal having a fixed phase relationship with respect to the reference frequency signal (input burst signal) is always output from the voltage controlled oscillator 24.
Output to the A / D converter 22.

According to the above-described embodiment, most of the components constituting the clock recovery circuit can be realized by the digital signal processing circuit. Therefore, these digital signal processing circuits are integrated into one DSP 14 to form one chip. Can be. As a means for removing a color signal component from video data, the above-described band elimination filter (BEF) is used.
A low-pass filter (LPF) may be used instead of 30.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a waveform diagram showing a phase comparison in the comparator of FIG. 1 embodiment.

FIG. 3 is a block diagram showing a conventional technique.

FIG. 4 is a block diagram showing a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Clock regeneration circuit 12 ... PLL 14 ... DSP 22 ... A / D converter 24 ... Voltage controlled oscillator 28 ... Sampling circuit 30 ... Band elimination filter (BEF) 32 ... Comparator 38 ... Control signal generation circuit 44 ... Low pass filter

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 9/44-9/78 H04N 11/00-11/22

Claims (3)

(57) [Claims] 1. A variable frequency oscillator whose oscillation frequency is changed by a control signal, wherein at least an intermittent reference frequency signal of a television signal is A / O based on an oscillation signal from the variable frequency oscillator.
An A / D converter for D-conversion; sampling means for sampling an output from the A / D converter at a reference frequency to output sample data; and a comparison for generating comparison signal data having a constant level at least during a comparison period. Signal data generating means; comparing means for comparing the sample data with the comparison signal data; and providing the control signal to the variable frequency oscillator during the reference frequency signal period based on an output of the comparing means. a control signal generating means, said control signal generating means to integrate the output of the comparing means
An analog low-pass filter, and an output of the comparing means.
3 states inserted between the analog low-pass filter
Status switch and the comparator during the period of the reference frequency signal.
A switch for controlling the three-state switch according to the output of the stage.
And a clock recovery circuit. 2. The A / D converter according to claim 2, wherein said comparison signal data generating means includes an A / D converter.
2. The clock recovery circuit according to claim 1, further comprising a filter for removing a color signal component from an output of the converter. 3. The clock recovery circuit according to claim 1, wherein said reference frequency is a subcarrier frequency of said television signal.