JP3251306B2 - Semiconductor logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor logic circuit,
In particular, the present invention relates to a low-power circuit technology for an ECL circuit constituted by bipolar transistors.

[0002]

2. Description of the Related Art Conventionally, as a high-speed semiconductor logic circuit, an ECL circuit composed of bipolar transistors has been frequently used. The ECL circuit is disclosed in, for example,
As shown in No. 6, it consists of an input emitter follower, a current switch and an output emitter follower. Among them, the input emitter follower is not necessarily required, and therefore, the description of this portion will be omitted in the following description. By the way, in this ECL circuit, the transistors are not saturated, and the levels of "1" and "0" are defined by using the cutoff function. You can get many outs. Further, since the NOR and the OR can be taken at the same time, there is an advantage that complicated logical processing can be performed with a small number. However, since the transistor is not used up to the saturation region, the use efficiency of the power supply is low and the power consumption is not considered.

[0003]

FIG. 2 is a circuit diagram of a conventional ECL circuit. In the ECL circuit of this figure, an input signal IN is applied to a base, a first current source I1 is connected to an emitter, a first bipolar transistor Q1 is connected to a load element R1 to a collector, and a reference voltage VBB is applied to a base. The second bipolar transistor Q2 having the emitter connected to the emitter of the first bipolar transistor Q1 and the base connected to the load element R1;
It comprises a third bipolar transistor Q3 that outputs an output signal OUT from the emitter, and a second current source I2. In this circuit, a current source I1, a bipolar transistor Q
The portion composed of the transistor Q1, and the load element R1 is a portion generally called a current switch, and the portion composed of the bipolar transistor Q3 and the current source I2 is a portion generally called an output emitter follower.

[0004] The power consumption PD of this circuit is as follows, assuming that the power supply voltage of the current switch section is VEE and the power supply voltage of the output emitter follower section is VT.

[0005]

(Equation 3)

[0006]

Here, for example, VEE = VT = -5.2
V, I1 = 1 mA, I2 = 2 mA, PD = 1
5.6 mW.

An object of the present invention is to make the power consumption of the output emitter follower unit, that is, the second term of the above equation (3) zero,
It is to reduce the power consumption of a circuit.

[0009]

The above object is achieved by applying an input signal or a reference voltage to a base of a semiconductor logic circuit, connecting a current source or a resistor to an emitter, and connecting a first source to a collector.
A reference voltage or a negative signal of the input signal is applied to a base, an emitter of the first bipolar transistor is connected to an emitter, and a second load element is connected to a collector. Are connected, the first load element is connected to the base, the third bipolar transistor outputs an output signal from the emitter, and the drain is connected to the emitter of the third bipolar transistor. A field effect transistor having a gate connected to the second load element, a base connected to a source of the field effect transistor, a collector connected to an emitter of the third bipolar transistor, and a voltage source connected to the emitter. Achieved by using a fourth bipolar transistor It is.

[0010]

The fourth bipolar transistor supplies a discharge current to the output signal line, similarly to the second current source I2. Here, since the field effect transistor turns on the fourth bipolar transistor only when the output signal switches from the H level to the L level, the discharge current flows only when necessary and does not always flow. Therefore, the power consumption of the output emitter follower, that is, the second term of the above equation (3) can be made zero, and the power consumption of the circuit can be reduced accordingly.

[0011]

FIG. 1 is a diagram showing a first embodiment of the present invention. In the figure, a semiconductor logic circuit according to the present invention comprises a first bipolar transistor Q1 having a base to which an input signal IN is applied, an emitter connected to a current source I1, and a collector connected to a first load element R1; The reference voltage VBB is applied to the base, the emitter is connected to the emitter of the first bipolar transistor Q1, and the collector is connected to the second bipolar transistor Q1.
A second bipolar transistor Q2 connected to the load element R2, a third bipolar transistor Q3 connected to the base to the first load element R1 and outputting an output signal OUT from the emitter, and a third bipolar transistor Q3 connected to the drain. Of the bipolar transistor Q3, the field effect transistor M1 having the gate connected to the second load element R2, and the field effect transistor M1 having the base connected.
Of the third bipolar transistor Q3, the collector of which is connected to the emitter of the third bipolar transistor Q3, and the emitter of which is connected to the voltage source VT.
4. Here, the relationship among the current source I1, the equivalent resistance R1 of the first load element, the base-emitter voltage VBE of the third bipolar transistor Q3, and the threshold voltage VTH of the field effect transistor M1 is as follows.

[0012]

(Equation 1)

When the input signal IN is set to H level,
That is, when the output signal OUT is at the L level, the field effect transistor M1 turns on, the bipolar transistor Q4 turns on, and supplies a discharge current to the output signal line. However, as described later, when the output signal OUT has a sufficiently low potential, the base potential of the bipolar transistor Q4 decreases,
Turns off automatically. That is, the bipolar transistor Q4 supplies a discharge current to the output signal line, similarly to the second current source I2 in FIG. However, since the bipolar transistor Q4 is turned on only when the output signal OUT switches from the H level to the L level, the discharge current flows only when necessary and does not always flow.

Further,

[0015]

(Equation 2)

Here, R2 is an equivalent resistance of the second load element.

When the input signal IN is set at L level, that is, when the output signal OUT is at H level, the field effect transistor M1 is turned off, as described later. Therefore, bipolar transistor Q4 is turned off, and no current flows through Q4. That is, the power consumption of the output emitter follower unit of this circuit is zero, and the power consumption PD of this circuit is only the power consumption of the current switch unit. Therefore, assuming that the power supply voltage of the current switch unit is VEE, the power consumption PD of this circuit is

[0018]

(Equation 4)

## EQU1 ## That is, the second term of the above equation (3) can be set to zero, and power consumption can be reduced accordingly.

The following quantitatively shows how much the power consumption increases in the present circuit if Equation 2 is not satisfied. Now, the current of the field effect transistor M1 is ID, and the grounded emitter current amplification factor of the bipolar transistor Q4 is H.
FE, power consumption PD of output emitter follower
(EF)

[0021]

(Equation 5)

Can be written as

Here, in FIG. 1, the input signal IN is H
When the level is switched to the level, the potential of the output signal OUT becomes −
Switch to R1 · I1-VBE (L level). At this time, if M1 is on, the bipolar transistor Q
4 also changes to −R1 · I1-VBE.
Therefore, when the power supply voltage VT is set to about -R1, I1-2, VBE, the output signal OUT becomes L level,
When the base potential of Q4 becomes -R1.I1-VBE, bipolar transistor Q4 is automatically turned off. At this time, the ID is obviously zero. Therefore, the power consumption PD of the output emitter follower unit when the input signal IN is at the H level
(EF) may be considered to be zero.

On the other hand, when the input signal IN is at the L level, the ID
Is

[0025]

(Equation 6)

[0026]

(Equation 7)

Here, β: proportionality constant, VGS: gate-source voltage of M1, VTH: threshold voltage of M1.

Can be represented by

When the input signal IN is at the L level, the gate voltage of M1 is -R2 · I1, and the source voltage of M1 is VT + V
Since BE = −R1 · I1-VBE, VGS of M1 is obtained.
Is

[0030]

(Equation 8)

It can be written as Therefore, PD (EF) is

[0032]

(Equation 9)

[0033]

(Equation 10)

## EQU1 ## Here, for example, R1 = 0.4K
Ω, I1 = 1mA, VBE = 0.8V, VT
Is VT = −R1 · I1-2 · VBE = −2.0V, VEE = −5.2V, β = 20 μS / V, HFE = 1
Assuming 00, PD (EF) and PD are as shown in Table 1, and PD is as shown in FIG. In this table, the PD of the conventional circuit is also shown. That is, Table 1 and FIG. 6 are tables showing also the effects of the present invention.

[0035]

[Table 1]

From Table 1 or FIG. 6, (-R2 · I1)-
If (−R1 · I1−VBE) −VTH is larger than 0 V, that is, if Expression 2 is not satisfied, the power consumption PD sharply increases, for example, (−R2 · I1) − (− R1 ·
It can be seen that when (I1-VBE) -VTH is 2 V or more, the PD becomes larger than before. On the other hand, (−
R2 · I1)-(− R1 · I1-VBE) -VTH
When the voltage is reduced to 0 V or less according to the present invention, the PD is reduced to about 1/3 of the conventional value.
Can be reduced to

FIG. 3 is a diagram showing a second embodiment of the present invention. This drawing is different from FIG. 1 in that the reference voltage VBB is applied to the base of Q2 in FIG. 1, whereas the negative signal IN 'of the input signal IN is applied to the base of Q2 in this drawing. It is. In other words, this drawing is different only in that the current switch is driven by a differential signal. Therefore,
In this diagram, the discussion described in FIG. 1 holds as it is, and the power consumption of the logic circuit can be reduced.

FIG. 4 is a diagram showing a third embodiment of the present invention. This drawing differs from FIG. 1 in that one input (I
N), in this figure, a bipolar transistor Q11 is added to provide two inputs (IN1, IN11). That is, while the inverter circuit is configured in accordance with the present invention in FIG. 1, this embodiment differs only in that a two-input NOR circuit is configured in accordance with the present invention. Therefore, the discussion described with reference to FIG. 1 holds true in this diagram, and the power consumption of the logic circuit can be reduced.

FIG. 5 is a diagram showing a fourth embodiment of the present invention. This drawing is different from FIG. 4 in that one output (OU
T), in this figure, bipolar transistors Q3 'and Q4' and a field effect transistor M1 'are added to provide two outputs (OUT, OUT'). That is, in FIG. 1, a two-input NOR circuit is configured according to the present invention, whereas in FIG. 1, a two-input NOR circuit is configured according to the present invention.
The only difference is that the R and OR circuits are configured. Therefore,
In this diagram, the discussion described in FIG. 1 holds as it is, and the power consumption of the logic circuit can be reduced.

In the above embodiment, the bipolar transistor is constituted by an NPN transistor and the field effect transistor is constituted by an N-channel transistor.
The bipolar transistor is composed of a PNP transistor, and the field-effect transistor is composed of a P-channel transistor.
The relationship between the potentials may be completely reversed.

[0041]

As described above, when the present invention is used, the power consumption PD of the conventional circuit,

[0042]

(Equation 3)

Among them, the second term can be set to zero, and the power consumption of the circuit can be reduced accordingly.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a conventional ECL circuit.

FIG. 3 is a diagram showing a second embodiment of the present invention.

FIG. 4 is a diagram showing a third embodiment of the present invention.

FIG. 5 is a diagram showing a fourth embodiment of the present invention.

FIG. 6 is a diagram showing the effect of the present invention.

[Explanation of symbols]

IN: input signal, VBB: reference voltage, OUT: output signal, Q1, Q2, Q3, Q4: bipolar transistor, R1, R2: load element, M1: field effect transistor, I1: current source, VEE, VT: voltage source .

──────────────────────────────────────────────────続 き Continuing from the front page (72) Kunihiko Yamaguchi 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Hitachi Central Research Laboratory, Inc. (72) Kazuo Kanaya 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Yoji Dei 1-280 Higashi Koikebo, Kokubunji-shi, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Kenichi Ohata 3681 Hayano, Mobara-shi, Chiba Prefecture Hitachi Device Engineering Co., Ltd. (72) Inventor Yoshiaki Sakurai 3681 Hayano Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. (56) References JP-A-4-130823 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 19/00-19/096

Claims (5)

(57) [Claims] 1. A first bipolar transistor having a current source or a resistor connected to an emitter, and the first bipolar transistor connected to an emitter.
Of the second transistor to which the emitter of the bipolar transistor is connected
A current switch section comprising a bipolar transistor, a third bipolar transistor receiving a collector signal of the first bipolar transistor at a base and outputting an output signal from an emitter, and an emitter of the third bipolar transistor. And a discharge circuit connected to the emitter follower portion, wherein the discharge circuit is connected to a fourth bipolar transistor having an emitter connected to the emitter of the third bipolar transistor and an emitter connected to a voltage source. A bipolar transistor,
A semiconductor logic circuit, comprising: a field-effect transistor that receives a collector signal of the second bipolar transistor at a gate and controls on / off of the fourth bipolar transistor. 2. An input signal or reference voltage is applied to a base, a current source or a resistor is connected to an emitter, a first load element is connected to a collector, and a reference voltage or a reference voltage is applied to a base. A negative signal of the input signal is applied, the emitter is connected to the emitter of the first bipolar transistor, the collector is connected to the second load transistor, the base is the second load transistor, and the base is the first load element. A third bipolar transistor connected to output an output signal from the emitter; a field effect transistor having the drain connected to the emitter of the third bipolar transistor and the gate connected to the second load element; and a base connected to the base. The source of the field effect transistor is connected, and the collector is connected to the third bipolar transistor. The emitter is connected, the semiconductor logic circuit composed of the fourth bipolar transistor voltage source emitter connected. 3. The current I1 of said current source or resistor and a first current I1
The relationship among the equivalent resistance R1 of the load element, the equivalent resistance R2 of the second load element, the base-emitter voltage VBE of the third bipolar transistor, and the threshold voltage VTH of the field effect transistor is given by 3. The semiconductor logic circuit according to claim 2, wherein: 4. A current I1 of said current source or resistor,
The relationship among the equivalent resistance R1 of the load element, the equivalent resistance R2 of the second load element, the base-emitter voltage VBE of the third bipolar transistor, and the threshold voltage VTH of the field-effect transistor is given by 4. The semiconductor logic circuit according to claim 2, wherein: 5. A third load element is inserted between the first load element and the collector of the first bipolar transistor, and a connection point between the first load element and the third load element is connected to the third load element. 5. The semiconductor logic circuit according to claim 2, wherein the semiconductor logic circuit is connected to a base of a third bipolar transistor.