JP3253782B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device such as a DRAM.

[0002]

2. Description of the Related Art Conventionally, magnetic disk devices have been widely used as storage devices for computer systems. However, the magnetic disk drive has a disadvantage that it has a highly precise mechanical drive mechanism and thus is vulnerable to impact, and has a problem that it cannot access at high speed because it accesses the recording medium mechanically.

In recent years, DRAMs have been used as storage devices.
The development of semiconductor storage devices such as the ones described above is underway. The semiconductor memory device has no mechanical drive part, so it is strong against impact,
It has the advantage that high-speed access is possible.

One of the important technologies in a semiconductor memory device such as a DRAM is reduction of noise. DRA
In the case of M, a folded bit line system has conventionally been adopted to reduce noise. A memory cell of this type requires a transfer gate, two gate wirings of a passing word line, and a region through which a bit line passes, and the memory cell has a minimum area of 8F ^2.
(F is the minimum processing dimension). For this reason, when the folded bit line method is applied to the next generation DRAM of 1 GDRAM, the problem of increased cost becomes remarkable.

One of the effective methods for preventing such an increase in cost is to reduce the chip size. More specifically, the layout method without passing word lines in the area of the memory cell area, such as 6F ² or 4F ^2, how to reduce the area of the memory cell has been proposed. However, this method has a problem in that a sense method (open bit line method) having large noise is employed.

Therefore, there is a method in which a bit line is formed in two layers and a sense system equivalent to a folded bit line system is used without increasing the area of a memory cell by using a pair of bit lines in units of two bit lines. Proposed. However,
This method has the following problems.

That is, as shown in FIG. 11, when the number of bit lines is two, there are couplings between the following four types of bit lines. When the amount of charge stored reaches the level of 1 GDRAM, noise increases, and SN increases. There is a problem that the ratio deteriorates.

(1) Coupling between upper bit lines (coupling C ₁ between bit line BL1a and bit line BL2a, coupling C ₁ 'between bit line BL1a and bit line BL3a) (2) Between lower bit lines (Coupling C ₂ between bit line BL 1 b and bit line BL ₂ b, coupling C ₂ ′ between bit line BL 1 b and bit line BL 3 _b ) (3) Coupling between upper bit line and lower bit line of the first type Ring (coupling C ₃ between bit line BL 2 a and bit line BL 1 b) (4) Coupling between upper bit line and lower bit line of the second type (coupling C ₃ ′ between bit line BL 1 a and bit line BL 1 b) To reduce such coupling between bit lines,
By a twist method as shown in the plan view of FIG. 12 (in the figure, a dotted line indicates a lower layer, and a solid line indicates that a bit line runs in an upper layer), for example, noise on the bit line BL1 and bit line BL1 And make the same noise
The noise may be canceled when the signal on the bit line BL1 and the signal on the bit line BL1 are differentially amplified. by this,
Noise caused by the couplings C ₁ , C ₁ , C ₂ , C ₂ ′, and C ₃ can be removed. However, this method has a problem that the bit lines BL1a, BL1b and the like have a complicated twist structure and are difficult to manufacture.

[0009]

As described above, various noise reduction methods have been conventionally proposed.
Since the layer twist structure can reduce noise without increasing the memory cell area, the next generation of highly integrated DRA
Although it was advantageous for M, there was a problem in manufacturing due to the complicated structure.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a bit line type semiconductor memory device capable of reducing noise with a simple structure.

[0011]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises a plurality of paired bit lines consisting of two bit lines and a plurality of paired bit lines intersecting the paired bit lines. A word line, and a memory cell provided at each intersection of the paired bit line and the word line and including a switching MOS transistor and a memory capacitor, wherein the paired bit line has one of the bit lines Are positioned above the other bit line, and the vertical relationship between the two bit lines changes with respect to the longitudinal direction, and the switching MOS transistor has one of a source and a drain below the paired bit line. Connected to a storage node electrode of the memory capacitor, and a plate electrode of the memory capacitor is connected to the storage node electrode of the memory capacitor. Wherein the of being formed between the bit lines.

[0012]

According to the present invention, since the plate electrode of the memory capacitor is formed between the two bit lines constituting the bit line, the coupling between these two bit lines can be cut off. The elimination of the coupling has the same noise reduction effect as that of the two bit lines having a twisted structure. In addition, the structure is simpler than the twist structure. Therefore, noise can be reduced without causing a manufacturing problem. Further, by adding a twist structure to the present invention, noise can be completely eliminated while keeping the memory cell size small.

[0013]

Embodiments will be described below with reference to the drawings. First, the basic concept of the present invention will be described with reference to FIG. In the present invention, instead of adopting the twist structure, the upper bit lines BL1a, BL2a, BL3a,
A structure is employed in which a plate electrode PL of a capacitor exists between lower bit lines BL1b, BL2b, and BL3b. In the figure, bit lines BL1a and BL1
b, bit line BL2a and bit line BL2b, bit line B
L3a and bit line BL3b each constitute a paired bit line. Thus, the couplings C ₃ and C ₄ shown in FIG. 11 can be eliminated, and noise can be reduced.

Here, in the conventional case, five couplings C ₁ , C ₁ ′, C ₂ , C ₂ ′, and C ₃ can be eliminated, whereas in the present invention, _two couplings C ₁ , C ₁ ′, C ₂ ′, C ₃ Coupling C
_Since only ₄ noises can be eliminated, the effect of reducing noise seems to be small at first glance, but the effect of reducing noise per bit line is almost the same.

That is, focusing on the bit line BL1a, as shown in FIG.
₁ , C ₁ ′, C ₃ and C ₄ are present, the coupling C ₄ remains in the case of the conventional method, while the couplings C ₁ and C ₁ ′ remain in the case of the present invention. There is only one coupling.

Further, since the present invention is not a twisted structure but a simple two-layer structure, there is no problem in manufacturing, so that noise can be reduced with a simple structure. FIG. 1 is a diagram showing a basic configuration of the present invention.

The memory cell comprises a memory capacitor (hereinafter simply referred to as a capacitor) C and a switching MOS transistor (hereinafter simply referred to as a MOS transistor) Tr. One source / drain of the MOS transistor Tr is connected to the bit line BL1, and the other source / drain is connected to the plate electrode PL of the capacitor C. The bit line BL1 runs in the upper layer in the adjacent memory cell, while the bit line BL2 runs in the lower layer and is connected to the source / drain (opposite to the capacitor C) of the MOS transistor of the adjacent memory cell. Has been repeated. Here, the bit lines BL1, BL
No. 2 simply runs on the upper layer and the lower layer and has no twist structure.

FIGS. 2 to 6 are diagrams showing the main parts of a DRAM according to a first embodiment of the present invention. FIG. 2 is an equivalent circuit diagram,
3 is a plan view, FIG. 4 is a sectional view taken along the line AA ′ of FIG. 3, FIG. 5 is a sectional view taken along the line BB ′ of FIG. 3, and FIG. 6 is a sectional view taken along the line CC ′ of FIG.

This is a practical configuration of the DRAM of FIG. 1. A selection MOS transistor STr is provided so that there is no problem even if a large number of memory cells are connected to a bit line. As S
It uses GT (Surrounding Gate Transistor).

FIGS. 5 and 6 show MOS transistors Tr.
2 is a cross-sectional view of an SGT cell including a capacitor C and a capacitor C. In the figure, reference numeral 13 denotes a silicon pillar formed by processing the p-type silicon substrate 1. On the silicon pillar 13, an n-type source / drain diffusion layer 15 connected to the storage node electrode 16 is formed. An n-type source / drain diffusion layer 12 connected to the bit line BL0 is formed around the lower portion of the silicon pillar 13.

Two n-type source / drain diffusion layers 12,
The gate insulating film 1 is formed around the silicon pillar 13 between
7 is formed, and a gate electrode 14 connected to the word line WL is formed around the gate insulating film 17.

A plate electrode PL is formed above the storage node electrode 16 with the capacitor insulating film 11 interposed therebetween, and these form a capacitor C. FIG. 4 is a cross-sectional view of the selection MOS transistor STr, and shows an n-type source / drain diffusion layer 2, a silicon pillar 3, a gate electrode 4, an n-type source / drain diffusion layer 5, and a gate insulating film. 7, the SGT having the same structure as the MOS transistor Tr shown in FIGS. 5 and 6 is formed.

FIG. 9 shows how the bit lines BL1 and BL2 are connected to the sense amplifier. In the figure, the solid line indicates that the bit line runs in the upper layer, and the dotted line indicates that the bit line runs in the lower layer.
Both the bit lines BL1 and BL2 are connected to the sense amplifier S / A at a portion running in a lower layer to which the memory cells are connected.

Even in the DRAM having such a structure, the plate electrode PL is provided between the bit line running in the upper layer and the bit line running in the lower layer. Coupling between the upper bit line and the lower bit line can be prevented, and noise can be reduced.

Further, in this embodiment, since the SGT is used as the transistor constituting the memory cell, the line width of the bit line and the word line and the space interval between the bit line and the word line are both set to the minimum processing width F. Therefore, the area of the memory cell can be 4F ² .

FIGS. 7 and 8 are views showing a main part of a DRAM according to a second embodiment of the present invention. FIG. 7 is a plan view and FIG.
FIG. 8 is a sectional view taken along the line DD ′ of FIG. 7. In FIG. 7,
Only the storage node electrode 39 and the contact electrode 33 of the storage node electrode 39 that are necessary for the description are shown.

This is an example in which the present invention is applied to a 6F ² cell size stack type capacitor cell. As shown in FIG. 7, the bit line BL1 is formed at an offset of F / 2 with respect to the element region 30, Contact hole 38 of line BL1
c is eccentric in the direction of the bit line BL1.

Contact hole 3 of contact electrode 33
3c is eccentric in the direction opposite to the bit line BL1, and the contact electrode 33 is further eccentric in the direction opposite to the bit line BL1 with respect to the contact hole 33c.
Located just in the middle between. The storage node electrode 39 is provided on the contact electrode 33 via the contact hole 39c, and the bit line BL2 is disposed between the bit lines BL1.

As shown in FIG. 8, the memory cell is formed in an element region trench-isolated by an insulating film 32, and a MOS transistor has two source / drain diffusion layers 35 and a gate insulating film as usual. 37 and a gate electrode 34. One of the two source / drain diffusion layers 35 is connected to the storage node electrode 39 via the contact electrode 33, and the other is connected to the bit line BL1 via the contact electrode. Also,
The capacitor forming the memory cell includes a storage node electrode 3
9, a capacitor insulating film 36, and a plate electrode PL, and are formed between the bit lines BL1 and BL2.

Also in this embodiment, the coupling between the bit lines BL1 and BL2 is cut off by the plate electrode PL, and the bit lines BL1 and BL2 are also disconnected.
Is a mere two-layer wiring, so that noise can be reduced without causing a manufacturing problem.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the case where the vertical transistor is used for the memory cell has been described, but a planar transistor may be used. Further, any semiconductor device using a bit line other than a DRAM can be applied.

[0032]

As described above in detail, according to the present invention, the coupling between two bit lines constituting a bit line pair can be cut off with a simple structure, which causes a problem in manufacturing. And noise on the bit line can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is an equivalent circuit diagram of a main part of the DRAM according to the first embodiment of the present invention.

FIG. 3 is a plan view of a main part of the DRAM according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view taken along the line AA ′ of the DRAM of FIG. 3;

FIG. 5 is a cross-sectional view of the DRAM of FIG. 3 taken along line BB ';

FIG. 6 is a cross-sectional view taken along the line CC ′ of the DRAM of FIG. 3;

FIG. 7 is a plan view of a main part of a DRAM according to a second embodiment of the present invention.

FIG. 8 is a sectional view taken along the line DD ′ of the DRAM of FIG. 7;

FIG. 9 is a diagram showing how to connect bit lines BL1 and BL2 to a sense amplifier.

FIG. 10 is a diagram for explaining a basic concept of the present invention.

FIG. 11 is a diagram for explaining a conventional problem.

FIG. 12 is a diagram showing a conventional method for reducing coupling between bit lines.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Source / drain diffusion layer 3 ... Silicon pillar 4 ... Gate electrode 5 ... Source / drain diffusion layer 7 ... Gate insulating film 11 ... Capacitor insulating film 12 ... Source / drain diffusion layer 13 ... Silicon pillar 14 ... Gate Electrode 15 Source / drain diffusion layer 16 Storage node electrode 17 Gate insulating film 30 Element region 31 Silicon substrate 32 Insulating film 33 Contact electrode 33 c Contact hole 36 Capacitor insulating film 37 Gate insulating film 38 Contact electrode 39: Storage node electrode 39c: Contact hole

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-77369 (JP, A) JP-A-3-105969 (JP, A) JP-A-1-200662 (JP, A) JP-A-6-2006 349267 (JP, A) JP-A-4-302891 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8242 H01L 27/108

Claims (1)

(57) [Claims] A plurality of paired bit lines comprising two bit lines; a plurality of word lines intersecting the paired bit lines; and a plurality of word lines provided at respective intersections of the paired bit lines and the word lines; A memory cell comprising a switching MOS transistor and a memory capacitor, wherein the paired bit lines are arranged such that one of the bit lines is located above the other bit line, and that
The vertical relationship between the bit lines changes, and one of the source and the drain of the switching MOS transistor is connected to a bit line below the paired bit line, and the other is connected to a storage node electrode of the memory capacitor, A semiconductor memory device, wherein a plate electrode of the memory capacitor is formed between the two bit lines forming the paired bit line.