JP3259116B2 - Pipeline type division processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline type division processing device for performing a pipeline operation using a divider for obtaining a partial quotient of a plurality of bits in one cycle.

[0002]

2. Description of the Related Art Conventionally, this type of pipeline type division processing apparatus can execute only division processing as disclosed in, for example, Japanese Patent Laid-Open No. 1-286023.

FIG. 3 is a diagram showing a configuration of a conventional pipeline type division processing device. This figure shows a case of a six-stage configuration as an example.

Reference numeral 33 denotes a first-stage block, 27 to 31 denote intermediate-stage blocks having the same configuration, and 32 denotes a last-stage block, each of which executes a process for each cycle.

The first-stage block 33 includes a divisor register 1 for storing input divisor data and a dividend register 7 for storing input dividend data.

The intermediate stage block 27 inputs the divisor data and the dividend data stored in the first stage divisor register 1 and the dividend register 7, respectively, and outputs the n-bit divider 19 for obtaining the n-bit partial quotient to the preceding stage divisor register 1. The divisor register 2 for storing the stored divisor data, the dividend register 8 for storing the remainder data of the division result of the n-bit divider 19 as the dividend data of the next stage, and the partial quotient data of the division result for the n-bit divider 19 are stored. The quotient register 13 is provided.

The next intermediate stage block 28 receives the divisor data and the dividend data stored in the divisor register 2 and the dividend register 8 in the preceding stage, respectively, and obtains an n-bit divider 20 for obtaining an n-bit partial quotient. A divisor register 3 for storing the divisor data stored in 2; a dividend register 9 for storing the remainder data of the division result of the n-bit divider 20 as dividend data in the next stage; and an n-bit divider 2
A quotient register 14 is provided for storing partial quotient data resulting from division by 0 and partial quotient data up to the preceding stage.

Similarly, the intermediate stage block 29 includes an n-bit divider 21, a divisor register 4, a dividend register 10, and a quotient register 15, and the intermediate stage block 30 includes an n-bit divider 22, a divisor register 5, a dividend register 11, The intermediate stage block 31 includes a quotient register 16 and an n-bit divider 23, a divisor register 6, a dividend register 12, and a dividend register 17.

The final-stage block 32 includes only the n-bit divider 25 and the quotient register 18, and the partial quotient data of each stage stored in the quotient register 18 is output collectively as the entire quotient data.

Note that pipeline registers are used as the divisor registers 1 to 6, the dividend registers 7 to 12, and the quotient registers 13 to 18, respectively.

Next, the operation will be described. First, when the divisor data and the dividend data are given in the first cycle, the divisor data is stored in the divisor register 1 and the dividend is stored in the dividend register 7. In the next cycle, the divisor data and dividend data stored in the registers 1 and 7 are both n-bit dividers 19
Where the n-bit partial quotient and remainder are obtained. The partial quotient data is stored in the quotient register 13 and the remainder data is stored in the dividend register 8. At this time, the divisor stored in the divisor register 1 is transferred to the divisor register 2.

In the next cycle, the divisor data and the dividend data stored in the registers 2 and 8 are output from the n-bit divider 20.
Where the n-bit partial quotient and remainder are obtained. The partial quotient data is stored in the quotient register 14, and the remainder data is stored in the dividend register 9. At this time, the divisor stored in the divisor register 2 is transferred to the divisor register 3, and the partial quotient stored in the quotient register 13 is transferred to the quotient register 14.

In this manner, a partial quotient of n bits is obtained for each cycle, and the quotient register 18 of the lowermost block 32 is obtained.
, A division result of n bits × 6 stages is input. Thereby, quotient data of n × 6 bits can be obtained.

In FIG. 3, the number of division processing blocks (intermediate stage and final stage blocks) is six and the number of processing bits of the divider is n. By changing the number of processing bits,
A division processing device having a required bit width can be configured.

Incidentally, there is a case where it is desired to perform a pipeline process for simply transferring data in addition to the division process. In this case, a hardware configuration as shown in FIG. 4 is conventionally used.

FIG. 4 is a diagram showing the hardware configuration of the conventional method and the occupation of the hardware. In the figure, the left side 41 shows the conventional division processing device shown in FIG. On the right side, a pipeline register group 42 of the number of stages corresponding to the division processing device 41 is shown. 34 to 40 are pipeline registers, and data is transferred to the register of the next stage every cycle.
Here, the data is divided data A1 to A4 and normal data (mere pipeline transfer data) B1 to B3. The hatched portions in 27 to 40 indicate unused portions of the hardware in one cycle.

That is, in the conventional division processing apparatus as shown in FIG. 3, only a division instruction can be executed, and when there is a pipeline processing other than the division processing, the function can be performed without changing the order of the input / output data. Thus, it is necessary to newly have a pipeline register group corresponding to the division processing device. Therefore, the amount of hardware increases.

Since the division processing unit 41 and the pipeline register group 42 must be synchronized, FIG.
As shown by the diagonal lines, there is an unused portion in the hardware on the pipeline register group 42 side in the case of division data, and in the divider 41 side in the case of normal data. This indicates that the hardware is not being used effectively.

Here, as a prior art, for example,
Japanese Unexamined Patent Publication No. 266628 (hereinafter referred to as prior art) discloses that simultaneous subtraction and multiplication of constants can avoid delays associated with pipeline registers and converters, and can quickly calculate division and square root functions. The disclosed "apparatus and method for calculating division" is disclosed.

[0020]

As described above, the conventional pipeline-type division processing device cannot simply transfer data, and a new pipeline is required to perform such pipeline processing. Since a line register group must be provided, an increase in the amount of hardware is unavoidable. Also, the hardware cannot be used effectively.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has a pipeline type division function which has a division processing function and a pipeline processing function, makes effective use of hardware, and reduces the amount of hardware as a whole. It is an object to provide a processing device.

Here, the above-mentioned prior art shows an apparatus and a method capable of calculating a division and a square root function by a pipeline method. The apparatus and method have both a division processing function and a pipeline processing function, and make effective use of hardware. There is no specific description suggesting the technical idea of the present invention to be realized, and the present invention is based on a technical idea completely different from the present invention.

[0023]

To achieve the above object, the present invention provides a first stage block having a divisor pipeline register for storing divisor data in one cycle and a divisor pipeline register for storing dividend data in one cycle. An n-bit divider for inputting divisor data and dividend data from the first or previous stage to obtain an n-bit partial quotient, a divisor pipeline register for storing divisor data from the first or previous stage, and a portion of the division result of the n-bit divider One or more intermediate-stage blocks including a quotient pipeline register for storing quotient data and partial quotient data up to the previous stage, and a dividend pipeline register for storing remainder data of the division result of the n-bit divider as dividend data of the next stage. And input divisor data and dividend data from the previous stage in one cycle and And a final block having a quotient pipeline register for storing partial quotients of the division result of the n-bit divider and partial quotient data up to the preceding stage and outputting the result as an overall division result. In the pipeline type division processing apparatus provided, the first stage block stores input divisor data in the divisor pipeline register during a division processing cycle, and forcibly stores divisor "1" data in the divisor pipeline register during a transfer processing cycle. It is characterized in that a divisor switching processing unit for storing is provided.

In particular, the divisor switching processing section includes means for generating divisor "1" data, and selectively outputs one of the divisor "1" data and input divisor data generated by this means in accordance with the divisor switching signal. And a selector for deriving
The divisor switching signal is switched between a division processing cycle and a transfer processing cycle, and input divisor data is selected in the division processing cycle and divisor "1" data is selected in the transfer processing cycle.

[0025]

In the pipeline type division processing device having the above configuration, the input divisor data and the divisor "1" data can be selected every cycle in the first-stage block, and the input divisor data is used in the division processing cycle, and in the pipeline processing cycle. By outputting the divisor “1” data, pipeline processing can be executed, and the division processing block that has not been used at the time of the pipeline processing is used as a pipeline register to reduce the necessary hardware amount. ing.

[0026]

An embodiment of the present invention will be described below in detail with reference to the drawings. However, in FIG. 1, the same parts as those in FIG. 3 are denoted by the same reference numerals.

FIG. 1 is a diagram showing a configuration of a pipeline type division processing apparatus according to the present invention, and shows a case of a six-stage configuration as an example.

In FIG. 1, the first-stage block 26 includes a divisor switch control unit 25 together with the divisor register 1 and the dividend register 7. The divisor switching control unit 25 outputs the divisor “1”.
A data generator 251 for generating data; and a selector 252 for selectively deriving one of the divisor "1" data and the input divisor data according to the divisor switching signal. By switching in the processing cycle, input divisor data can be output in the division processing cycle, and divisor "1" data can be output in the transfer processing cycle. The divisor data selected here is stored in the divisor register 1.

FIG. 2 is a diagram showing the occupation of the hardware of the data of the present invention. Here, the data is divided by data A1 to A1.
A4 and normal data (mere pipeline transfer data) B
1 to B3 indicate that the division processing and the pipeline processing are switched every cycle.

Next, the operation of FIG. 1 will be described.

First, the operation of the division processing function will be described. First, a divisor switch signal is sent to the divisor switch controller 25 so that the divisor data input to the divisor register 1 is entered. As a result, the input divisor data is stored in the divisor register 1
The dividend data is stored in the dividend register 7.

In the next cycle, the divisor data and dividend data stored in the registers 1 and 7
The data is input to the bit divider 19, and the n-bit partial quotient and remainder are obtained. The partial quotient data is stored in the quotient register 13 and the remainder data is stored in the dividend register 8. In the next cycle, the intermediate stage block 28 calculates the quotient and remainder of n bits for the divisor data and the dividend data stored in the registers 2 and 8.

In this way, a partial quotient of n bits is obtained for each cycle, and the quotient register 18 of the last block 32 is obtained.
, A division result of n bits × 6 stages is input. Thus, a quotient of n × 6 bits can be obtained.

Next, the operation of the pipeline register function will be described. First, a divisor switch signal is sent to the divisor switch controller 25 so that a value of “1” is input to the divisor register 1. As a result, "1" is forcibly stored in the divisor register 1 as divisor data. The dividend data is stored in the dividend register 7 as dividend data.

In the next cycle, the divisor data “1” stored in the registers 1 and 7 and the transfer data are stored in the intermediate block 2.
7 is input to an n-bit divider 19, and the n-bit partial quotient and remainder are obtained. At this time, since the divisor data is “1”, the quotient data becomes the upper n bits of the data stored in the dividend register 7 and is stored in the register 13.

In the next cycle, the intermediate stage block 2
At 8, a division process is performed using the values stored in the registers 2 and 8 as a divisor and a dividend, and the quotient register 14 stores the value of the quotient register 13 in the preceding stage and n bits from the (n + 1) th bit of the transfer data. Is done.

In this way, the transfer data is divided by "1" every cycle, and the transfer data for n bits is stored in the quotient register of each stage. The quotient register 18 of the last-stage block 32 stores transfer data for n bits × 6 stages. Thereby, it apparently functions as a pipeline register having a quotient of n × 6 bits.

Therefore, the division processing device of the present invention has a division processing function and a pipeline processing function, and as shown in FIG. 2, both functions can be switched for each stage and for each cycle. Can be effectively utilized.

Although the above embodiment has been described in connection with a six-stage configuration, the number of division processing blocks (intermediate and final blocks) is six, and the number of processing bits of the divider is n. The present invention is not limited to this. By changing the number of stages of the division processing block and the number of processing bits of the divider for obtaining the partial quotient, a division processing device having a required bit width can be configured.

As described above, the pipeline type division processing device according to the present invention can have not only the division processing function but also the pipeline processing function by adding a small amount of hardware. Further, since two types of functions, a division processing function and a pipeline processing function, can be switched for each stage and for each cycle, it is not necessary to have the pipeline register group 42 shown in FIG. Further, since the required register bit width can be reduced, the physical quantity can be reduced.

It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications can be made without departing from the spirit of the present invention.

[0042]

As described above, according to the present invention, there is provided a pipeline type division processing apparatus having a division processing function and a pipeline processing function, and utilizing hardware effectively to reduce the amount of hardware as a whole. Can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a pipeline type divider according to one embodiment of the present invention.

FIG. 2 is a diagram showing how data is occupied by hardware according to the embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional pipeline type divider.

FIG. 4 is a diagram showing a hardware configuration of a conventional pipeline type divider and how hardware is occupied.

[Explanation of symbols]

 1 to 6 divisor register 7 to 12 dividend register 13 to 18 quotient register 19 to 24 n-bit divider 25 divisor switching control unit 26 to 33 processing block 34 to 40 pipeline register 41 division processing device 42 pipeline register group

Claims (2)

(57) [Claims] 1. A first-stage block including a divisor pipeline register for storing divisor data and a dividend pipeline register for storing dividend data in one cycle, and inputting divisor data and dividend data from the first stage or the previous stage in one cycle. An n-bit divider for obtaining a partial quotient of bits, a divisor pipeline register for storing divisor data from the first stage or the previous stage, and a quotient pipeline for storing partial quotient data resulting from the division by the n-bit divider and partial quotient data up to the previous stage A register and at least one intermediate stage block provided with a dividend pipeline register for storing remainder data of the division result of the n-bit divider as dividend data of the next stage; and inputting divisor data and dividend data from the previous stage in one cycle. N-bit divider for obtaining an n-bit partial quotient by In a pipeline type division processing device including a partial block having a partial quotient of a division result of a divider and a quotient pipeline register that stores partial quotient data up to a previous stage and outputs the result as an overall division result, the first-stage block includes: A divisor switching processor is provided for storing input divisor data in the divisor pipeline register during a division processing cycle and forcibly storing divisor "1" data in the divisor pipeline register during a transfer processing cycle. Pipeline type division processing device. 2. The divisor switching processing section generates a divisor "1" data, and outputs one of the divisor "1" data and input divisor data generated by the divisor in response to a divisor switching signal. And a selector for selectively deriving the divisor switching signal in a division processing cycle and a transfer processing cycle, so that input divisor data is selected in the division processing cycle and divisor "1" data is selected in the transfer processing cycle. 2. The pipeline type division processing device according to claim 1, wherein: