JP3259265B2 - Method of manufacturing mask ROM of ion implantation program system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a mask ROM of an ion implantation program system for performing a program by ion implantation of impurities.

[0002]

2. Description of the Related Art FIG. 4 shows a first conventional example of a method of manufacturing a mask ROM of an ion implantation program system. In the first conventional example, the SiO ₂ film 12 on the surface of the Si substrate 11 is formed.
To separate the element isolation region, and the SiO ₂ film 13 and the polycrystalline S
A gate oxide film and a gate electrode are formed on the i-film 14, respectively. Then, a diffusion layer 15 as a source / drain is formed, and transistors 16 and 17 for a memory cell and a transistor 18 for a peripheral circuit are formed.

After that, a polycrystalline Si film 14 or the like is
After the contact hole 22 and the like reaching the diffusion layer 15 and the like as the drain are opened in the interlayer film 21, the first layer A
A bit line or the like is formed by the l wiring 23. The transistors 1 other than the transistor 16 to which data is to be written
7 and 18 are covered with a resist 24, and impurities having the same conductivity type as that of the Si substrate 11 are ion-implanted into the channel region of the transistor 16 using the resist 24 as a mask.

As a result, the threshold voltage of the transistor 16 is increased, and the transistor 16 does not operate with the voltage applied to the polycrystalline Si film 14, and the programming is performed. Thereafter, an interlayer film (not shown) covering the Al wiring 23 and the like, a second-layer Al wiring (not shown) and the like are formed to complete the mask ROM.

On the other hand, Japanese Patent Laid-Open No. Hei 4-91470 discloses that
A second conventional example of a method of manufacturing a mask ROM of the ion implantation program system is shown. In the second conventional example, the first
The metal wiring of the layer is covered with an interlayer film, and a through hole for connecting the metal wiring of the first layer and the metal wiring of the second layer is opened in the interlayer film. The portion on the transistor to which data is to be written is removed, and ion implantation for programming is performed using the interlayer film and the first-layer metal wiring as a mask.

[0006]

However, in the first conventional example shown in FIG. 4, a lithography step for patterning the resist 24 is necessary at the time of ion implantation for programming, and the first layer is not used. Al wiring 23
It is necessary to start the program from a state in which the TAT has been formed only up to this point, so the TAT is long.

On the other hand, in the above-mentioned second conventional example, the first-layer metal wiring and the interlayer film covering this metal wiring are used as masks at the time of ion implantation for programming. Patterning as a mask and through-hole opening are simultaneously performed. Further, the program can be started from a state where an interlayer film covering the first-layer metal wiring is formed on the entire surface. Therefore, the TAT is shorter than in the first conventional example. However, shortening the TAT is very important in a mask ROM, and further reduction in the TAT has been demanded.

In both the first and second prior art examples, ion implantation for programming is performed with the entire thickness of the interlayer film 21 covering the polycrystalline Si film 14 and the like remaining in the thickness direction. Therefore, the interlayer film 2 to be penetrated by ion implantation
The film thickness such as 1 is large. For this reason, the variation in the implantation amount of the impurity is large, and the programming cannot be performed reliably.

[0009]

According to a first aspect of the present invention, there is provided a method of manufacturing a mask ROM of an ion implantation program system, wherein a gate electrode of a transistor for a memory cell is covered with a first interlayer film. A first wiring 23 is formed on an interlayer film 21 of the second type, and the first wiring 23 is
5 and forming a through hole 27 reaching the first wiring 23 in the second interlayer film 25,
Removing at least part of the second interlayer film 25 and the first interlayer film 21 in the thickness direction of the gate electrode 14 in all the transistors 16 and 17; 27, the first wiring 2
At the same time as forming the second wiring 31 connected to the transistor 3, a mask layer 32 of the same layer as the second wiring 31 is formed on the gate electrode 14 of the transistor 17 of the transistors 16 and 17 which is not programmed. And a step of ion-implanting a programming impurity 33 using the first and second interlayer films 21 and 25 and the mask layer 32 as a mask.

According to a second aspect of the present invention, in the method of manufacturing a mask ROM of the ion implantation program system, at least the insulating film 35 having an etching rate lower than that of the first and second interlayer films 21 and 25 at the time of the etching for the removal. The method includes a step of forming between the gate electrode 14 and the first interlayer film 21 and a step of performing the etching using the insulating film 35 as a stopper.

[0011]

According to the method of manufacturing a mask ROM of the ion implantation program system of the first aspect, the second wiring 31 and the mask layer 3 are formed.
The program can be started from the state where the conductive film to be made No. 2 is formed on the entire surface.

In the ion implantation for programming, not only the second interlayer film 25 on the gate electrode 14 but also a part of the first interlayer film 21 in the thickness direction is removed. Therefore, the thickness of the interlayer film 21 to be penetrated by ion implantation is smaller than that in the case where only the second interlayer film 25 is removed.

In the ion implantation for programming, a mask layer 32 of the same layer as the second wiring 31 is used as a mask. Since this mask layer 32 is formed simultaneously with the second wiring 31, the mask layer 32 is formed. A lithography step only for forming the layer 32 is unnecessary.

In the method of manufacturing a mask ROM of the ion implantation program system according to the second aspect, the etching rate of the insulating film 35 formed between the gate electrode 14 and the first interlayer film 21 is increased by the first and second interlayer films. 21 and 25, the second and first interlayer films 25 and 2 on the gate electrode 14.
When removing the gate electrode 14 by a simple process,
At least the insulating film 35 can be left with good controllability.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, first and second embodiments of the present invention will be described with reference to FIG.
This will be described with reference to FIGS. In addition, the first shown in FIG.
Components corresponding to those of the conventional example are denoted by the same reference numerals.

1 and 2 show a first embodiment. 1 and 2 correspond to each other at a portion A. In the first embodiment, as shown in FIGS. 1A and 2, a 400 nm thick SiO ₂ film 1 is formed on the surface of a p-type Si substrate 11.
2 is selectively formed by the LOCOS method to divide the element isolation region, and the surface of the element active region surrounded by the SiO ₂ film 12 is thermally oxidized by using the SiO ₂ film 13 having a thickness of 10 nm as a gate oxide film. Formed. Then, a gate electrode is formed on the SiO ₂ films 13 and 12 with a polycrystalline Si film 14 having a thickness of 400 nm.

Thereafter, the polycrystalline Si film 14 and the SiO ₂ film 1
Using n as a mask, impurities are ion-implanted into the Si substrate 11 to form an n-type diffusion layer 15 in the element active region.
Up to this point, transistors 16 and 17 for a memory cell using the diffusion layer 15 as a source / drain and a transistor 18 for a peripheral circuit are completed.

Thereafter, a BPSG film having a thickness of 400 nm is formed as an interlayer film 21 covering the polycrystalline Si film 14 and the like, and a contact hole 22 reaching the diffusion layer 15 and the like as a drain.
And the like are opened in the interlayer film 21. Then, a bit line or the like is formed with the first-layer Al wiring 23, and a 500-nm-thick SiO ₂ film is formed as the interlayer film 25 covering the Al wiring 23 and the like.

Next, as shown in FIG. 1B, the interlayer film 25 is formed.
The resist 26 is patterned on the
Is used as a mask and the interlayer film 25 is etched using the Al wiring 23 as a stopper to open a through hole 27 reaching the Al wiring 23. And this through hole 2
Simultaneously with the opening of the hole 7, the interlayer films 25 and 21 are etched using the resist 26 as a mask, so that one layer is formed on the polycrystalline Si film 14 in the transistors 16 and 17 for all memory cells.
A programming hole 28 leaving only the interlayer film 21 of about 00 nm is opened at least on the polycrystalline Si film 14.

Next, as shown in FIG.
After removing 6, a second-layer Al film is formed on the entire surface.
Then, the Al film is patterned to form a second-layer Al wiring 31 connected to the first-layer Al wiring 23 through the through hole 27, and at the same time, as shown in FIG. An Al layer 32 is formed to cover the programming hole 28 on the polycrystalline Si film 14 in the transistor 17 for the memory cell to which no writing is performed.

Thereafter, boron 33 is ion-implanted over the entire surface under the condition that the peak concentration is located in the channel region of the transistor 16 for the memory cell into which data is to be written. At this time, the programming hole 28 of the transistor 17 is A
The entire thickness of the interlayer films 21 and 25 on the transistor 18 is 900 nm, which is smaller than the thickness of the interlayer film 21 at the bottom of the programming hole 28 of the transistor 16 which is about 100 nm. Because of the thickness, boron 33 is not ion-implanted into the channel regions of the transistors 17 and 18.

As a result, the data is written into only the desired transistor 16 and the program is performed. Thereafter, as shown in FIG. 1D, the second layer A
An interlayer film 34 covering the l wiring 31, the Al layer 32 and the like is formed to complete the mask ROM.

FIG. 3 shows a second embodiment. In the second embodiment, as shown in FIG. 3A, the same steps as in the first embodiment are performed until the diffusion layer 15 is formed, and then the Si ₃ N ₄ film 35 having a thickness of 100 nm is formed. Is formed on the entire surface. Thereafter, as shown in FIGS.
Steps similar to those in the above-described first embodiment are executed again from the formation of 1 to the patterning of the resist 26.

Using the resist 26 as a mask and the Si ₃ N ₄ film 35 as a stopper, the interlayer films 25 and 21 are used.
Is etched to form a program hole 28. At this time, the through holes 27 are formed in the same manner as in the first embodiment.
Are also opened at the same time. Thereafter, as shown in FIGS. 3C and 3D, the same steps as those in the first embodiment are further executed to complete the mask ROM.

Incidentally, in order to leave the interlayer film 21 having a thickness of about 100 nm at the bottom of the program hole 28 in the above-described first embodiment, a method such as time monitoring must be used. However, in such a method, it is difficult to leave the interlayer film 21 with a desired film thickness with good controllability.
The electrical connection between the i film 14 and the Al layer 32 cannot be reliably prevented.

On the other hand, in the second embodiment, since the Si ₃ N ₄ film 35 is used as a stopper when the program hole 28 is opened, at least the Si ₃ N ₄ film 35 is used.
Can be left with good controllability, and the polycrystalline Si film 14 and Al
Electrical connection with the layer 32 can be reliably prevented.

Although the transistors 16 to 18 are n-channel transistors in each of the first and second embodiments, the present invention can be applied to the case where the transistors 16 to 18 are p-channel transistors. it can.

[0028]

According to the method of manufacturing a mask ROM of the ion implantation program system of the first aspect, the program can be started from a state where the second wiring and the conductive film to be the mask layer are formed on the entire surface. The TAT is shorter than in the case where only the second interlayer film, which is the base of the second wiring, is formed.

Further, since the thickness of the interlayer film to be penetrated by the ion implantation is small, the variation in the implantation amount of the impurity is small, and the program can be performed reliably. In addition, since a lithography step only for forming a mask layer is not required, the TAT is also short due to this.

According to a second aspect of the present invention, there is provided a method of manufacturing a mask ROM using an ion implantation program method.
And a simple process for removing the first interlayer film,
Since at least the insulating film can be left on the gate electrode with good controllability, electrical connection between the gate electrode and the mask layer can be reliably prevented.

[Brief description of the drawings]

FIG. 1 is a side sectional view showing a first embodiment of the present invention in the order of steps.

FIG. 2 is a plan view of the mask ROM manufactured in the first embodiment.

FIG. 3 is a side sectional view showing a second embodiment of the present invention in the order of steps.

FIG. 4 is a side sectional view showing a first conventional example of the present invention.

[Explanation of symbols]

14 Polycrystalline Si film 16 Transistor 17 Transistor 21 Interlayer film 23 Al wiring 25 Interlayer film 27 Through hole 31 Al wiring 32 Al layer 33 Boron 35 Si ₃ N ₄ film

Claims (2)

(57) [Claims] 1. A gate electrode of a transistor for a memory cell is covered with a first interlayer film, a first wiring is formed on the first interlayer film, and the first wiring is formed by a second interlayer film. Forming a through hole reaching the first wiring in the second interlayer film, and simultaneously forming the second interlayer film and the first interlayer film on at least the gate electrode in all the transistors. Removing a part in the thickness direction of the first wiring, and forming a second wiring connected to the first wiring via the through hole, and at the same time, Forming a mask layer of the same layer as the second wiring on the gate electrode; and ion-implanting a programming impurity using the first and second interlayer films and the mask layer as a mask. And a method of manufacturing a mask ROM of the ion implantation program system. A step of forming an insulating film having an etching rate lower than that of the first and second interlayer films at least between the gate electrode and the first interlayer film during the etching for removing; 2. The method according to claim 1, further comprising the step of performing the etching using the insulating film as a stopper.