JP3261064B2 - Method of manufacturing flexible circuit board for semiconductor device - Google Patents
Method of manufacturing flexible circuit board for semiconductor deviceInfo
- Publication number
- JP3261064B2 JP3261064B2 JP08877697A JP8877697A JP3261064B2 JP 3261064 B2 JP3261064 B2 JP 3261064B2 JP 08877697 A JP08877697 A JP 08877697A JP 8877697 A JP8877697 A JP 8877697A JP 3261064 B2 JP3261064 B2 JP 3261064B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resin
- circuit board
- flexible circuit
- resin layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Wire Bonding (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明はICチップ等の半導
体装置を回路基板に実装する際にインタ−ポ−ザ−とし
て使用可能な半導体装置用可撓性回路基板の製造法に関
し、特には製造コストが低く、寸法精度の高い量産性に
優れたチップスケ−ルパッケ−ジ又はチップサイズパッ
ケ−ジ(CSP)タイプに採用して好適な半導体装置用
可撓性回路基板の製造法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flexible circuit board for a semiconductor device which can be used as an interposer when a semiconductor device such as an IC chip is mounted on a circuit board. The present invention relates to a method of manufacturing a flexible circuit board for a semiconductor device which is suitable for a chip scale package or a chip size package (CSP) type having a low cost, a high dimensional accuracy, and excellent mass productivity.
【0002】[0002]
【従来の技術】この種のCSPの構造は図3に示すよう
に、ICチップを相手方の回路基板PCBに表面実装す
る場合に、ICチップの接続側に予めインタ−ポ−ザ−
と通称される小型の可撓性回路基板を接続接合してお
き、この可撓性回路基板を介して回路基板PCBに実装
するものがある。2. Description of the Related Art As shown in FIG. 3, this type of CSP has a structure in which, when an IC chip is surface-mounted on a counterpart circuit board PCB, an interposer is previously provided on the connection side of the IC chip.
There is a type in which a small-sized flexible circuit board commonly referred to as “A” is connected and joined, and mounted on a circuit board PCB via the flexible circuit board.
【0003】斯かる半導体装置用可撓性回路基板は、I
Cチップと同等程度か又はそれより僅かに大きめに形成
されたべ−ス用絶縁層20の外面に所要の配線パタ−ン
21を具備し、それら配線パタ−ン21の一方面にはI
Cチップと接続する為の接続用バンプ24を備えると共
に、他方面には回路基板PCBに接続する為の半田バン
プ25を備え、また、配線パタ−ン21の外面の所定領
域は表面絶縁層23で被覆されており、更に、べ−ス用
絶縁層20のICチップ側には接着層22を設けてIC
チップとこの可撓性回路基板とを適宜接合し得るように
構成される。なお、26はICチップの為の封止樹脂層
を示す。[0003] Such a flexible circuit board for a semiconductor device is an I-type flexible circuit board.
A required wiring pattern 21 is provided on the outer surface of the base insulating layer 20 formed to be about the same size as the C chip or slightly larger than the C chip.
A connecting bump 24 for connecting to the C chip is provided, and a solder bump 25 for connecting to the circuit board PCB is provided on the other surface. A predetermined region on the outer surface of the wiring pattern 21 is a surface insulating layer 23. Further, an adhesive layer 22 is provided on the IC chip side of the base insulating layer 20 to form an IC.
It is configured such that the chip and the flexible circuit board can be appropriately joined. Reference numeral 26 denotes a sealing resin layer for an IC chip.
【0004】ここで、べ−ス用絶縁層20及び表面絶縁
層23は、接着剤付き樹脂フィルムをラミネ−トするか
若しくは熱硬化性又は熱可塑性樹脂を塗布・硬化させる
ことにより形成できる。また、接続用バンプ24と半田
バンプ25を形成するに先立ってべ−ス用絶縁層20及
び表面絶縁層23には所要の開口部を形成する。Here, the base insulating layer 20 and the surface insulating layer 23 can be formed by laminating a resin film with an adhesive or by applying and curing a thermosetting or thermoplastic resin. Prior to forming the connection bumps 24 and the solder bumps 25, required openings are formed in the base insulating layer 20 and the surface insulating layer 23.
【0005】このような開口部は、パンチ、ドリルやレ
−ザ−による加工の他、アルカリ等によるウエットエッ
チング手段の加工や樹脂自体に感光性を持つ樹脂のフォ
トリソグラフィ法による加工、更にはプラズマ等を用い
たドライエッチング等の加工技術により形成される。[0005] Such openings are formed by punching, drilling or laser processing, wet etching with alkali or the like, photolithography of resin having photosensitivity to the resin itself, and plasma processing. It is formed by a processing technique such as dry etching using the like.
【0006】[0006]
【発明が解決しようとする課題】ところで、上記の接着
剤付き樹脂フィルムを使用する場合には、パンチ、ドリ
ル、レ−ザ−等の手段によりフィルムに予め所要形状の
上記開口部の為の加工を施す必要があるが、パンチ、ド
リル等の手段では、孔径としては0.3mm程度が実用
上の限界である。また、斯かる手段で得た加工フィルム
をラミネ−トした場合、ラミネ−ト時に加わる熱の影響
により接着剤が溶融して孔底を一部塞ぐという問題があ
る。In the case where the above resin film with an adhesive is used, the film having a required shape is previously formed in the film by means of a punch, a drill, a laser or the like. However, for a means such as a punch or a drill, the practical limit is about 0.3 mm as the hole diameter. Further, when the processed film obtained by such means is laminated, there is a problem that the adhesive melts due to the effect of heat applied at the time of lamination and partially blocks the bottom of the hole.
【0007】更に、貼り合せの際の、孔、スリット等と
配線パタ−ン21との位置精度は、±0.2mm〜±
0.3mmが実用的限界であるので、半導体パッケ−ジ
に使用される例えば配線パタ−ン幅50μm、配線パタ
−ンと孔間精度±10μm等の可撓性回路基板に対して
予め開口部加工されたフィルムをラミネ−トする手法の
適用は極めて困難である。[0007] Further, the positional accuracy of the wiring pattern 21 with the holes, slits and the like at the time of bonding is ± 0.2 mm to ± 0.2 mm.
Since 0.3 mm is a practical limit, an opening is previously formed in a flexible circuit board used for a semiconductor package such as a wiring pattern having a width of 50 μm and an accuracy between the wiring pattern and a hole of ± 10 μm. It is extremely difficult to apply a method of laminating a processed film.
【0008】そこで、孔やスリット等の開口部の形状加
工にNC制御されたレ−ザ−を適用すれば、孔径50μ
m、位置精度±10μm程度で加工性状も良好なものが
得られるが、この手法は加工コストが高く、量産性に乏
しい。Therefore, if a laser controlled by NC is applied to the processing of the shape of the opening such as a hole or a slit, the hole diameter becomes 50 μm.
Although good processing properties can be obtained with m and position accuracy of about ± 10 μm, this method is high in processing cost and poor in mass productivity.
【0009】また、半導体の製造に広く使用されている
液状の感光性樹脂を塗布し、所謂フォトリソグラフィ法
により高精度の所要形状を得ることは可能であるが、斯
かる手法は工程が複雑であり、また、樹脂は感光基を有
するので耐化学薬品性、耐熱性や機械的特性は純粋なフ
ィルムと比較して劣るという問題もある。Although it is possible to apply a liquid photosensitive resin widely used in the manufacture of semiconductors and obtain a required shape with high precision by a so-called photolithography method, the process is complicated. In addition, since the resin has a photosensitive group, there is a problem that chemical resistance, heat resistance and mechanical properties are inferior to those of a pure film.
【0010】本発明はそこで、この種の半導体装置用可
撓性回路基板を製造する際に必要な所要形状の孔やスリ
ット等の開口部を高い位置精度及び寸法精度を確保しな
がら低コスト且つ短時間に加工することにより高品質な
製品を得ることの可能な半導体装置用可撓性回路基板の
製造法を提供するものである。Accordingly, the present invention provides a flexible circuit board for a semiconductor device of this type, which is provided with a hole and a slit having a required shape in a low cost while ensuring high positional accuracy and dimensional accuracy. An object of the present invention is to provide a method of manufacturing a flexible circuit board for a semiconductor device, which can obtain a high-quality product by processing in a short time.
【0011】[0011]
【課題を解決するための手段】その為に本発明による半
導体装置用可撓性回路基板の製造法では、レジスト層と
樹脂層とを一体化した表面絶縁フィルムを用意し、この
表面絶縁フィルムの前記樹脂層側を可撓性回路基板の配
線パタ−ン側に貼り付け、次いで前記レジスト層を所要
のパタ−ン形状に加工し、これにより得られたレジスト
パタ−ンにより前記樹脂層を加工することにより表面絶
縁層を形成することを特徴とするものである。For this purpose, in the method of manufacturing a flexible circuit board for a semiconductor device according to the present invention, a surface insulating film in which a resist layer and a resin layer are integrated is prepared. The resin layer side is adhered to the wiring pattern side of the flexible circuit board, then the resist layer is processed into a required pattern shape, and the resin layer is processed by the obtained resist pattern. Thus, a surface insulating layer is formed.
【0012】このようにして得られた半導体装置用可撓
性回路基板は、半導体パッケ−ジのインタ−ポ−ザ−に
使用できる。そして、前記レジスト層としては光感光性
のものを使用でき、また、前記樹脂層はポリイミド前駆
体の如き半硬化状態の樹脂を用いることができる。The thus obtained flexible circuit board for a semiconductor device can be used as an interposer for a semiconductor package. The resist layer can be made of a photosensitive material, and the resin layer can be made of a semi-cured resin such as a polyimide precursor.
【0013】また、前記の如き表面絶縁層は、この可撓
性回路基板に必要なバンプの形成前か又は後に形成する
ことができる。Further, the surface insulating layer as described above can be formed before or after formation of bumps necessary for the flexible circuit board.
【0014】[0014]
【実施例】以下、図示の実施例を参照しながら本発明を
更に詳述する。先ず図1の(1)〜(10)は本発明の
一実施例による半導体装置用可撓性回路基板の製造工程
図であり、同図(1)のように例えば厚さ18μmの銅
箔等の導電箔1と厚さ25μmのポリイミドフィルム等
の絶縁べ−ス層2からなる片面無接着導電箔張積層板を
用意し、同図(2)の如く導電箔1にエッチング手段で
所要の配線パタ−ン3を形成する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in further detail with reference to the illustrated embodiments. First, FIGS. 1 (1) to 1 (10) are manufacturing process diagrams of a flexible circuit board for a semiconductor device according to one embodiment of the present invention. As shown in FIG. A single-sided non-adhesive conductive foil-clad laminate comprising a conductive foil 1 and an insulating base layer 2 such as a polyimide film having a thickness of 25 μm is prepared, and as shown in FIG. A pattern 3 is formed.
【0015】次いで同図(3)のように、樹脂層4とレ
ジスト層5とを一体化した表面絶縁フィルムを予め用意
し、その樹脂層4側を上記の配線パタ−ン3側に一様に
貼り付ける。ここで、レジスト層5には光感光性のもの
を使用することができ、又、樹脂層4としては、半硬化
状態の各種樹脂、例えばポリイミド樹脂、エポキシ樹脂
又はアクリル樹脂等の電子部品の為に用いられる絶縁樹
脂の前駆体を使用することができる。Next, as shown in FIG. 3C, a surface insulating film in which the resin layer 4 and the resist layer 5 are integrated is prepared in advance, and the resin layer 4 side is uniformly formed on the wiring pattern 3 side. Paste in. Here, a photo-sensitive material can be used for the resist layer 5, and the resin layer 4 is used for electronic components such as various resins in a semi-cured state, for example, a polyimide resin, an epoxy resin, or an acrylic resin. Can be used.
【0016】そこで、同図(4)の如く、レジスト層5
に露光・現像処理を加えて所要形状のを形成し、次いで
同図(5)のように得られたレジストパタ−ン6により
露出した樹脂層4の部位に水酸化カリウム等によるケミ
カルエッチング処理を施してこの樹脂層4に対して所要
のスリット7や開口部8を形成する。Therefore, as shown in FIG.
Then, exposure and development processes are performed to form a desired shape, and then a portion of the resin layer 4 exposed by the resist pattern 6 obtained as shown in FIG. The required slits 7 and openings 8 are formed in the lever resin layer 4.
【0017】次に、同図(6)の如くレジストパタ−ン
6を剥離した後、樹脂層4にキュア処理を加えて硬化さ
せることにより、スリット7、開口部8を形成した表面
絶縁層を形成できる。次いで、同図(7)の如く絶縁べ
−ス層2の外面に熱可塑性のポリイミド樹脂等を塗布・
硬化させて熱可塑性樹脂層9を形成する。Next, as shown in FIG. 6 (6), after the resist pattern 6 is peeled off, a curing treatment is applied to the resin layer 4 to cure the resin layer 4, thereby forming a surface insulating layer in which the slits 7 and the openings 8 are formed. it can. Next, a thermoplastic polyimide resin or the like is applied to the outer surface of the insulating base layer 2 as shown in FIG.
The resin is cured to form the thermoplastic resin layer 9.
【0018】そこで、同図(8)の如く絶縁べ−ス層2
及び熱可塑性樹脂層9の外面側から配線パタ−ン3の所
定箇所に達するバンプ形成用の孔10をレ−ザ−等の手
段で適宜穿設した段階で、同図(9)の如く銅等のメッ
キ手段等で各孔10に導電性部材を充填して所要のバン
プ11を形成する。Therefore, as shown in FIG.
At the stage where a hole 10 for forming a bump reaching a predetermined portion of the wiring pattern 3 from the outer surface side of the thermoplastic resin layer 9 is appropriately formed by means of a laser or the like, as shown in FIG. Each hole 10 is filled with a conductive member by plating means or the like to form a required bump 11.
【0019】そして、一般的には同図(10)のように
配線パタ−ン3の露出面には金等の表面メッキ層12を
形成して製品を得ることができる。Generally, a product can be obtained by forming a surface plating layer 12 of gold or the like on the exposed surface of the wiring pattern 3 as shown in FIG.
【0020】上記のような一連の工程は例えばテ−プキ
ャリア状の上記部材を順次的に繰り出しながら連続的に
各工程を処理し、検査工程後に巻き取って出荷し、ユ−
ザ−側でのICチップの実装後に外形打ち抜き加工を行
うことができる。In the above series of steps, for example, the above members in the form of a tape carrier are sequentially fed out, and each step is continuously processed.
After the IC chip is mounted on the other side, the outer shape punching process can be performed.
【0021】図2の(1)〜(10)は本発明の他の実
施例による半導体装置用可撓性回路基板の製造工程図で
あり、同図(1)のように前記実施例と同様に導電箔1
及び絶縁べ−ス層2からなる片面無接着導電箔張積層板
を用意し、同図(2)の如くその絶縁べ−ス層2の外面
に前記熱可塑性樹脂層9を先ず形成する。FIGS. 2 (1) to (10) are process diagrams of manufacturing a flexible circuit board for a semiconductor device according to another embodiment of the present invention. As shown in FIG. Conductive foil 1
Then, a single-sided non-adhesive conductive foil-clad laminate comprising the insulating base layer 2 is prepared, and the thermoplastic resin layer 9 is first formed on the outer surface of the insulating base layer 2 as shown in FIG.
【0022】そこで、同図(3)のように導電箔1に対
して所要の配線パタ−ン3を形成した段階で、同図
(4)の如く前記と同様に樹脂層4とレジスト層5とを
一体化した表面絶縁フィルムを予め用意し、その樹脂層
4側を上記の配線パタ−ン3側に一様に貼り付ける。Then, at the stage when the required wiring pattern 3 is formed on the conductive foil 1 as shown in FIG. 3 (3), the resin layer 4 and the resist layer 5 are formed in the same manner as described above as shown in FIG. Is prepared in advance, and the resin layer 4 side is uniformly adhered to the wiring pattern 3 side.
【0023】次いで、同図(5)の如く絶縁べ−ス層2
及び熱可塑性樹脂層9の外面側から配線パタ−ン3の所
定箇所に達するバンプ形成用の孔10をレ−ザ−等の手
段で適宜穿設した段階で、同図(6)の如く銅等のメッ
キ手段等で各孔10に導電性部材を充填して所要のバン
プ11を形成する。Next, as shown in FIG.
At the stage where a hole 10 for forming a bump reaching a predetermined portion of the wiring pattern 3 from the outer surface side of the thermoplastic resin layer 9 is appropriately formed by means of a laser or the like, as shown in FIG. Each hole 10 is filled with a conductive member by plating means or the like to form a required bump 11.
【0024】そして、同図(7)の如く前記実施例と同
様にレジスト層5に露光・現像処理を加えて所要形状の
レジストパタ−ン6を形成し、次いで同図(8)のよう
に得られたレジストパタ−ン6により露出した樹脂層4
の部位に前記と同様に水酸化カリウム等によるケミカル
エッチング処理を施してこの樹脂層4に対して所要のス
リット7や開口部8を形成する。Then, as shown in FIG. 7 (7), the resist layer 5 is exposed and developed in the same manner as in the previous embodiment to form a resist pattern 6 of a required shape, and then obtained as shown in FIG. 8 (8). Resin layer 4 exposed by the resist pattern 6
In the same manner as described above, chemical etching treatment with potassium hydroxide or the like is performed to form the required slits 7 and openings 8 in the resin layer 4.
【0025】次に、同図(9)の如く前記実施例と同様
な手法でレジストパタ−ン6を剥離した後、樹脂層4に
キュア処理を加えて硬化させることにより、スリット
7、開口部8を形成した表面絶縁層を形成できるので、
同図(10)のように配線パタ−ン3の露出面に金等の
表面メッキ層12を形成して製品が得られる。Next, as shown in FIG. 9 (9), after the resist pattern 6 is peeled off in the same manner as in the above embodiment, a curing process is applied to the resin layer 4 to cure it, whereby the slit 7 and the opening 8 are formed. Since the surface insulating layer formed with can be formed,
A product is obtained by forming a surface plating layer 12 of gold or the like on the exposed surface of the wiring pattern 3 as shown in FIG.
【0026】[0026]
【発明の効果】本発明によれば、レジスト層をフォトリ
ソグラフィ技術で加工し、これにより得られたパタ−ン
に従って樹脂層を加工することにより表面絶縁層を形成
するので、位置精度及び寸法精度を確保しながら複数個
の製品を一括的に加工することができ、低コスト且つ短
時間での加工が可能である。According to the present invention, the surface layer is formed by processing the resist layer by the photolithography technique and processing the resin layer according to the pattern obtained thereby, so that the positional accuracy and the dimensional accuracy are improved. A plurality of products can be processed at a time while ensuring the above, and processing at low cost and in a short time is possible.
【0027】また、前記樹脂層の加工にケミカルエッチ
ング加工を採用できるので、バリ、開口部やスリットの
壁面の傷又は汚染或いは孔底の導電箔の汚染やダメ−ジ
の無い高品質な孔加工を行える。In addition, since a chemical etching process can be employed for the processing of the resin layer, a high quality hole processing without burrs, scratches or contamination on the wall surfaces of the openings or slits, or contamination or damage to the conductive foil at the bottom of the hole. Can be performed.
【0028】前記樹脂層には各種のポリマ−前駆体を使
用できるので、加工性を向上させながら安全管理を達成
できる。Since various polymer precursors can be used for the resin layer, safety management can be achieved while improving processability.
【0029】前記レジスト層と樹脂層を分離したものを
使用することにより、感光基を有しない純粋な表面絶縁
層を得ることができるので、耐熱性、耐薬品性や耐マイ
グレ−ション性及びアウトガス等に対する信頼性を向上
できる。By using the resist layer and the resin layer separated from each other, a pure surface insulating layer having no photosensitive group can be obtained, so that heat resistance, chemical resistance, migration resistance and outgassing can be obtained. And the like can be improved in reliability.
【0030】本発明による製造法によれば、前記樹脂層
は接着剤層を持たないので、接着剤層と樹脂層からなる
従来の二層構造の表面絶縁フィルムと比較して耐熱性を
好適に上げることができる。According to the production method of the present invention, since the resin layer does not have an adhesive layer, the heat resistance can be suitably improved as compared with a conventional two-layer surface insulating film composed of an adhesive layer and a resin layer. Can be raised.
【図1】(1)〜(10)は本発明の一実施例による半
導体装置用可撓性回路基板の製造工程図。1 (1) to 1 (10) are manufacturing process diagrams of a flexible circuit board for a semiconductor device according to an embodiment of the present invention.
【図2】(1)〜(10)は本発明の他の実施例による
半導体装置用可撓性回路基板の製造工程図。FIGS. 2 (1) to (10) are manufacturing process diagrams of a flexible circuit board for a semiconductor device according to another embodiment of the present invention.
【図3】半導体装置用可撓性回路基板を含むCSPの概
念的な断面構成図。FIG. 3 is a conceptual cross-sectional configuration diagram of a CSP including a flexible circuit board for a semiconductor device.
1 絶縁べ−ス層 2 導電箔 3 配線パタ−ン 4 樹脂層 5 レジスト層 6 レジストパタ−ン 7 スリット 8 開口部 9 熱可塑性樹脂層 10 バンプ形成用孔 11 バンプ 12 表面メッキ層 DESCRIPTION OF SYMBOLS 1 Insulation base layer 2 Conductive foil 3 Wiring pattern 4 Resin layer 5 Resist layer 6 Resist pattern 7 Slit 8 Opening 9 Thermoplastic resin layer 10 Bump forming hole 11 Bump 12 Surface plating layer
Claims (9)
縁フィルムを用意し、この表面絶縁フィルムの前記樹脂
層側を可撓性回路基板の配線パタ−ン側に貼り付け、次
いで前記レジスト層を所要のパタ−ン形状に加工し、こ
れにより得られたレジストパタ−ンにより前記樹脂層を
加工することにより表面絶縁層を形成することを特徴と
する半導体装置用可撓性回路基板の製造法。1. A surface insulating film in which a resist layer and a resin layer are integrated is prepared, and the resin layer side of the surface insulating film is affixed to a wiring pattern side of a flexible circuit board. Manufacturing a flexible circuit board for a semiconductor device, wherein a surface insulating layer is formed by processing the layer into a required pattern shape and processing the resin layer with the resulting resist pattern. Law.
て所要の配線パタ−ンを形成し、レジスト層と樹脂層と
を一体化した表面絶縁フィルムの前記樹脂層側を前記配
線パタ−ン側に貼り付け、次いで前記レジスト層を所要
のパタ−ン形状に加工し、これにより得られたレジスト
パタ−ンにより前記樹脂層を加工することにより表面絶
縁層を形成した後、前記片面無接着導電箔張積層板の絶
縁層側から前記配線パタ−ンの所定箇所に達するバンプ
形成の為の孔を形成し、この孔に導電性部材を充填して
バンプを形成する工程を含む半導体装置用可撓性回路基
板の製造法。2. A required wiring pattern is formed on a conductive foil of a single-sided non-adhesive conductive foil-clad laminate, and the resin layer side of a surface insulating film in which a resist layer and a resin layer are integrated is connected to the wiring. Affixing to the pattern side, then processing the resist layer into a required pattern shape, processing the resin layer with the resulting resist pattern to form a surface insulating layer, A semiconductor comprising a step of forming a bump for reaching a predetermined portion of the wiring pattern from the insulating layer side of the non-adhesive conductive foil-clad laminate to form a bump, and filling the hole with a conductive member to form a bump; A method for manufacturing a flexible circuit board for a device.
光性である請求項1又は2の半導体装置用可撓性回路基
板の製造法。3. The method for manufacturing a flexible circuit board for a semiconductor device according to claim 1, wherein the resist layer of the surface insulating film is photosensitive.
態の樹脂である請求項1〜3のいずれかに記載の半導体
装置用可撓性回路基板の製造法。4. The method for manufacturing a flexible circuit board for a semiconductor device according to claim 1, wherein the resin layer of the surface insulating film is a resin in a semi-cured state.
ド樹脂、エポキシ樹脂又はアクリル樹脂等の電子部品用
絶縁樹脂の前駆体である請求項4の半導体装置用可撓性
回路基板の製造法。5. The method for manufacturing a flexible circuit board for a semiconductor device according to claim 4, wherein the resin layer of the surface insulating film is a precursor of an insulating resin for electronic parts such as a polyimide resin, an epoxy resin or an acrylic resin.
て所要の配線パタ−ンを形成し、レジスト層と樹脂層と
を一体化した表面絶縁フィルムの前記樹脂層側を前記配
線パタ−ン側に貼り付け、次いで前記片面無接着導電箔
張積層板の絶縁層側から前記配線パタ−ンの所定箇所に
達するバンプ形成の為の孔を形成し、この孔に導電性部
材を充填してバンプを形成した後、前記レジスト層を所
要のパタ−ン形状に加工し、これにより得られたレジス
トパタ−ンにより前記樹脂層を加工することにより表面
絶縁層を形成する工程を含む半導体装置用可撓性回路基
板の製造法。6. A required wiring pattern is formed on a conductive foil of a single-sided non-adhesive conductive foil-clad laminate, and the resin layer side of a surface insulating film in which a resist layer and a resin layer are integrated is connected to the wiring. Affixed to the pattern side, and then formed a hole for forming a bump reaching a predetermined portion of the wiring pattern from the insulating layer side of the single-sided non-adhesive conductive foil-clad laminate, and a conductive member was inserted into this hole. A semiconductor including a step of forming a surface insulating layer by processing the resist layer into a required pattern shape after filling and forming a bump, and processing the resin layer with the obtained resist pattern; A method for manufacturing a flexible circuit board for a device.
光性である請求項6の半導体装置用可撓性回路基板の製
造法。7. The method for manufacturing a flexible circuit board for a semiconductor device according to claim 6, wherein the resist layer of the surface insulating film is photosensitive.
態の樹脂である請求項6又は7の半導体装置用可撓性回
路基板の製造法。8. The method according to claim 6, wherein the resin layer of the surface insulating film is a semi-cured resin.
ド樹脂、エポキシ樹脂又はアクリル樹脂等の電子部品用
絶縁樹脂の前駆体である請求項8の半導体装置用可撓性
回路基板の製造法。9. The method of manufacturing a flexible circuit board for a semiconductor device according to claim 8, wherein the resin layer of the surface insulating film is a precursor of an insulating resin for electronic parts such as a polyimide resin, an epoxy resin, or an acrylic resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08877697A JP3261064B2 (en) | 1997-03-24 | 1997-03-24 | Method of manufacturing flexible circuit board for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08877697A JP3261064B2 (en) | 1997-03-24 | 1997-03-24 | Method of manufacturing flexible circuit board for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10270505A JPH10270505A (en) | 1998-10-09 |
| JP3261064B2 true JP3261064B2 (en) | 2002-02-25 |
Family
ID=13952266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP08877697A Expired - Fee Related JP3261064B2 (en) | 1997-03-24 | 1997-03-24 | Method of manufacturing flexible circuit board for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3261064B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000106482A (en) | 1998-07-29 | 2000-04-11 | Sony Chem Corp | Flexible substrate manufacturing method |
| JP2006310689A (en) * | 2005-05-02 | 2006-11-09 | Nippon Mektron Ltd | Manufacturing method of double-access flexible circuit board |
-
1997
- 1997-03-24 JP JP08877697A patent/JP3261064B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10270505A (en) | 1998-10-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100792352B1 (en) | Bottom substrate of package on package and manufacturing method thereof | |
| US7849591B2 (en) | Method of manufacturing a printed wiring board | |
| CN104428892B (en) | Method and apparatus for substrate core layer | |
| US20090301766A1 (en) | Printed circuit board including electronic component embedded therein and method of manufacturing the same | |
| US10002825B2 (en) | Method of fabricating package structure with an embedded electronic component | |
| US20080067666A1 (en) | Circuit board structure with embedded semiconductor chip and method for fabricating the same | |
| JP2001028483A (en) | Wiring board, multilayer wiring board, circuit component mounted body, and method of manufacturing wiring board | |
| JP2009278060A (en) | Printed circuit board and manufacturing method thereof | |
| JP5007164B2 (en) | Multilayer wiring board and multilayer wiring board manufacturing method | |
| JP2009016377A (en) | Multilayer wiring board and multilayer wiring board manufacturing method | |
| KR20220061099A (en) | Circuit board, manufacturing method of circuit board, and electronic device | |
| CN116013870A (en) | Embedded device packaging substrate and manufacturing method thereof | |
| US6582616B2 (en) | Method for preparing ball grid array board | |
| JP3261064B2 (en) | Method of manufacturing flexible circuit board for semiconductor device | |
| US20110083891A1 (en) | Electronic component-embedded printed circuit board and method of manufacturing the same | |
| US20090288861A1 (en) | Circuit board with buried conductive trace formed thereon and method for manufacturing the same | |
| JPH118471A (en) | Method for manufacturing multilayer wiring board, and method for mounting electronic component using multilayer wiring board | |
| KR20030011433A (en) | Manufacturing method for hidden laser via hole of multi-layered printed circuit board | |
| JP3107535B2 (en) | Wiring board, circuit component mounted body, and method of manufacturing wiring board | |
| KR100704911B1 (en) | Electronic printed circuit board and its manufacturing method | |
| CN111863737A (en) | An embedded device packaging substrate and its manufacturing method | |
| KR101119306B1 (en) | Method of manufacturing a circuit board | |
| US11764344B2 (en) | Package structure and manufacturing method thereof | |
| KR20030011434A (en) | Manufacturing method for hidden laser via hole of multi-layered printed circuit board | |
| JP2004014559A (en) | Circuit board, multilayer circuit board, and methods of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081214 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081214 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091214 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101214 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111214 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121214 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121214 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131214 Year of fee payment: 12 |
|
| LAPS | Cancellation because of no payment of annual fees |