JP3263200B2 - Synchronous signal generation circuit and frequency division circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous signal generating circuit and a synchronous signal generating circuit .
It relates to peripheral circuits, and particularly a divided signal a high frequency signal by dividing the synchronization is synchronized with the reference signal signal generation circuit and its
The present invention relates to a frequency dividing circuit used in a synchronous signal generating circuit .

When data is transferred between a plurality of devices, for example, between a disk drive and a disk controller, the frequency of a clock for determining the operation timing of each device is different or the phase of the clock is shifted. Or Therefore, it is necessary to synchronize the clocks of a plurality of devices.

[0003]

2. Description of the Related Art FIG.
A PLL (phase locked loop) type shown in FIG. The voltage controlled oscillator (VCO) 4 outputs a frequency signal fv corresponding to the input voltage. The frequency dividing circuit 20 receives the frequency signal fv and divides the frequency signal fv to obtain a frequency-divided signal fp.
Is output as a synchronization signal. The phase comparator 1 inputs the frequency-divided signal fp and a reference signal fr of a reference frequency which is a clock of another device. The phase comparator 1 compares the two phases and outputs a phase difference signal S1 based on the comparison result.
The charge pump circuit 2 receives the phase difference signal S1 and outputs a voltage signal Do based on the signal S1. The low-pass filter (LPF) 3 receives the voltage signal Do and outputs a smoothed control voltage signal VT to the VCO 4.

By repeatedly performing such an operation, the frequency and phase of the frequency-divided signal fp are finally synchronized with the frequency and phase of the reference signal fr.

[0005]

However, the divided signal f
The time required for p to synchronize with the reference signal fr differs depending on the phase difference and frequency difference between the two. The time required for the synchronization varies depending on the capabilities of the individual synchronization signal generation circuits. However, the smaller the phase difference and the frequency difference between the divided signal fp and the reference signal fr, the more easily the divided signal fp synchronizes with the reference signal fr.

Therefore, in a conventional synchronous signal generating circuit,
At the start of synchronization, an operation has been performed to compare the phases of the reference signal fr and the frequency-divided signal fp to bring the frequency division start point closer to the phase of the reference signal fr.

However, the dividing ratio of the dividing circuit 20 is
The oscillation frequency of the VCO 4 until the start of the synchronization, the design consideration, and the like are set in advance according to the capability of the VCO 4. If the frequency difference between the frequency-divided signal fp and the reference signal fr is large at the start of synchronization, the phase difference becomes large in the next cycle even if the phase difference is small at first, and the effect of controlling the frequency-dividing start point is weakened. I will. Further, when the VCO is built in the chip, the performance may be different between the individual VCOs due to manufacturing variations and the like. Therefore, simply controlling the division start point in consideration of the phase difference between the divided signal and the reference signal has little effect.

The present invention has been made in view of the above circumstances, and has as its object to reduce the time required for synchronization by controlling the frequency division timing and frequency division ratio of a frequency signal of a voltage controlled oscillator. It is in.

[0009]

FIG. 1 is a diagram illustrating the principle of the present invention. The voltage controlled oscillator 4 outputs a frequency signal fv according to the input voltage. The frequency dividing circuit 5 receives the frequency signal fv and outputs a frequency-divided signal fp obtained by dividing the frequency signal fv as a synchronization signal. The phase comparator 1 inputs the frequency-divided signal fp and the reference signal fr of the reference frequency, compares the phases of the two, and outputs a phase difference signal S1 based on the comparison result. The charge pump circuit 2 receives the phase difference signal S1 and outputs a voltage signal Do based on the signal S1. The low-pass filter 3 receives the voltage signal Do and smoothes the voltage signal Do.
T is output to the VCO 4.

The frequency dividing circuit 5 includes a frequency dividing ratio setting circuit 6, a timing setting circuit 7, and a frequency dividing section 8. Dividing ratio setting circuit 6 outputs the number of pulses of the frequency signal fv in one cycle of the criteria signal fr as a frequency division ratio. Timing setting circuit 7 sets the division timing to divide the frequency signal fv based on the criteria signal fr. Frequency divider 8
A frequency based on the frequency dividing ratio and the frequency division timing signal f
Divide v.

[0011]

The frequency of the frequency signal fv in one cycle of the action] standards signal fr is set as the division ratio. Therefore, at the start of synchronization, the frequency-divided signal fp is a signal that is substantially synchronized with the reference signal fr. After that, P
LL, and operates on the divided signal fp with respect to the reference signal fr.
Synchronization is completed in a short time.

[0012]

FIG. 2 shows an embodiment of the present invention.
This will be described with reference to FIG. 1 and 7 for convenience of explanation.
The same components as those described above are denoted by the same reference numerals and described.

FIG. 2 shows a synchronizing signal generation circuit 10 according to this embodiment.
It is shown. The synchronization signal generation circuit 10 includes a phase comparator 1, a charge pump circuit 2, an LPF 3, a VCO 4, and a frequency divider 5.

The VCO 4 has a frequency signal f corresponding to the input voltage.
Output v. The frequency divider 5 receives the frequency signal fv,
A frequency-divided signal fp obtained by dividing the frequency is output as a synchronization signal. The phase comparator 1 inputs the frequency-divided signal fp and a reference signal fr of a reference frequency which is a clock of another device. The phase comparator 1 compares the two phases and outputs a phase difference signal S1 based on the comparison result.

The charge pump circuit 2 receives the phase difference signal S1 and outputs a voltage signal Do based on the signal S1. The LPF 3 includes an integrating circuit having a resistor and a capacitor, and outputs a control voltage signal VT obtained by smoothing the voltage signal Do and removing a high-frequency pulse component to the VCO 4.

FIG. 3 shows the details of the frequency dividing circuit 5. When the lock start signal SL goes high, the frequency division ratio setting circuit 6 counts the pulses of the frequency signal fv in one cycle of the reference signal fr with reference to the immediately following rising edge of the reference signal fr, as shown in FIG. I do. In this count, the frequency signal fv is frequency-divided by two in order to set the duty of the frequency-divided signal fp to 50%. Then, the setting circuit 6 stores the count value as the frequency division ratio of the frequency signal fv, and outputs the frequency division ratio signal DR to the comparison circuit 12. In this embodiment, the count value is α. The setting circuit 6 supplies an enable signal TE to the frequency division timing setting circuit 7.
Is output.

When the enable signal TE goes high, the frequency division timing setting circuit 7 detects the first rising edge of the frequency signal fv and outputs the enable signal CE to the VCO counter 11 constituting the frequency divider 8.

The VCO counter 11 outputs an enable signal CE.
Becomes H level, the counting of the frequency signal fv is started,
The count value SV is output to the comparison circuit 12. Counter 1
1 is reset when an L-level reset signal RST is input from the comparison circuit 12.

The comparison circuit 12 compares the frequency division ratio signal DR and the count value SV at any time, and when they match, the VCO frequency divider 1
3 and an L-level reset signal RST to the counter 11.

When the first rising edge of the frequency signal fv is input when the enable signal DE is at the H level, the VCO frequency divider 13 divides the frequency signal fv and outputs a frequency-divided signal fp.

As a result, as shown in FIG.
Then, a frequency-divided signal fp obtained by dividing the frequency signal fv by the frequency division ratio 2α is output in a state substantially synchronized with the reference signal fr. Thereafter, by performing the operation of the ordinary PLL circuit, the frequency signal fv of the VCO 4 is finally locked to the multiplication of the reference signal fr, and the frequency and phase of the frequency-divided signal fp are changed to those of the reference signal fr. Synchronized.

As shown in FIG. 6, the start point of the frequency division timing may be set based on the point in time when a predetermined number (for example, three) of pulses are counted from the rising edge of the reference signal fr. .

[0023]

As described in detail above, according to the present invention,
By controlling the frequency-dividing timing and frequency-dividing ratio of the frequency signal of the voltage-controlled oscillator, the frequency-divided frequency-divided signal can be output in a state substantially synchronized with the reference signal. Therefore, there is an excellent effect that the time required for synchronization can be shortened.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing one embodiment.

FIG. 3 is a block diagram showing a frequency dividing circuit.

FIG. 4 is an explanatory diagram showing frequency division start timing of a frequency signal with respect to a reference signal.

FIG. 5 is an explanatory diagram illustrating frequency division timing of a frequency signal with respect to a reference signal.

FIG. 6 is an explanatory diagram showing another example of a frequency signal division start timing for a reference signal.

FIG. 7 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 phase comparator 2 charge pump 3 low-pass filter (LPF) 4 voltage-controlled oscillator (VCO) 5 divider 6 divider ratio setting circuit 7 timing setting circuit 8 divider Do voltage signal fp divided signal fr reference signal fv frequency Signal S1 Phase difference signal VT Control voltage signal

Continuation of front page (56) References JP-A-4-262620 (JP, A) JP-A-57-190426 (JP, A) JP-A-5-152950 (JP, A) JP-A-3-86635 (JP) , U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03L 7/18 H03L 7/199

Claims (2)

(57) [Claims] 1. A voltage controlled oscillator for outputting a frequency signal corresponding to an input voltage divider circuit to output a frequency-divides No. signal to said frequency signal by dividing
If, by comparing the phase of the reference signal of the reference frequency and the divided No. ShuShin
A phase comparator for outputting the position No. Osatsushin Te, the phase a charge pump circuits for outputting a voltage No. signal based on No. Sashin, smoothing the control voltage before SL voltage control flights then signals the voltage No. signal < br /> in the synchronization signal generation circuit example Bei a low pass filter for outputting to the exciter, the divider circuit, the path <br/> number pulse of the frequency signal in one cycle of the reference signal frequency division and the division ratio setting circuits for outputting as a ratio, a timing setting circuits which set the division timing to divide the frequency signal based on the reference signal, the said division timing and the frequency division ratio synchronizing signal generating circuit, characterized in that it comprises a frequency divider for dividing the frequency signal based. 2. A reference signal of a reference frequency and an output from an oscillator.
Phase of the divided frequency signal with the divided signal.
Generating a synchronizing signal for controlling the frequency of the frequency signal
A frequency divider used in the circuit, The frequency divider, The frequency signal in one cycle of the reference signal.
A division ratio setting circuit that outputs the number of pulses as a division ratio; Frequency division for dividing the frequency signal based on the reference signal
A timing setting circuit for setting timing; The frequency is determined based on the frequency division ratio and the frequency division timing.
A frequency divider for dividing a number of signals, A frequency dividing circuit comprising: