JP3269733B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a high speed and low power MOS type integrated circuit.

[0002]

2. Description of the Related Art Conventionally, a digital logic LSI generally includes a CMOS circuit in which a P-type MOS transistor and an N-type MOS transistor are paired in order to achieve high integration and low power of the circuit. It is. On the other hand, as a circuit system different from the CMOS configuration,
Complementary Pass-transistor (CPL), which uses many pass transistors, in order to improve the operation speed and achieve high integration.
Logic) circuit is disclosed in "Logic Circuit and Data Processing Device Using It" (JP-A-2-288917).

Here, the circuit having the CMOS structure or C
A case where a full adder is configured by a circuit having a PL configuration will be described. FIG. 2 shows a full adder configured using a CMOS circuit. The full adder 13 shown in FIG. 2 outputs a sum signal 14 and a carry signal 15 for three inputs of input signals A, B, and C. The circuits constituting the full adder are all CMOS circuits in which a PMOS transistor and an NMOS transistor are paired. In the CMOS circuit, since the PMOS transistor and the NMOS transistor do not turn on at the same time, there is no current flowing directly from the power supply to the ground, and the power consumption is small. Therefore, C
MOS circuits are widely used in digital circuits.

FIG. 3 shows a full adder constituted by using a CPL circuit. The full adder 18 shown in FIG. 3 is a sum signal 2 for six inputs of input signals A, AB, B, BB, C, and CB (AB, BB, and CB are inverted signals of A, B, and C, respectively).
0, a sum inverted signal 19, a carry signal 21, and a carry inverted signal 22 are output. Thus, the circuit of the CPL configuration needs a complementary signal. In the CPL circuit, all the parts constituting the logic are constituted only by NMOS transistors, and the PMOS transistor is used only in the part of the latch for pull-up and the output buffer. As described above, most of the circuit can be configured only with NMOS transistors, so that the number of elements can be reduced and the chip area can be reduced as compared with a circuit having a CMOS configuration.
As a feature of the CPL circuit, the speed is higher than that of the CMOS circuit. On the other hand, the power consumption is slightly higher than that of the CMOS circuit.

[0005]

In digital logic LSIs used for portable battery-powered equipment, there is a strong demand for lowering the voltage and lowering the power in order to extend the life of the batteries used. Lowering the voltage of an LSI means that the power supply voltage is 2
There is a great effect in reducing the power that decreases in proportion to the power. However, on the other hand, there arises a problem that the operation speed also decreases.

Therefore, when the LSI used for the portable battery-powered device is constituted by a CMOS circuit as in the past, the power consumption can be reduced by lowering the power supply voltage. However, since the operating speed is greatly reduced due to the decrease in the power supply voltage, there is a possibility that the demand for the operating speed cannot be satisfied.

On the other hand, when the entire circuit is configured using a CPL circuit in order to ensure high speed at low voltage,
Although the operation speed requirement can be satisfied, the power consumption may not be satisfied because the power consumption cannot be reduced as much as a CMOS circuit. This is because the CPL circuit requires complementary input / output signals, so that the number of signal lines is about twice as large as that of the CMOS circuit, and the wiring capacity is increased. Also,
In the CPL circuit configured by the pass transistor, the High level of the signal passing through the pass transistor rises only to a level obtained by subtracting the threshold voltage from the power supply voltage. For this reason, it is used at a low voltage and C
When driving a MOS circuit, delay time and power consumption increase, which is problematic. Also, the high level of the output of the pass transistor
When the h level becomes equal to or lower than the logical threshold value of the driven CMOS circuit, the circuit does not operate normally.

It is an object of the present invention to provide a CMOS circuit and a CP.
It is an object of the present invention to provide a high-speed and low-power multiplier or a signal processing device using the same by utilizing the features of each of the L circuits.

[0009]

In order to solve the above-mentioned problems, in the case where the entire circuit is constituted only by CMOS circuits as in the prior art, it is necessary to increase the gate width of the transistor in order to operate at high speed even at a low voltage. . However, increasing the gate width of the transistor leads to an increase in power consumption, so that the effect of lowering the power by lowering the power supply voltage is reduced. Further, when the entire circuit is constituted by the CPL circuit, high-speed operation can be ensured even at a low voltage, but power consumption cannot be reduced as much as a CMOS circuit. As described above, when only the CMOS circuit or only the CPL circuit is used, it is difficult to simultaneously realize high-speed operation and low power under a low voltage.

Therefore, in the semiconductor device of the present invention for achieving the above object, in the case of the multiplier shown in FIG. 1, the adder array is constituted by using a CPL circuit which can operate at high speed even at a low voltage. Since the adder array occupies about half of the delay time of the entire multiplier, the speeding up of the adder array has a large effect on the speeding up of the entire multiplier. Since the load capacity of the half adder is small, it is suitable to be configured by a CPL circuit. FIG.
Divides the adder array in the signal propagation direction as shown by
By arranging a booth decoder near each adder array, the signal line between the booth decoder and the adder array was shortened. Further, a pull-up latch circuit composed of a PMOS transistor is added to the output portion of the pass transistor circuit, and the H level of the signal passing through the pass transistor is increased.
The high level was raised to the power supply voltage. The circuit configuration of the pull-up latch circuit used here is “Logic circuit and data processing device using the same” (Japanese Patent Laid-Open No. 2-288).
917) states that it works to assist the amplification of the output signal. However, the latch circuit for pull-up in the circuit of the present invention is used in combination with a low-threshold pass transistor to reduce delay time and power consumption at a low voltage and to operate the circuit itself properly. This is essential for operating the circuit at low voltage.

On the other hand, a low-power CMOS circuit is used for a buffer having a large load capacity to be driven and a full-scale detection circuit capable of operating at a lower speed than other parts in the circuit.

As described above, by adopting a circuit configuration in which the features of the CPL circuit and the CMOS circuit can be utilized, a high-speed and low-power circuit can be formed even at a low voltage.

[0013]

As shown in FIG. 1, adder arrays 9 and 11, which occupy a large part of the delay time of the entire multiplier, are constituted by CPL circuits, and buffers 4, 5, 12 and a full-scale detection circuit 6 are provided. By using a CMOS circuit, the delay time can be reduced by about 20% as compared with the conventional case where the entire multiplier is formed by a CMOS circuit.

Further, by dividing the adder array having the CPL structure in the signal propagation direction and disposing a booth decoder in the vicinity, the wiring capacity between the booth decoder and the adder array can be reduced, and the adder array having the CPL structure can be reduced. Can suppress an increase in power consumption due to the use of.

Further, by adding a pull-up latch circuit composed of a PMOS transistor to the output portion of the pass transistor circuit, the High level of the signal passing through the pass transistor is raised to the power supply voltage, and the delay time and power consumption are reduced. Can be smaller. In particular, driving the CMOS circuit at the output terminal of the pass transistor at a low voltage,
When the High level of the output of the pass transistor is equal to or lower than the logical threshold value of the driven CMOS circuit, the normal operation of the circuit is compensated.

[0016]

FIG. 1 shows a first embodiment of the present invention. FIG.
Is a multiplier circuit having the circuit configuration of the present invention. FIG.
Is a circuit configuration in the case of a parallel multiplier using Booth's algorithm, in which a multiplier 1 and a multiplicand 2 are input and a multiplier output 3 is obtained. The circuits constituting the multiplier include a multiplier input buffer 4, a multiplicand input buffer 5, a full scale detection circuit 6 for detecting the maximum value of the input signal, and a multiplicand 2
Is converted to a Booth code, Booth decoders 8 and 10 for calculating a partial product between the signal converted to the Booth code and the multiplier 1, and addition for adding the partial products calculated by the Booth decoders 8 and 10 And an output buffer 12.

Among these circuits, the adder arrays 9 and 11 for which the driving load capacity is small and high-speed operation is required.
Was constituted by a CPL circuit. The shortening of the delay time of the adder array has a great effect on increasing the speed of the entire multiplier because the adder array occupies about half of the delay time of the entire multiplier. Further, when the circuit is constituted by a CPL circuit, the power consumption increases significantly when the load capacity to be driven is large, but the increase in power consumption is hardly a problem because the load capacity to drive the adder array is small. The reason will be described with reference to FIG. FIG. 3 shows a full adder used in the adder array of the multiplier shown in FIG. CP shown in FIG.
The full adder having the L configuration has complementary inputs and outputs and the sum signal 2
0, the inverted sum signal 19, the carry signal 21, and the inverted carry signal 22 are respectively applied to the load capacitors 23, 24, 25, and 26.
Is attached. Therefore, since the number of signal lines is larger than that of the conventional CMOS circuit, power consumption increases when the load capacity of the signal lines is large. However, in the adder array, since the wiring length between the circuits is short and the number of signal lines connected to one output terminal is almost one in most cases, the load capacity is small. Thus, configuring the adder array by the CPL circuit is an effective means for achieving high speed without increasing power consumption.

On the other hand, the input buffer 4 for the multiplier, the input buffer 5 for the multiplicand, the full scale detection circuit 6, the Booth encoder 7, and the output buffer 12 are constituted by using CMOS circuits. Among these, the input buffer 4 for the multiplier, the input buffer 5 for the multiplicand, and the output buffer 12 have large driving load capacities. The full-scale detection circuit 6
Are configured with CMOS circuits that consume less power because each of them can operate at a lower speed than other circuits in the multiplier circuit.

Further, in the circuit of the present invention, in order to reduce the power consumption of the booth decoder connected to the full adder in the adder array, as shown in FIG. Divided into two. In FIG.
A part of a booth decoder of a multiplier and a part of an adder array constructed by using a secondary booth algorithm with 16 × 16 bits will be described. Conventionally, as shown in FIG.
8 are arranged vertically in eight stages, and signal lines 29 and 30 from the booth decoder 27 are connected to the full adder. These signal lines have a long wiring length per full since the full adders 28 are arranged vertically in eight stages. In addition, when the full adder 28 is formed by the CPL circuit, the input signals are complementary. Therefore, the number of the signal lines 29 and 33 is increased about twice as compared with the case where the full adder is formed by the CMOS circuit. Therefore, there is a problem that the wiring capacitance of the signal lines 29 and 30 is large and power consumption increases.

Therefore, in the circuit of the present invention shown in FIG. 1, the Booth decoder and the adder array are divided into two as shown in FIG. FIG. 5 shows the divided Booth decoder and a part of the adder array. FIG. 5 includes booth decoders 31 and 35, signal lines 33, 34, 35 and 36 from the booth decoders, and full adders 32 and 36. Here, the signal lines 33, 34, 3
When the signal lines 5 and 36 are compared with the signal lines 29 and 30 shown in FIG. 4, it can be seen that the signal lines 33, 34, 35 and 36 are shorter. Therefore, the signal line shown in FIG. 5 has a smaller wiring capacitance than the signal line shown in FIG. 4, and the power consumption of the booth decoder can be reduced. Dividing the booth decoder and the adder array in this way minimizes the power consumption that increases by configuring the full adder array with a CPL circuit. Further, by dividing the adder array, the number of channels of signal lines passing through the inside of the full adder can be reduced to about half. As a result, the cells of the full adder can be reduced, and the chip area can be reduced.

Further, when the CPL circuit is used at a low voltage, the High level of the signal passing through the pass transistor is lowered from the power supply voltage by the threshold voltage of the pass transistor, which causes a problem in circuit performance. To solve this problem, a pull-up latch circuit is added to the output of the pass transistor as shown in FIG. 6 in the circuit of the present invention.
FIG. 6 shows a part of a full adder circuit constituted by a CPL circuit. 6, the input signal A39,
Inverted signal 40 of input signal A, input signal B41, inverted signal 42 of input signal B, input signal C43, inverted signal 44 of input signal C, inverted signal 45 of sum signal, sum signal 46, pass transistors 47-54, VCC55 , 56, a latch circuit 57 for pull-up, CMOS inverters 58, 59,
Output terminals 60 and 61 of the pass transistor. Here, the operation waveform of the output terminal 60 or 61 of the pass transistor when the circuit of FIG. 6 is used at a low voltage is shown in FIG.
Shown in

FIG. 7 shows the High level of the signal passing through the pass transistor. The waveform 62 is a waveform when there is a latch circuit 57 for pull-up, and the waveform 63 is a waveform when there is no latch circuit for pull-up. The waveform is shown. When there is no pull-up latch circuit, as shown in FIG. 7, the High level of the signal passing through the pass transistor is greatly reduced. The signal having this lowered level is represented by C shown in FIG.
When input to the MOS inverter 58 or 59, CM
The delay time of the OS inverter 58 or 59 increases. Further, since the PMOS constituting the CMOS inverter is not completely turned off, a through current flows from the power supply to the ground, and power consumption increases. Further, waveform 6 shown in FIG.
When 3 is equal to or less than the logic threshold value of CMOS inverter 58 or 59 in FIG. 6, normal operation of the circuit cannot be expected.

FIG. 8 shows the relationship between the pull-up circuit and the delay time. FIG. 8 shows the result of calculating the delay time of a full adder constituted by using a transistor having a threshold voltage of 0.4 V by computer simulation. As can be seen from the figure, when the pull-up latch circuit is not provided, when the power supply voltage drops to about 2 V or less, which is five times the threshold voltage, the delay time is sharply reduced as compared with the case where the pull-up latch circuit is provided. To increase.

As described above, by using the pull-up latch circuit of the present invention at a low voltage, the delay time and the power consumption can be reduced and the normal operation of the circuit can be compensated.

When a 16 × 16-bit parallel multiplier is formed by using the second-order Booth algorithm according to the circuit configuration of the present invention, the speed is improved by about 20% by forming the adder array by the CPL circuit. I can expect. for that reason,
Even when used at a low voltage, the speed is higher than that of the conventional circuit, and the same performance as the conventional circuit can be achieved even at a lower voltage. In the present embodiment, the parallel type multiplier using the Booth's algorithm has been described. However, the same effect can be obtained even when the circuit configuration of the present invention is used for a multiplier of another system not using the Booth's algorithm. .

FIG. 9 shows a second embodiment of the present invention. FIG.
Is the multiplier 67 and the arithmetic operation circuit 6 of the present invention shown in FIG.
8, 69, a register 70, 71, a memory 72, a control circuit 73, and a signal processing circuit 64 including an internal signal line 74. Here, the operation of the signal processing circuit 64 will be briefly described. The multiplier 67 multiplies the input signal 65 with data stored in the memory 72 after being input. The values calculated by the multiplier 67 are subjected to arithmetic operations such as addition and accumulation by the arithmetic operation circuits 68 and 69 and the registers 70 and 71, and an output signal 66 is obtained. The control circuit 73 includes a multiplier 67 in the signal processing circuit, arithmetic operation circuits 68 and 69, registers 70 and 71, a memory 7
2 is generated, and the signal is transferred to each functional block via the internal signal line 74. By using the circuit of the present invention shown in FIG. 1 as the multiplier 67 of the signal processing circuit 64, a high-speed signal processing circuit can be configured. For example, when the factor determining the operation time of the signal processing circuit 64 is a multiplier, the multiplier 6 having the configuration shown in FIG.
7, the multiplication time can be reduced, and the speed of the entire signal processing circuit 64 can be increased. Although an example of the signal processing circuit is shown in FIG. 9, the operation speed of the signal processing circuit having another circuit configuration can be expected to be improved by the circuit configuration of the present invention.

[0027]

By using the circuit configuration of the present invention,
This has the effect of increasing the speed of the multiplier or a signal processing circuit configured using the multiplier. For example, when a 16-bit × 16-bit parallel multiplier is configured by the circuit configuration of the present invention, the speed can be increased by about 20% as compared with the conventional circuit. Therefore, even when the voltage of the circuit is reduced, high speed can be maintained as compared with the conventional circuit. Even in the case of a signal processing circuit in which the operating speed of the multiplier determines the processing speed of the entire circuit, the use of the multiplier of the present invention as the multiplier used in the signal processing circuit allows about 20% Can be speeded up.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a diagram showing a circuit configuration of a full adder having a CMOS configuration.

FIG. 3 is a diagram showing a circuit configuration of a full adder having a CPL configuration.

FIG. 4 is a diagram showing a part of a Booth decoder and an adder array having a conventional circuit configuration.

FIG. 5 is a diagram showing a part of a Booth decoder and an adder array according to the circuit configuration of the present invention.

FIG. 6 is a diagram showing a part of a full adder according to the circuit configuration of the present invention.

FIG. 7 is a diagram showing operation waveforms of a pass transistor output unit.

FIG. 8 is a diagram illustrating a relationship between a latch circuit for pull-up and a delay time.

FIG. 9 is a diagram showing a second embodiment of the semiconductor device according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Multiplier, 2 ... Multiplicand, 3 ... Multiplier output, 4 ... Multiplier input buffer, 5 ... Multiplicand input buffer, 6 ... Full scale detection circuit, 7 ... Booth encoder, 8 ... Booth decoder, 9 ... Adder array Booth decoder, 11
... Adder array, 12 ... Output buffer, 13 ... CMOS
Full adder of configuration, 14 ... sum signal, 15 ... carry signal, 1
6: load capacity, 17: load capacity, 18: full adder of CPL configuration, 19: inverted signal of sum signal, 20: sum signal, 21
... Carry signal, 22 ... Reverse signal of carry signal, 23 ... Load capacity, 24 ... Load capacity, 25 ... Load capacity, 26 ... Load capacity, 27 ... Booth decoder, 28 ... Full adder, 29 ...
Signal line, 30 ... signal line, 31 ... booth decoder, 32 ...
Full adder, 33 signal line, 34 signal line, 35 booth decoder, 36 full adder, 37 signal line, 38 signal line, 39 input signal A, 40 inverted signal of input signal A,
41: input signal B, 42: inverted signal of input signal B, 43
.. Input signal C, 44... Inverted signal of input signal C, 45... Inverted signal of sum signal, 46... Sum signal, 47... Pass transistor, 48 .. pass transistor, 49. Transistor, 52: pass transistor, 53: pass transistor, 54: pass transistor, 55: VCC56 ... VC
C, 57: Latch circuit for pull-up, 58: CMOS
Inverter, 59: CMOS inverter, 60: Output terminal of pass transistor, 61: Output terminal of pass transistor, 62: Waveform, 63: Waveform, 64: Signal processing circuit,
65 input signal, 66 output signal, 67 multiplier, 68
... arithmetic operation circuit, 69 ... arithmetic operation circuit, 70 ... register, 71 ... register, 72 ... memory, 73 ... control circuit,
74 ... internal signal line.

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Koichi Seki 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory of Hitachi, Ltd. (72) Inventor Kazuo Yano 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Kunito Rikino 3681 Hayano Mobara-shi, Chiba Hitachi Devices Engineering Co., Ltd. (56) References JP-A-4-317221 (JP, A) JP-A-5-167435 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 7/52

Claims (4)

(57) [Claims] An adder array comprising a logic component constituted by pass transistors, a pull-up latch circuit constituted by PMOS transistors, and a CMOS inverter; and a buffer constituted by a CMOS circuit.
A semiconductor device, wherein a circuit including a booth code conversion circuit and an overflow detection circuit has a multiplication function. 2. The semiconductor device according to claim 1, wherein the adder array section is divided in the signal propagation direction, and a partial product generation circuit connected to the divided adder array is arranged near the adder array. Wherein the signal line between the partial product generation circuit and the adder array is shortened. 3. The semiconductor device according to claim 1, wherein when a power supply voltage to be used is operated at a low voltage less than five times a threshold voltage of the pass transistor, a pull-up transistor constituted by a PMOS transistor is provided at an output portion of the pass transistor circuit. A semiconductor device characterized by adding a latch circuit for raising and raising a High level of a signal to a power supply voltage. 4. A semiconductor device comprising any or all of the circuits according to claim 1, 2 and 3, and having a signal processing function.