JP3271685B2 - Patrol type storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a storage device employing a patrol system.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional storage device of this kind.

In FIG. 2, a memory patrol execution instruction circuit 21 instructs execution of a memory patrol in a regular cycle, and a memory patrol address register 22 increments the address by one in the cycle instructed by the memory patrol execution instruction circuit 21. This is an address for memory patrol. On the other hand, the normal address register 23 is a register for storing an address used in a normal processing operation. The address selector 24 selects the address of the normal address register 23 during the normal processing operation, and selects the address of the memory patrol address register 22 during the execution of the memory patrol, and supplies the selected address to the memory 25.

An error detection / correction circuit 26 is a circuit for detecting and correcting an error in data read from the memory 25, and a write instruction circuit 27 is provided for the memory 25 for error-corrected data during memory patrol. Write to
This is a circuit for instructing the memory 25 not to write data for which error correction has been performed during the normal processing operation.

The signal lines 201, 202 and 203 are "0" during normal processing operation and "0" during memory patrol.
As a result, if the signal line 201 is "0", the value of the memory patrol address register 22 is held, and if the signal line 201 is "1", the value of the memory patrol address register 22 is incremented by 1. If "0", the address selector 24 outputs the normal address register 23, and if "1", the memory patrol address register 2
2 is output. If the signal line 203 is “0”, it indicates that the data is read from the memory 25 during the normal processing, and if “1”, it indicates that the data is read during the memory patrol.

Next, a series of operations from correcting a correctable error generated during a normal processing operation by a memory patrol operation to writing the corrected data into a memory will be described.

During the normal processing operation, the signal line 202 becomes "0" and the address selector 24 sets the normal address register 23
Is selected, and the memory 25 is accessed. The data read from the memory 25 has an error, and the error detection and correction circuit 26 detects and corrects the error. The corrected data is output to another unit, but the signal line 203
Is “0”, so that the write instruction circuit 27
5 is suppressed. Therefore, memory 2
The data in 5 remains erroneous.

The memory patrol is executed several times by the memory patrol execution instruction circuit 21, and the memory patrol is executed by the signal line 201 with the value obtained by matching the address of the memory patrol address register 22 by +1 with the address at which the correctable error has occurred. When this operation is performed, data in which a correctable error has occurred is read from the memory 25. The error detection and correction circuit 26 detects and corrects an error. The signal line 203 becomes "1", the write instruction circuit 27 instructs writing to the memory 25, and the corrected data is finally written to the memory 25. When the writing is completed, the signal lines 201, 202, and 203 become "0", and the memory patrol at the address of the correctable error ends.

[0009]

In a storage device employing the above-described conventional patrol system, when a correctable error occurs during a normal processing operation, data error correction is performed, but the corrected data is written to the memory. If the address used in the memory patrol does not match the address of the data in which the correctable error occurred, the data in the memory had a correctable error. Remains. Normally, the memory patrol starts from address 0, and the address obtained by incrementing the previous memory patrol address by the memory patrol execution instruction signal is used. Therefore, if it takes time until the memory patrol address matches the address where the correctable error has occurred, correction is performed. Possible errors could change to uncorrectable errors. Therefore, in order to solve this problem, there is a problem that the cycle in which the memory patrol for all addresses ends is shortened, and the performance of the normal processing must be reduced.

[0010]

The storage device according to the present invention employs a patrol system in which data in a memory is periodically read, the presence or absence of a data error is checked, and if there is an error, the data is corrected and written into the memory again. In the storage device, a memory patrol execution instruction circuit for instructing execution of a memory patrol in a regular cycle, a memory patrol address register for incrementing an address in a cycle designated by the memory patrol execution instruction circuit for a memory patrol, and a normal processing operation A normal address register that stores the address used in the, a correctable error address register group that can store multiple addresses of the data where a correctable error has occurred, and the presence or absence of a correctable error in the data read from the memory. Correctable error, if correctable error exists An output / correction circuit, a correctable error address control circuit for inputting the contents of the normal address register to the correctable error address register when an error is detected by the correctable error detection / correction circuit, A specific period generating circuit that generates a specific period signal several times during execution at all the addresses of the normal cycle, an address of a normal address register in a normal processing operation, and a signal from the specific period generating circuit is set to “0” when a memory patrol is executed. If "", the address of the memory patrol address register; if the signal from the specific cycle generation circuit is "1", a selector for selecting an address selected from the correctable error address register group by the correctable error address control circuit; and a normal processing operation Correctable errors detected during Not written to memory, and having a write instruction circuit correctable errors detected during the memory patrol instructs corrected such that write to memory.

[0011]

FIG. 1 is a block diagram showing one embodiment of the present invention. A memory patrol execution instruction circuit 1, a memory patrol address register 2, a normal address register 3, an address selector 4, a memory 5, an error It comprises a detection / correction circuit 6, a write instruction circuit 7, a correctable error address register group 8, a correctable error address control circuit 9, and a specific cycle generation circuit 10.

The memory patrol execution instruction circuit 1 instructs the execution of the memory patrol in a regular cycle, and sets the signal lines 101, 102 and 103 to "0". The specific cycle generation circuit 10 uses the address selected by the correctable error address control circuit 9 as a memory patrol address at a specific cycle several times while the memory patrol is executed at all addresses of the memory. This is a circuit that generates a signal to instruct (sets the signal line 104 to “1”).

The correctable error address register group 8 is a register group capable of storing a plurality of addresses of data in which a correctable error has occurred during a normal processing operation. , The used address is cleared from the correctable error address register group 8. The correctable error address control circuit 9 is a circuit for controlling the correctable error address register group 8, and after the execution of the memory patrol using the correctable error address is completed until the execution of the memory patrol using the correctable error address again. If the same address where a correctable error has occurred is accessed a plurality of times, the correctable error address register group 8
Is invalidated because it has already been registered, and registration of the same address is suppressed a plurality of times.

When the signal line 105 output from the correctable error address control circuit 9 is "0", it indicates that no correctable error has occurred, and no address is registered in the correctable error address register group 8. Show the thing, "
1 "indicates that an address has been registered. The signal line 106 is an address line for registering an address of a correctable error from the normal address register 3 in the correctable error address register group 8. A line 107 is a signal line indicating that a correctable error exists in the data read from the memory 5, and when "0", no correctable error exists, and when "1", a correctable error exists. Show.

The memory patrol address register 2 increments the address by 1 in the cycle designated by the memory patrol execution designating circuit 1 to provide an address for melody patrol, and the signal of the logical product of the signal lines 104 and 105 is "
When the signal line 101 is "1" at "0", the address is incremented by "1".
For other status values, the address is held.

In the address selector 4, the signal line 102 is "0" in the normal processing operation.
When the memory patrol is executed and the signal of the signal line 102 is “1” and the logical product of the signal lines 104 and 105 is “0”, the address of the memory patrol address register 2 is selected and “1” is selected. If so, the correctable error address control circuit 9 selects an address selected from the correctable error address register group 8. Signal line 10
Even if 2 is “1” and the signal line 104 is “1”, if the address is not registered in the correctable error address register group 8, the signal line 105 becomes “0” and the address of the memory patrol address register 2 is changed. select.

Now, in the present storage device adopting the patrol system having such a configuration, a series of operations from correcting a correctable error occurring during a normal processing operation by a memory patrol operation to writing into a memory is described. explain.

During normal processing operation, signal lines 102 and 104
Becomes "0", the address selector 4 selects the address from the normal address register 3 and accesses the memory 5. The data read from the memory has a correctable error, which is detected by the error detection / correction circuit 6,
Make corrections. At this time, the signal line 107 becomes "1", and the correctable error address control circuit 9 registers the correctable error address sent to the signal line 106 from the normal address register 3 in the correctable error address register group. When the correction is completed, the signal line 107 becomes "0" and the signal line 10
5 becomes "1".

The corrected data is output to another unit. However, since the signal line 103 is "0", writing of the corrected data to the memory is suppressed by the write instruction circuit 7. When the memory patrol is executed several times by the memory patrol execution instructing circuit 1 and the signal line 104 from the specific cycle generating circuit 10 becomes “1”, and the memory patrol is instructed during the specific cycle, the signal lines 104 and 105 The ANDed signal becomes "1", the signal line 102 becomes "1", and the address selector 4 selects an address selected from the correctable error address register group 8 by the correctable error address control circuit 9 to generate a correctable error. Memory patrol is performed using the address of the data. in this case,
The signal obtained by ANDing the signal lines 104 and 105 is “1”.
Therefore, the value of the memory patrol address register 2 is held. The read data is error-corrected by the error detection / correction circuit 6, and the signal line 103 is "1". Therefore, the write instruction circuit 7 instructs writing of the corrected data to the memory.

At the time when the memory patrol using the address of the data in which the correctable error has occurred ends, the used address becomes the correctable error address register group 8.
Cleared from. The signal lines 102, 103, and 104 become "0" because the memory patrol using the correctable error address has been completed. The signal line 105 is “0” unless another correctable error address is registered.
Becomes

When the signal patrol is "1", a memory patrol is instructed. Since no correctable error has occurred before that, if the signal line 105 is "0", the address selector 4 sets the memory patrol address register 2 And the memory patrol is performed.

As described above, the error correction data can be written into the memory relatively quickly as compared with the prior art.

[0023]

According to the present invention, an address in which a correctable error has occurred is used as a memory patrol address in a specific cycle a plurality of times while the memory patrol is executed for all addresses in the memory. The writing can be performed relatively quickly as compared with the case where the correction writing is performed on the memory only by the memory patrol. As a result, a reliable structure as a storage device becomes possible. Also, the time until the memory patrol is executed up to the last address does not increase much as compared with the conventional example, so that the performance of the normal processing does not decrease.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional example.

[Explanation of symbols]

 1, 21 memory patrol execution instruction circuit 2, 22 memory patrol address register 3, 23 normal address register 4, 24 address selector 5, 25 memory 6, 26 error detection / correction circuit 7, 27 write instruction circuit 8, correctable error address register Group 9 Correctable error address control circuit 10 Specific cycle generation circuit.

Continuation of the front page (56) References JP-A-61-290556 (JP, A) JP-A-6-67989 (JP, A) JP-A-6-324492 (JP, A) JP-A-7-122087 (JP) , A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 12/16 G06F 11/10

Claims (1)

(57) [Claims] In a storage device adopting a patrol method, data in a memory is periodically read, the presence or absence of an error in the data is checked, and if there is an error, the data is rewritten into the memory. A memory patrol execution instruction circuit for instructing execution, a memory patrol address register for incrementing an address in a cycle designated by the memory patrol execution instruction circuit for memory patrol, and a normal address register for storing an address used in a normal processing operation. A group of correctable error address registers that can store multiple addresses of data where a correctable error has occurred, and a correction that detects the presence or absence of a correctable error in the data read from the memory and corrects if there is a correctable error. A correctable error detection / correction circuit; When an error is detected by the error detection / correction circuit, a correctable error address control circuit that inputs the contents of the normal address register at that time to the correctable error address register, and a memory patrol is performed at all addresses of the memory. A specific cycle generating circuit that generates a specific cycle signal several times; an address of a normal address register in a normal processing operation; an address of a memory patrol address register if a signal from the specific cycle generating circuit is “0” during execution of a memory patrol; If the signal from the specific cycle generation circuit is "1", a selector for selecting an address selected from the group of correctable error address registers by the correctable error address control circuit, and a correctable error detected during a normal processing operation is corrected. Is written but not written to memory. Storage apparatus employing the patrol method characterized by having a write instruction circuit correctable errors detected during trawl instructs corrected such that write to memory.