JP3271982B2 - Field effect transistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a field effect transistor, and more particularly to an integrated circuit field effect transistor capable of generating a high current and having a low leakage current.

BACKGROUND OF THE INVENTION Field effect transistors (FETs) are the primary active devices for large scale integrated (VLSI) and very large scale integrated (ULSI) applications such as logic devices, memory devices and microprocessors. The reason is that integrated circuit FETs are inherently high impedance, high density, low power devices. Accordingly, much research and development has been done to improve the operating speed and integration density of FETs and reduce their power consumption.

Albert W.Vinal is a high-speed, high-performance field-effect transistor
Nos. 4,984,043 and 4,990,974 both disclose under the title "Fermi Threshold Field Effect Transistor". These patents describe metal oxide semiconductor field effect transistors (MOSFETs) that operate in enhanced mode without requiring inversion by setting the threshold voltage of the device to twice the Fermi potential of the semiconductor material. . As is known to those skilled in the art, the Fermi potential is defined as a state in which the energy state of the semiconductor material has a half probability of being occupied by electrons. If the threshold voltage is set to twice the Fermi potential, as described in the aforementioned U.S. patent, the oxide thickness, the channel length, the drain voltage and the threshold voltage to the substrate doping are reduced. Dependencies are largely eliminated. Furthermore, when the threshold voltage is set to twice the Fermi potential, the electric field in the vertical direction on the substrate surface between the oxide and the channel is minimized,
In practice, it is almost zero. For this reason, the carrier mobility of the channel is maximized, and a high-speed device in which the hot electron effect is significantly reduced can be obtained. Thus, the performance of the device has little to do with the dimensions of the device.

Despite significant improvements in the Fermi threshold FET compared to known FET devices, the capacitance of the Fermi FET device needed to be reduced. Therefore, both are "Fermi threshold field effect transistors with reduced gate and diffusion capacitance"
Nos. 07 / 826,939 (U.S. Pat. No. 5,194,923) and 07 / 977,698 by Albert W. Vinal, which are disclosed under the title of U.S. Pat.
A Fermi-FET device is described in which a conductive carrier flows into a channel at a predetermined depth of a substrate below a gate without having to form an inversion layer on the surface of a semiconductor device. Therefore, the average depth of the channel charge must include the dielectric constant of the substrate as part of the gate capacitance. This significantly reduces the gate capacitance.

As described in the above-mentioned patents and patent applications, the low-capacity Fermi-FET has a conductivity type opposite to the conductivity type of the substrate, and a Fermi-tub region of a predetermined depth having the same conductivity type as the drain and the source. Can be suitably realized. The Fermi-tub extends downward from the substrate surface by a predetermined depth and forms source and drain diffusion regions within the tab boundaries of the Fermi-tub. The Fermi-tub forms a uni-junction transistor in which the source, drain, channel and Fermi-tub are all doped with the same conductivity type but have different doping concentrations. This is the low capacity Fermi FE
T can be provided. In the present invention, a low-capacity Fermi-FET including a Fermi-tub is referred to as a “low-capacity Fermi-FET” or “tab FET”.

Despite significant improvements in Fermi-FETs and low-capacitance Fermi-FETs compared to known FET devices, there is a need to increase the saturation current per unit channel width produced by Fermi-FET devices. The higher the current of Fermi-FET devices, the higher the integration density of logic devices, memory devices, microprocessors and other integrated circuit devices,
And / or higher operating speeds.
However, saturation current need not be obtained at the expense of high leakage current. Higher leakage currents significantly increase the wasteful power consumption of the device. Finally, as portable and laptop computers become more prevalent,
There is a need to lower the threshold voltage of Fermi-FET transistors without adversely affecting operation. Devices with lower threshold voltages can operate better with 3V or lower supply power, which is often used in portable devices and other energy consuming devices.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved Fermi threshold field effect transistor (Fermi FET).

Another object of the present invention is to provide a Fermi-FET capable of generating a very high current per unit channel width.

It is still another object of the present invention to provide a Fermi-FET capable of generating a very low leakage current and a very high current per unit channel width.

According to the present invention, the source and drain regions are doped, and the predetermined concentration of the second conductivity type facing the channel is made sufficiently high to maximize the saturation current of the Fermi-FET. Source/
The accumulated free charge at the drain channel interface is
It is clear to control the amount of saturation current of the FET. Thus, the present invention provides a predetermined minimum doping concentration of the source and drain opposite the channel and maximizes the saturation current of the field effect transistor. Doping beyond this predetermined concentration does not significantly increase the saturation current of the field effect transistor. The predetermined concentration Ndo _min of the source and / or drain that minimizes the saturation current is expressed by the following equation.

Where e _S is the dielectric constant of the substrate φ _X is the flat band voltage between source / drain diffusion doping and channel doping q is 1.6 × 10 ^-19 coulomb e _i is the dielectric constant of the gate insulator L ₀ is the channel length V _gmax is the maximum gate voltage V _t is the threshold voltage Y _f depth T _ox of the Fermi channel adjacent to the source and drain regions are flow depth excess carriers in the channel δ the thickness of the insulator.

A source doping gradient region and preferably a drain doping gradient region are also provided between the source region and the channel and between the drain region and the channel, respectively. These doping gradient regions are doped with a doping gradient that decreases from a source / drain doping concentration adjacent to the source / drain regions to a channel doping concentration adjacent to the channel. Preferably, these source / drain doping gradient regions respectively surround the source and drain regions.

In order to maintain the high saturation current described above, the thickness of the source and drain doping gradient regions should be at least 300 μm.
And make sure you need to. In order to maintain the high saturation current described above, it is preferable to extend the gate insulating layer and the gate electrode beyond the source / drain doping gradient region. Finally, the substrate doping concentration is preferably at least four times the tab doping concentration, which adversely affects the tub depth and the criteria required for doping to minimize the substrate doping concentration and eliminate the electric field perpendicular to the Fermi channel. Not to be.

According to the Fermi-FET of the present invention, the saturation current can be increased without significantly increasing the leakage current. For example, a Fermi-FET with a gate insulator thickness of less than 120 ° and a channel length of about 1 μm or less, using a power supply of 0-5 V, a leakage current of less than 10 pAmp / μm, and a P-channel saturation of at least 4 amp / cm. Current and at least 7
An N-channel saturation current of amp / cm can be provided.
This performance cannot be achieved by conventional surface-channel or buried-channel MOSFETs that generate a sufficient electrostatic field in the channel perpendicular to the substrate surface.

Furthermore, according to the present invention, the threshold voltage of the Fermi FET is
Maintain a given channel depth preferably at approximately 600 ° and increase the channel doping concentration to lower the threshold voltage to less than half the Fermi potential, thereby keeping the electrostatic field of the channel perpendicular to the substrate at zero However, it can be reduced to twice or less the Fermi potential of the substrate. Channel doping can obtain a desired threshold voltage according to at least the following equation.

Where ΔV _T is the threshold voltage change from twice the Fermi potential of the substrate q is 1.6 × 10 ^-19 coulomb T _ox is the thickness of the oxide insulator N _ch is the impurity concentration of the channel Y _f is the source and drain The depth e _s of the Fermi channel adjacent to the region is the permittivity e _{i of the} substrate and the permittivity of the gate insulator.

This channel concentration is maintained at about 5 × 10 ¹⁶ or less to prevent the carrier mobility from decreasing, thereby reducing the saturation current.

According to the above example of the present invention, it can be used in combination with independently controlled saturation current and threshold voltage to obtain Fermi FETs. In particular, it is possible to independently control the maximum saturation current of the device by varying the source / drain doping concentration for a given channel depth of preferably 600 ° and to vary the channel doping concentration to increase the threshold voltage of the device. It can also be controlled independently. Thus, the saturation current and the threshold voltage of the Fermi-FET can be controlled independently.

As described above, according to the high-current Fermi-FET of the present invention, when the channel length is 1 μm or less, the thickness of the gate insulating layer is approximately 120 °, and the channel width is 10 pamp / μm or less, at least the channel width ( 4 amp/c of P channel)
It is possible to generate a drain saturation current of 7 amp / cm of m and channel width (N channel). These values cannot be achieved with conventional MOSFETs where the electric field is oriented perpendicular to the direction of channel carrier flow. Fermi FET
As can be seen from a detailed comparison between the conventional MOSFET and the conventional MOSFET, the saturation velocity is a vector amount generated by an electric field parallel to the substrate in the carrier flowing direction and an electric field perpendicular to the substrate and perpendicular to the carrier flowing direction. Fermi FE
To remove the vertical (orthogonal) component by T,
The saturation current becomes maximum as compared with the conventional MOSFET. Traditional
MOSFETs cannot increase saturation current without making leakage current unacceptably high. This Fermi-FET makes it possible to obtain a Fermi-FET transistor having a high saturation current and a low leakage current.

Further in accordance with the present invention, a Fermi-FET includes a Fermi-tub region adjacent to the source region and facing the drain region and an injector region of the same conductivity type as the source region. The injector region is preferably doped at a doping level intermediate the relatively low doping concentration of the Fermi-tub region and the relatively high doping concentration of the source region. The injector region controls the depth of the carriers injected into the channel and allows the carriers to be injected into the channel at a predetermined depth below the gate.

The source injector area is preferably a source injector tab area surrounding the source area. In other words, it is preferable that the source injector tub region is formed in the Fermi-tub region and the source region is formed in the source injector tub region. Similarly, the drain injector tub region is preferably formed in the Fermi-tub region, and the drain region is preferably formed in the drain injector tub region. Further, the source region and the drain region can extend deeper than the source injector tub region and the drain injector tub region, respectively, in the substrate. The source and drain injector tub regions are preferably of the same conductivity type as the source, drain, and Fermi-tub regions, and are preferably doped at an intermediate concentration between the Fermi-tub, source, and drain regions. It is.

Further, according to the present invention, a pinch-off voltage is reduced and a saturation current is increased by providing a gate sidewall spacer extending from a portion adjacent to a source injector region of a Fermi FET to a portion adjacent to a gate electrode. Can be. This gate sidewall spacer preferably comprises an insulator having a dielectric constant greater than the dielectric constant of the gate insulating layer. For example, in a typical field-effect transistor in which the gate insulator is silicon dioxide, it is preferable that the gate spacer be silicon nitride. Preferably, the gate sidewall spacer extends from a portion adjacent to the drain injector region to a portion adjacent to the gate electrode. Typically, the gate sidewall spacer surrounds the gate electrode.

It is preferable to provide a polycrystalline silicon (polysilicon) layer formed on the gate insulating layer and a conductive layer such as a metal on the polysilicon layer for the gate electrode of the Fermi FET. The polysilicon layer is preferably of a different conductivity type from the source, drain and tub regions of the Fermi-FET. Gate sidewall spacers extend from the sidewalls of the polysilicon layer over the source and drain injector tub regions. The gate sidewall spacer lowers the pinch-off voltage of the device and increases the saturation current of the device.

These source and drain injector regions are used in a tub-FET structure to form a high current Fermi-FET device.
These source and drain injector regions are used in combination with gate sidewall spacers to form a high current device with a low pinch-off voltage.

When fabricating short channel FETs, eg, FETs having a channel length of approximately 0.5 μm, the drain field ending in the source depletion region increases the base leakage current and causes drain induced injection. According to another embodiment of the present invention, the base leakage current is reduced by extending the source and drain injector regions to the depth of the Fermi-tub region. Alternatively, a base leakage current control region of the same conductivity type as the substrate may be provided.

The base leakage control region is heavily doped into the substrate and extends across the substrate from an extension of the opposite end of the source and drain regions and to both sides of the Fermi-tub / substrate implant. As a result, a high-current, short-channel device having a low pinch-off voltage and a low leakage current can be obtained.

It is also easy to use a base leakage current region or an extended injector region for a tub-FET with a channel length longer than approximately 0.5 μm. Further, a base leakage current control region can be used for a tub-FET that does not include an injector region.

Further, the Fermi-tub depth is preferably defined between a maximum tab depth and a minimum tab depth. In particular, the Fermi-tub region can be completely depleted by the substrate-tub junction at the threshold voltage of the field effect transistor by making the Fermi-tub depth sufficiently deep. It is also possible to form a closed inversion injection barrier between the source region and the drain region at a voltage equal to or lower than the threshold value. Therefore, a high saturation current and a low leakage current can be obtained at the same time.

In particular, the present invention field effect transistor temperature T ° Kelvin permittivity e _s and Fermi while being doped with a first doping concentration N _sub - comprises a first conductivity type semiconductor substrate having a potential e _f. A Fermi-tub region of the second conductivity type is formed on the surface of the substrate and has a second concentration α times the concentration N _sub .
Doping is performed at a doping concentration of N _tub . The source and drain regions of the second conductivity type that are separated from each other are formed in the Fermi-tub region on the substrate surface. A gate insulating layer is formed between the spaced apart source and drain regions on the surface of the substrate. The source, drain and gate electrodes are electrically connected to the source and drain regions and the gate insulating layer, respectively.

According to the present invention, the Fermi - the tab region is extended from the surface into the substrate to a point of a predetermined depth, the time predetermined depth _{(2e s φ s N sub /} qN tub (N tub + N sub)) 1 ^{/ 2} and shallower than (2e _s V _t / qN _tub ) ^1/2 where q is
1.6 × 10 ^-19 coulombs, V _t is the threshold voltage of the Fermi FET, phi
_s is 2φ _f + (KT / q) 1nα, and K is 1.38 × 10 ⁻²³ Joules / ゜ Kelvin. By defining the Fermi-tub between the minimum depth and the maximum depth, a high saturation current, low leakage current Fermi FET can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described in detail hereinafter with reference to the accompanying drawings, which show a preferred embodiment of the invention. However, the present invention is not limited to the embodiments described below, and various modifications and changes can be made without changing the gist. Further, in the drawings, the same portions are denoted by the same reference numerals, and the thicknesses of the layers and regions are enlarged for convenience of explanation.

Prior to describing the high saturation current low leakage current Fermi threshold field effect transistor of the present invention, U.S. patent application Ser.
The reduced gate and diffused capacitance Fermi threshold field effect transistors disclosed in 07 / 826,939 and 07 / 977,689 (named "Low Capacitance Fermi-FET" and "Tab-FET" respectively) are described. See the above-cited U.S. patent application for a more complete description.

After describing the low-capacity Fermi-FET, a Fermi-FET having an injector region, a gate sidewall spacer region, and a base leakage control region will be described.

Next, the control of the saturation current by controlling the doping of the source / drain diffusion facing the channel will be described. Thereafter, control of the threshold voltage will be described.
Furthermore, a conventional MOSFET and a Fermi-FET are theoretically compared, and it is explained that the conventional MOSFET cannot combine the high saturation current and the low leakage current of the Fermi-FET as desired.

Fermi-FET with reduced gate and diffusion capacitance A low-capacity Fermi-FET with Fermi-tab is outlined below. Additional details at this time can be found in US patent application Ser.
See / 826,939 and 07 / 977,689.

Conventional MOSFET devices require that an inversion layer be formed on the surface of the semiconductor to support carrier conduction. The inversion layer typically has a depth of 100 ° or less. Under these circumstances, the gate capacitance is essentially the dielectric constant of the gate insulator divided by its thickness. In other words, the channel charge is confined near the surface where the effect of the dielectric properties of the substrate is not as important in determining the gate capacitance.

The conduction carriers are confined in the channel region below the gate so that the gate capacitance can be reduced if the average depth of the channel charge needs to include the dielectric constant of the substrate to calculate the gate capacitance. Become.

In general, the gate capacitance of a low-capacitance Fermi-FET can be expressed by the following equation.

Here, Y _f is the depth of a conduction channel called a Fermi channel, e _s is the dielectric constant of the substrate, and β is a factor that determines the average depth of charge flowing in the Fermi channel below the surface.

This β depends on the depth depending on the profile injected into the channel from the source. Β = 2 for low capacitance Fermi FETs. T _ox is the thickness of the gate oxide layer and e _i is its dielectric constant.

The low-capacitance Fermi-FET comprises a Fermi-tub region of a predetermined depth having a conductivity type opposite to that of the substrate and having the same conductivity type as the source and drain regions. The Fermi-tub extends a predetermined depth below the substrate surface, and drain and source diffusions form in the Fermi-tub region within the Fermi-tub boundary. Suitable Fermi depth is the depth of the sum of the Fermi channel depth Y _f and depletion depth Y _o. A Fermi channel region having a predetermined depth _Tf and width Z extends between the source and drain diffusions. The conductivity type of the Fermi channel is controlled by a voltage supplied to the gate electrode.

The gate capacitance is mainly determined by the depth of the Fermi channel and the carrier distribution of the Fermi channel, and is almost independent of the thickness of the gate oxide layer. The diffusion capacitance is inversely proportional to the difference between the sum of the depth of the Fermi-tub and the depth of the depletion layer of the substrate and the depth _Xd of the diffusion portion. Preferably, the depth of the diffusion is the same as the depth of the Fermi channel. In a deeper configuration, the depth of the diffusion is less than the depth Y _tub of the Fermi- _tub . The dopant concentration in the Fermi-tub region is preferably selected so that the depth of the Fermi channel is at least three times the depth of the inversion layer in the MOSFET.

Therefore, the low-capacitance Fermi FET has the first surface having the first surface.
A conductive type semiconductor substrate; a second conductive type Fermi-tub region on a first surface within the semiconductor substrate; and a second conductive type spaced source and drain region on a first surface of the Fermi-tub region. And a channel of a second conductivity type between the spaced apart source and drain regions on the first surface of the Fermi-tub region. The channel extends a first predetermined depth (Y _f ) from the first surface, and the Fermi-tub region extends a second predetermined depth (Y _o ) from the channel.
A gate insulating layer is provided between the source and drain regions of the first surface on the substrate that are separated from each other. Source, drain, and gate electrodes are provided for electrical connection to the source and drain regions and the gate insulating layer, respectively.

At least the first and second predetermined depths are selected such that when a threshold voltage of the field effect transistor is supplied to the gate electrode, an electrostatic field perpendicular to the first surface at the first depth becomes zero. The first and second predetermined depths extend from the first predetermined depth toward the first surface when a voltage equal to or higher than the threshold voltage of the field effect transistor is applied to the gate electrode. It is also possible to select such that carriers of the second conductivity type can flow in the channel from the source to the drain. Thus, carriers flow from the source region to the drain region below the first surface without creating an inversion layer in the Fermi-tub region. Further, the first and second predetermined depths are:
The voltage on the substrate surface can be selected so as to double the Fermi potential of the substrate adjacent to the gate insulating layer. The sum of the voltage between the substrate contact and the substrate and the voltage between the polysilicon gate and the gate electrode is substantially zero.

Substrate has a doping density N _s intrinsic carrier concentration with doped with N _P, the temperature T degrees Kelvin and a dielectric constant e _s, has a substrate contact field effect transistor is in contact with the substrate electrically, the substrate channels Mashimashi predetermined depth Y _f extending from the surface, the Fermi - the tab region Mashimashi second predetermined depth Y _o extending from the channel, Fermi - doped with tub region in α times the doping density of the doping density N _s, Gate electrode is first
When it is doped at a doping density N _p and having a conductive type polysilicon layer of the first predetermined depth can be expressed by the following equation.

Where q is 1.6 × 10 ^-19 coulombs and K is 1.38 × 10 ^-23 joules / ゜ K. The second predetermined depth (Yo) can be expressed by the following equation.

Here, φ _s is equal to 2φ _f + KT / q, and φ _f is the Fermi potential of the semiconductor substrate.

FIG. 1 shows an N-channel high-current channel FET according to the present invention.
Is shown. It is easy to obtain a P-channel Fermi-FET by reversing the conductivity type of the N-channel region and the conductivity type of the P-channel region.

As shown in FIG. 1, a high-current Fermi-FET 20 is formed on a semiconductor substrate 21 having a first conductivity type, here a P-type, and including a substrate surface 21a. A second conductivity type, here, N-type Fermi-tub region 22 is formed on the surface 21 a of the substrate 21. A source region 23 and a drain region 24 of a second conductivity type, here N type, which are separated from each other, are formed on the surface 21 a of the Fermi-tub region 22. Source and drain regions,
It can be easily formed in the trench on the surface 21a.

The gate insulating layer 26 is formed on the surface 21a of the substrate 21 between the source region 23 and the drain region 24 which are separated from each other. As known to those skilled in the art, the gate insulating layer is typically silicon dioxide. However, silicon nitride and other insulators can be used.

A gate electrode is formed on the insulating layer so as to face the substrate. The gate electrode preferably includes a polycrystalline silicon (polysilicon) gate electrode layer 28 of a first conductivity type, here a P-type. Conductive gate electrode layer, typically metal gate electrode layer 29
A polysilicon gate electrode facing the gate insulating layer 26.
28. A source electrode 31 and a drain electrode 32, typically a metal, are also formed on the source region 23 and the drain region 24, respectively.

A substrate contact 33 of the first conductivity type, here a P-type, is also formed in the substrate 21 inside the Fermi-tub 22 as shown or outside the Fermi-tub 22. As shown, board contacts
33 may be doped with a first conductivity type, here P-type, such that this contact comprises a relatively high doped region 33a and a relatively low doped region 33b. The substrate electrode 34
Establish electrical contact to the substrate.

The structure described so far with reference to FIG. 1 corresponds to the low capacitance (capacitance) Fermi-FET structures of US patent applications 07 / 977,689 and 07 / 826,939. As already described in these applications, channel 36 is the source region.
It is formed between 23 and the drain region 24. In FIG.
The depth of the channel from the surface 21a shown in Y _f, Fermi from the base of the channel indicated by the Y _o 1 (bottom) -
The depth to the bottom of the tub 22, along with the doping levels of the substrate 21, the tub region 22 and the polysilicon gate electrode 28, is high performance using the relationship of equations (2) and (3) above,
Choose to provide a low capacitance field effect transistor.

Still referring to FIG. 1, in accordance with the present invention, a source conductivity (injector) region 37 of the second conductivity type, here N-type.
a is provided adjacent to the source region 23 and opposed to the drain region. As will be described later, the source injection region generates a high current,
Fermi-FET by controlling the depth injected into the
To achieve. The source injection region 37a can extend only between the source region 23 and the drain region 24. The source implant region preferably surrounds the source region 23 forming the source implant tab region 37, as shown in FIG. The side and bottom surfaces of the source region 23 can be completely surrounded by the source implantation tab region 37. Alternatively, the side surface of the source region 23 is surrounded by the source implantation tab region 37, which may penetrate the source implantation tab region 37 and project to the bottom surface. Further, the source injection region 37a is
Extending into 1 may form a bond between Fermi-tub 22 and substrate 21. Drain injection region 38a,
Drain implant tub region 38, preferably surrounding drain region 24
It is also preferable to provide

The source implant region 37a and the drain implant region 38a or the source implant tub region 37 and the drain implant tub region 38 preferably have a relatively low doping level of the Fermi-tub 22 and a relatively high doping level of the source 23 and the drain 24. It is preferred to dope to a second conductivity type of intermediate doping level, here N-type. Thus, as shown in FIG. 1, the Fermi-tub 22 is designated as N, the source implanted tub region 37 and the drain implanted tub region 38 are designated as N +, and the source region 23 and the drain region 24 are designated as N ++. Thus, a single junction transistor is formed.

The high current Fermi-FET of the present invention generates a driving current that is about four times the driving current of the conventional FET. Gate capacitance is about half that of conventional FET devices. The doping concentration of the source injection tub region 37 controls the depth of carriers injected into the channel region 36 typically to about 1000 °. The doping concentration of the source implantation tub region 37 is typically 2E18
Preferably, the source implanted tub region 37 has a depth at least equal to the desired maximum depth of the implanted majority carriers. The source implanted tub region 37 extends to the same depth as the Fermi-tub region 22 to provide a subthreshold leakage current, as described below.
rent). This shows that the carrier concentration injected into the channel 36 cannot exceed the doping concentration of the source injection region 37a facing the drain. The width of a part of the source injection region 37a facing the drain is typically
The range is 0.05 to 0.15 μm. The doping concentration of each of the source region 23 and the drain region 24 is typically 1E
19 or more. The depth of the Fermi-tub 22 ( _Yf + _Yo )
The doping concentration of about 1.8E16 is about 2200 °.

As shown in FIG. 1, a high-current Fermi-FET 20 includes a gate side wall (side wall) spacer 41 on a substrate surface 21a2.
The gate sidewall spacer 41 extends from the adjacent source implantation region 37a to the adjacent polysilicon gate electrode 28. Gate sidewall spacer 41 preferably also extends from adjacent drain implant region 38a to adjacent polysilicon gate electrode 28. In particular, as shown in FIG. 1, the gate sidewall spacer 41 is
a, the source implantation region 37a and the drain implantation region
Lying on each 38a. Preferably, polysilicon gate electrode 28 is surrounded by gate sidewall spacers 41. Also preferably, as described later, the gate insulating layer 26 is formed on the source surface 37a and the drain region on the substrate surface 21a.
Extending over 38a, gate sidewall spacer 41 also extends over source implant region 37 and drain implant region 38.

The gate side wall spacer 41 reduces the pinch-off voltage of the Fermi-FET 20 and increases its saturation current in a manner described in detail below. Preferably, the gate side wall spacer is
An insulator having a higher dielectric constant than the gate insulating layer 26 is used. Thus, for example, if the gate insulating layer 26 is silicon dioxide, the gate sidewall spacer is preferably silicon nitride. When the gate insulating layer 26 is made of silicon nitride, the gate sidewall spacer is preferably made of an insulator having a dielectric constant higher than that of silicon nitride.

As shown in FIG. 1, a gate sidewall spacer 41 can extend over the source region 23 and the drain region 24, respectively, and a source electrode 31 and a drain electrode 32 are formed at extensions of the gate sidewall spacer region, respectively. can do. Conventional field oxide region or other insulator 42
Regions separate the source, drain and substrate contacts. Although the outer surface 41a of the gate sidewall spacer 41 is shown as a curve in the cross-sectional view, other forms may be used, such as a straight outer surface forming a triangular cross section or a right outer surface forming a rectangular cross section. Can be understood by those skilled in the art.

0.8 μm High Current Fermi-FET Design Referring to FIGS. 2A-2C, a preferred doping profile and geometry for designing a 0.8 μm channel high current Fermi-FET as shown in FIG. 1 is described. I do.
One skilled in the art will understand that both N-channel FETs and P-channel FETs can be manufactured in a similar manner. Figures 2A-2C
0.8 μm from which the drain current characteristics shown in 5B to 5C are derived
The N-channel high-current Fermi-FET doping profile that forms a device with a channel length is a simulation result shown in a graph. Methods of achieving these doping profiles are known to those skilled in the art, and a number of known methods have been used.

2A to 2C, the P-type doping concentration of the polysilicon gate electrode 28 is changed with respect to the P-channel or the N-channel.
2E19. The SiO ₂ gate insulating layer 26 has a thickness of 140 °. The thickness of the polysilicon gate electrode 28 is 3,000 mm.
The height of the gate side wall spacer 41 is also 3000 mm, and the gate side wall spacer 41 is made of silicon nitride. The width of the source injection tab region 37a facing the drain is set to about 0.1 μm, and the gate insulating layer 26 overlaps this area by about 0.05 μm.

Referring now to FIG. 2A, along line 2A-2A 'in FIG.
A vertical doping profile centered on the source 23 and perpendicular to the surface 21a will be described. The area to which the profile applies is also shown labeled on top of the horizontal axis in FIG. 2A. As shown, side wall spacer 41 has a thickness of about 140 °, and source region 23 has a depth of about 2000 ° from surface 21a. Source implanted tub region 37 has a depth of about 2000 _° from surface 21a, and Fermi-tub 22 has a depth (Y _f + Y 0) of 2200 _° from surface 21a. The thickness of the substrate 21 is about 1 μm.
The doping concentration of the source implantation tab 37 is about 2E18, and the doping concentration of the source region 23 is about 2.5E19.

FIG. 2B is the doping profile shown along the line 2B-2B ′ in FIG. As shown in FIG. 2B, Fermi-tub
22 was realized using a double injection step resulting in a double hump. However, those skilled in the art will appreciate that multiple implants or other techniques can be used to create a uniform doping profile for the Fermi-tub, if desired. As shown, the Fermi-tub 22 has a depth of about 2200 ° at an average concentration of a flat area of 1.8E16. The effective doping concentration of the humpback substrate is about 1E17.

FIG. 2C shows the doping profile along the line 2C-2C 'in FIG. In other words, the doping profile is from the center of the source region 23 to the center of the drain 24 via the source implanted region 37a, the channel 36 and the drain implanted region 38a. These regions are similarly denoted by reference numerals in FIG. 2C.

Referring to FIG. 3, an enlarged cross section of the area between source 23 and polysilicon gate electrode 28 is shown to illustrate the operation of source injector region 37a and gate sidewall spacer region 41. When the gate voltage becomes equal to or higher than the source voltage, the electric field E _ii ends at the interface 39 between the source injector region 37a and gate sidewall spacer region 41.
The electric field _Eii is applied to the polysilicon gate electrode 28 and the interface 39.
At the surface of the injector region 37a. Due to this electric field, charge accumulation is performed within the depth δ of the surface of the injector 37a as shown in FIG. Using the divergence theorem from the boundary condition of the injector-insulator interface 39, the following condition is obtained.

Here e _s is the permittivity of the substrate 21, E _s is the injector 37a at interface 39 field, e _ii is the permittivity of the spacer region 41, E
_iin is the electric field of the spacer region 41 at the interface 39.

For this reason, the electric field E _{s at the} silicon surface can be represented by various dielectric constants at the interface and the electric field E _{iin of the} injector insulator as shown by the following equation.

Source 23 is at ground potential and the polysilicon gate electrode
28 is in the gate voltage V _g of the above ground electrodes (N-channel)
In the case, the electric field E _iin of the injector insulator is expressed as the difference between the gate and injector surface potential φ _s divided by the insulator thickness βT _in of the effective spacer region as shown in the following equation: V _t is the threshold voltage.

The fringe field factor β is generally greater than or equal to one and depends on the length of the factor field path from the polysilicon gate electrode 28 and interface 39 as shown in FIG.
Β is close to 1.0 for long channel devices and β> 1.0 for short channel devices. This difference depends on the depth of the charge storage layer of the polysilicon gate electrode layer 28 on the insulator interface. For short channel devices, this depth tends to increase the fringe factor β.

The gate sidewall spacer 41 can be made of the same material as the gate insulating layer 26. However, generally, the dielectric constant e _ii of the sidewall spacer 41 needs to be larger than the dielectric constant e _gi of the gate insulating layer 26. Preferably, the ratio e _ii / e _gi should be at least equal to the fringe factor β. For β = 1, the increased dielectric constant acts to reduce the sub-threshold leakage current. As an insulating material, it is preferable to select silicon dioxide (SiO ₂ ) for the gate insulator 26 and silicon nitride (Si ₃ N ₄ ) for the gate sub-spacer 41.

Surface field E _s from Equation (5) and (6) can be derived as shown by the following equation.

Here, δ is the depth of the storage region, q is the charge, and N _ac (y) is the concentration depending on the depth of the stored charge on the surface of the injector.

Since the conduction of the Fermi-FET depends on the charge accumulation rather than the inversion, the same equation can be expressed for the total equivalent accumulation of the majority carriers under the gate electrode where the drain voltage is low. The actual depth δ of this charge is controlled by the injection profile. This equation is represented by the following equation.

The basic relationship between the surface potential φ _s and the surface electric field e _s will be described below. As the drain voltage approaches zero, the total charge in channel region 36 is given by:

Here, N _ch (y) is the volume density of the channel charge measured in the vertical direction, and δ is the depth of the charge flowing to the source end of the channel. Insulator at the source end of the channel - the vertical field density E _s of the silicon of the silicon surface 39 can be expressed by the following equation using the divergence theorem.

By comparing the expressions (9) and (10), the surface electric field E _s becomes dependent only on the total charge Q * per irrelevant unit area and charge distribution in the depth direction of the channel. Therefore, the surface electric field is expressed by the following equation.

Next, the surface potential at the source end of the channel based on the same channel charge distribution is determined. Using Poisson's equation, the surface potential under the injector insulator at the source end of the channel is:

The gate-induced injection of excess charge at the source-channel interface into the Fermi channel region is then quite uniform at the charge flow depth depending on the properties of the surface injector region 37a. Under these circumstances, N within the charge flow depth δ
_It is appropriate to set _ch (y) = N _do . Under this condition, the following equation is obtained from the following (12).

Therefore, the basic relationship between the source potential φ _s and the surface electric field E _s is derived from Expression (9) under the condition N _ch (y) = N _do as shown by the following expression.

In other words, the surface potential of the source terminal perception of the channel is the product of 1/2 and a surface potential E _s of the charge flow channel depth [delta].

By substituting equation (14) into equation (8), the surface electric field E _s
Is obtained as follows.

The factor δ in equation (15) corresponds to the effective carrier flow depth of the tub-FET channel as shown in FIG. The effective gate capacitance C _g * F / cm ² is given by the following equation.

Therefore, the drain saturation current and its structure dependency can be predicted as shown by the following equation using equation (15).

In other words, the drain saturation current is the effective gate capacitance C
_g *, channel width Z, carrier speed V, and gate drive voltage C _g −V _t . The channel length _Lo is given by equation (17).
Does not appear directly. In order to show the role of the channel length, the expression of the carrier velocity V shown in (17) is further performed.
Equation (17) can be rewritten by the product of the carrier mobility μ and lateral field E ₁ as shown in the following equation.

Therefore, the following equation holds when electrons are considered.

By substituting equations (19a)-(19d) into equation (17), a basic solution for the drain saturation current is obtained as shown in the following equation.

Here, C _g * is given by equation (16).

Similarly, the drain saturation current for a P-channel device can be expressed as:

If the gate drive current is large in a short channel device,
Saturation current can be expressed by a simple equation independent of channel length and carrier mobility as shown in the following equation.

Therefore, when determining the drain saturation current of the Fermi-FET, L _o is of little use channel length of approximately 1μm or less. The most basic control of the saturation current is the thickness of the injector insulator, its relative permittivity and the effective charge flow depth δ. The injector tab doping concentration is appropriately selected and the charge flow depth δ is adjusted to be 200 ° or more.

4A and 4B show the simulated drain saturation current of N and P channel tub FETs plotted as a function of channel length _Lo and gate insulating layer thickness _Tgin . The relative insensitivity to N-channel length is compared against insulator thickness. P channel device is a hole (hole)
It becomes more sensitive to channel length due to the lateral electric field effect on velocity. FIG. 4C shows a plot of simulated gate capacitance versus gate insulating layer thickness when δ = 200 °.

When the following equation is satisfied in the design of the tub FET, the lowest pinch-off voltage for maximum saturation current and low subthreshold base current is obtained for a given injector tub depth. This equation relates to the dielectric constant of the injector 37, the spacer 41 and the gate insulator 26.

The following equation is obtained from equation (18) as one of the tab FET designs.

Here, if T _iin = T _gin , the following equation is obtained.

When actually designing a high current Fermi FET, silicon nitride (Si ₃ N ₄ ) is used for the gate sidewall spacer 41.
And silicon dioxide (SiO ₂ ) can be used for the gate insulator 26. The dielectric constant of silicon nitride is 7E-13F /
cm and the dielectric constant of silicon dioxide is 3.45E-13F / cm. Accordingly, the ratio becomes β = 1.5 or more. 1.6 ma / μm N-channel device and 0.8 in very high drive current Fermi-FET
For ma / μm P-channel devices, it is preferred to use a 100 ° silicon nitride gate insulator. Unlike silicon dioxide insulators, silicon nitride insulators have a high field strength of 1E
It has 7 V / cm and can therefore be made thinner, yet maintain a high gate breakdown voltage and improve complete aging. In a Fermi-FET using a nitrided gate insulator, the spacer and injector insulator can be nitride, but preferably the spacer and sidewall insulator material is twice the dielectric constant. The gate sidewall spacer 41 does not need to extend directly on the surface 21a, but a thin insulating layer of a material other than the material of the sidewall spacer 41 can be formed at the interface 39 between the injector 37 and the sidewall spacer 41. .

5B and 5C show 0.8 μm N-channel high current Fermi F
3 shows a simulated drain current characteristic of an ET device.
FIG. 5A shows a similar simulated state of a conventional 0.8 μm MOS N-channel device. FIG. 5A shows a 5V MOS technology with a 150 ° SiO ₂ gate insulator. FIG.5B shows 140 °, SiO ₂ ,
The characteristics of a high-current Fermi-FET having a gate insulator are simulated and shown. FIG. 5C shows a simulated high current Fermi-FET with 100 °, silicon nitride, and gate insulator. In both cases, the drain current and pinch-off characteristics of the high current Fermi-FET device are significantly better than MOS or buried channel technology. That is, similar improvements are obtained for P-channel high current Fermi-FET devices as compared to MOS or buried channel technology. That is, the P-channel saturation current is typically one-half of the N-channel saturation current, and the pinch-off voltage is approximately twice that of an N-channel device.

Representative base current and sub-threshold leakage characteristics of the high current Fermi-FET devices of FIGS. 5B and 4C are shown in FIGS. 6A and 6B.
Shown in FIG. 6A shows the characteristics of the N-channel high-current Fermi-FET, and FIG. 6 shows the characteristics of the P-channel high-current Fermi-FET.
Shown in B. That is, these figures show 0.8 μm per μm width.
, And the P-channel current of a 0.8 μm transistor per μm width are shown. Base current is 5V bias at room temperature, typically 2E-
13 A / μm. This can be reduced to 2E-15A / μm using the short channel technology described below.

FIG. 7 shows a variety of different sidewall spacer structures 41.
5V, N-channel, high-current Fermi-FET with (Figure 1)
2 shows the worst case of a simulated comparison plot of the drain current of FIG. In all plots, the thickness of the SiO ₂ gate insulator 28 is 132 °. Various Fermi-FET structures are shown in FIGS. 8A and 8C.

FIG. 8A shows Example 1 in which the gate sidewall spacer 41 is made of silicon nitride and the gate insulator 26 is made of silicon dioxide. Also, the gate insulator 16 is shown at the interface 39 so as to be slightly superimposed on the top of the injector 37a. FIG. 8B shows Example 2 in which the gate sidewall spacer 41 is made of silicon nitride and the gate insulator 26 is made of silicon dioxide. In this case, the gate insulator 26 does not overlap the source injector region 37a at the interface 39. FIG. 8C shows Example 3 in which both the gate sidewall spacer 41 and the gate insulator 26 are made of silicon dioxide. This structure is also a polysilicon gate
28 edge at source interface 39a source injector region 37a
It is configured to slightly overlap with. In all cases, the effective channel length was 0.71 μm.

As shown in FIG. 7, in Example 1, the drain saturation current is maximum and the pinch-off voltage is small. Example 1 also confirmed that the sub-threshold base current was minimized at an arbitrary drain voltage. Example 1 further satisfies the conditions specified by equations (24) and (25). Therefore, Example 1 is preferred. The reason is that the gate insulation region 26
Is partially overlapped on the source injector region 37a at the interface 39, and the dielectric constant of the gate sidewall spacer region 41 is larger than the dielectric constant of the gate insulating region 26.

Low Leakage Current Fermi Threshold Field Effect Transistor A Fermi FET with a short channel that still produces low leakage current according to the present invention will be described with reference to FIGS. 9A and 9B. This device was subsequently referred to as "Low leakage current Fermi FE
T ". 9A low leakage current Fermi-FET50
Includes a bottom leakage current control region 51 of the first conductivity type, ie, the P conductivity type, which is heavily doped with respect to the substrate 21. It is therefore marked P + in FIG. 9A. FIG.
Low leakage current Fermi FET 60 includes enlarged source and drain injection regions 37a, 38a,
Preferably, it extends to a depth of 2.

9A, the bottom leakage current control region 51 extends across the substrate 21 from between the extensions of the opposed ends of the source and drain regions 23 and 24, and extends from the top of the Fermi bath 22 to the bottom. Extends into. It's Fermi Channel
Preferably it is located below 36 and in line with it.
The depth from the Fermi channel 36 to the top of the bottom leakage current control region 51 is consistent with the equation described earlier.
Y ₀ . Other parts of the Fermi-FET transistor of FIG. 9A are identical to those described in FIG. 1 except that a shorter channel is depicted. Persons skilled in the art may omit the implanted regions 37a and 38a and the implanted baths 37 and 38 to provide a low leakage current low capacitance short channel Fermi FET without the high current characteristics of the device of FIG. It will be appreciated that the gate sidewall spacer region 41 may be omitted.

The bottom leakage current control region 51 minimizes the drain induced injection in short channel Fermi field effect transistors, ie, these field effect transistors have a channel length of about 5 μm or less and yet have low diffusion depletion Maintain capacitance. For example, at 5 volts, the leakage current can be maintained at 3E-13A or less.

The bottom leakage current control region can be designed using Equation (2), where Y ₀ is the depth from the channel to the top of the bottom leakage current control region as shown in FIG. The factor α is the ratio of the P + doping of the bottom leakage current control region 51 to the N doping of the Fermi bath 22. Preferably, α is set to about 0.15, ie, below the gate 28, inside the bottom leakage current control region. Source and drain region 23
Under and 24, α is set to about 1.0 to minimize diffusion depletion capacitance. In other words, the doping concentration of the substrate 21 and the Fermitab 22 is substantially equal in the region below the source and the drain. Thus, for the above design parameters, and for a 0.5 μm channel width, the doping concentration of the bottom leakage current control region 51 is about 5E17, the depth of which gives a drain or source diffusion potential of 5 volts. Sufficient to support partial diffusion in the provided tab junction area.

Next Looking at Figure 9B, another design for bottom leakage current control is preferable to extend the depth of the source implant region 37a and drain injection region 38a to a depth of the Fermi tab (Y _f + Y ₀₎ is there. As shown in FIG. 9B, the All Source Injection tab
It is preferred that the depth of 37 and the drain implant tub 38 reach the depth of the extended Fermi tub. Injection tab
The separation distance between the bottom of 37 and 38 and the bottom of Fermi-tub 22 is preferably less than half the channel length,
Is preferred. Under these conditions, the injection tab
37 and 38 has a doping concentration of approximately 1.5E18 / cm ^3. Similarly, it is preferable to extend the depth of the substrate contact region 33b so as to approach the depth of the Fermi-tub. Fermi-FET of Fig. 9B
Other parts of the transistor 60 are the same as those described in FIG. 1 except that a shorter channel is drawn.

0.5 μm Low Leakage Current Fermi-FET Design Next, with reference to FIGS. 10A-10B, a preferred doping profile and geometry for designing the 0.5 μm low leakage current Fermi-FET shown in FIG. 9A will be described. . One skilled in the art will know that both N-channel FETs and P-channel FETs are fabricated in a similar manner. All geometries and doping profiles are such that the length of the channel region 36 between the opposing surfaces of the implanted regions 37a and 38a is 0.5 μm instead of 0.8 μm as described above.
And is the same as that described in FIGS. 2A-2C, except that a bottom leakage current control region 51 has been added. Those skilled in the art will be familiar with how to achieve these doping profiles using many known techniques.

FIG. 10A shows the vertical doping profile centered on channel 36 along line 10A-10A ′ of FIG. 9A. Each area where this profile is obtained is as described on the top horizontal axis of FIG. 10A. As shown, the bottom leakage current control region 51 extends from 1950 angstroms (10 ^-10 m) to 4000 angstroms from the top surface 21a of the substrate 21. Thus, it is centered near the interface between Fermi-tub 22 and substrate 21. The doping concentration is 5E17. In contrast to FIGS. 2A-2C, the substrate 21 is doped with 1E17.

FIG. 10B shows the doping profile along line 10B-10B ′ of FIG. 9A. As shown, the bottom leakage current control region 51
Is approximately the same length as the channel length between the source implantation region 37a and the drain implantation region 38a, that is, approximately 0.5 μm
Extends only horizontally.

Referring now to FIGS. 10C-10D, a preferred doping profile and geometry for designing the 0.5 μm channel low leakage current Fermi-FET shown in FIG. 9B will be described.
One skilled in the art will know that both N-channel FETs and P-channel FETs are fabricated in a similar manner. All geometries and doping profiles are such that the source implant region 37, the drain implant region 38, and the substrate contact region 33b are extended to a tub depth of about 2000 Angstroms, and between the opposing surfaces of the implant regions 37a and 38a. Channel region 36 is 0.5 μm instead of 0.8 μm
2A-2C, except that

FIG. 10C shows the vertical doping profile centered on channel 36 along line 10C-10C 'of FIG. 9B. As shown, the substrate concentration is approximately 1E18. FIG.10D is line 1 of FIG.9B.
10 shows a side view of the doping along 0D-10D '. As shown, the source injection tank 37 extends to the depth of the Fermi tank.

Operation of Bottom Leakage Current Control Region Next, the operation theory of the bottom leakage current control region 51 of FIG. 9A and the deep injection region of FIG. 9B for reducing the leakage current in the short channel device will be described. First, the concept of the sub-threshold will be described in order to define the term used for the bottom leakage current. A discussion of how the depth of the implant tub affects bottom leakage current is then developed, along with a discussion of drain-induced implantation and a reduction in drain field threshold.

Solving the equations describing the behavior of the sub-threshold of a Fermi-FET requires some new definitions. FIG. 11 shows the basic behavior graphically. There are four main features of the sub-threshold current behavior. In FIG. 11, these action areas are labeled A, B, C, and _DFTL . Point A defines a “sub-threshold” threshold V _stt . Point B defines the normal conduction threshold. Point C defines the "bottom leakage current" that is affected by the drain voltage. Finally, the arrow on the _DFTL defines "Drain field threshold reduction". The sub-threshold threshold occurs when the injection gate field is zero.

Referring again to FIGS. 9A and 9B, the dependence of the bottom leakage current on the drain voltage is a result of the drain field component terminating on the source injection diffusion 37a facing the channel. This drain field terminating at the source causes carrier injection into channel 36. This sub-threshold effect is called "drain-induced implantation" DII.

DII is a characteristic property of many-carrier Fermi-FET and buried-channel field-effect devices. Below the threshold, the majority carrier channel 36 and the Fermitab
22 does not include charge sites that inhibit the drain field from extending across the channel region. As a result,
The drain field can be terminated in the source depletion region facing the channel and can cause implantation.

In contrast, minority carrier MOS devices require a substrate area that bridges the source and drain. Thus, the drain field is terminated by ionizing the substrate region adjacent to the drain diffusion region facing the channel. If the substrate region is completely depleted between the source and drain diffusion regions, a well-known punch-through phenomenon occurs, resulting in a rapidly increasing high injection current.

In summary, MOS device design is confused by punch-through and threshold issues. Embedded channel devices are confused by both punch-through and DII. Fermi FETs are only confused by the DII condition, which is due to the bottom leakage current control region or the injection region.
By increasing the depth of 37 and 38, it can be reduced considerably. When comparing Fermi-FETs with MOS and buried-channel devices, the significantly higher current and speed advantages of Fermi-FETs are much more important in the former than the design constraints required for DII control, and in the latter the punch The constraint for eliminating thru and threshold is the opposite. Both problems become increasingly important as the channel length decreases.

The following analysis is intended to explain the impact of depth Y _d of the injection into the contours of its easy (diverting) the drain electric field in majority carrier Fermi FET device. Figure
The bottom leakage current control region 51 of 9A and the deep implant tub of FIG. 9B are virtually equivalent to eliminating DII.

FIG. 12A shows the electric field contour that results when drain-induced implantation becomes a problem for a low capacitance Fermi FET that includes Fermi-tub 22 and implanted regions 37, 38 and does not include sidewall spacers 41. In particular, the region at the bottom corner of the injection tub contributes to excess DII due to the electric field condensed there. FIG. 12B shows a properly compensated strategy to minimize this effect by moving the bottom edge of substrate depletion region 21 closer to the bottom of source and drain tabs 37,38. 9A also achieves this result.

A drain implanted region 38 facing the channel 36, the contour integral of the drain field terminating on poly gate surface 28 is present equal certain depth Y _L to the contour integral of the drain field terminating in the substrate region 21. At that point, the drain field can be terminated at the source 23 facing the channel region. There is an implant tab depth that minimizes the number of lines of the electric field that can be terminated on the source implant region 38. This requirement implies that α is less than one. Typically, α <Lo / 2. When designing a Fermi-FET device, the following equation (31) must be considered. The depth is predicted Y _L should not exceed the depth of the implanted region. Otherwise, significant bottom leakage current will flow out of the bottom and corners of the diffusion under the sub-threshold regime. Equation (32), determined below, gives the minimum bottom current.

Equation (32) is also described in U.S. Patent Nos. 4,990,974 and 4,9,974.
It also predicts the basic design criteria for the first Fermi-FET specified in 84,043. In particular, when Y _tub = Y _O and Y _O = Y _P , α = 1 and Y _L = Y _O. In other words, the diffusion depth Y _d must then be equal to the Fermi channel depth Y _O. Y _P
Is the depletion depth of the substrate region.

Next, equation (32) is derived. The effective radius of the electric field lines terminating on the polysilicon gate electrode 28 as R _1, the effective radius of the electric field lines terminating in the substrate region 21 and R _2, the drain electric field along these field lines between E _d . The electric field between the diffusion regions is almost uniform in the sub-threshold region as compared to the electric field terminating in the substrate region below the diffusion region.

(Π / 2) R ₁ E _sd + T _OX E _sd (e _s / e _i ) = V _d + V _pj (26) (π / 2) R ₂ E _sd = V _d + V _w (27) R ₂ = Y _tub + Y _P -Y _L (28) using to R ₁ = Y _L (29) equation (26) to the (29), V _w = well potential _{(KT / q) log e (} N ^ / Ns); and V _pj = Polysilicon gate electrode junction potential (KT / q) log _e (N ^ / N _poly ) where Is obtained. If V _w = V _pj : Is obtained. Equation (31) is independent of the electric field strength E _d. The depth Y _p of the depletion of the substrate, must be placed in small by design.

The punch-through phenomenon is a severe problem for short channel MOS devices and buried channel devices.
High substrate doping is required to minimize its effects. In all FET structures, a second drain-induced phenomenon occurs, called the "drain field threshold reduction" DFTL. Briefly, DFTL is the result of an insulating layer potential developed near the source end of a channel, which is the electric field created by the drain voltage terminating at the gate when the gate voltage is lower than the drain voltage. Is the result of The drain-induced insulation layer potential is always in the direction of decreasing the threshold. Punch through is eliminated by the low capacitance Fermi FET, but the DFTL still remains. D
The following formula shows the change in threshold voltage ΔVt due to FTL, which applies only when the drain voltage is higher than the gate voltage, where Lo is the channel length and _Xd is the diffusion The depth of: Is obtained.

The effect of the DFTL increases with the amount by which the drain voltage exceeds the gate voltage, and becomes more pronounced with lower gate voltages as the channel length decreases. This effect is correspondingly reduced by reducing the thickness of the gate insulation.

An experimental way to measure the effect of DFTL is to plot the subthreshold behavior of the device. 6A and 6B
See DFTL drain voltage V _d increases accompanying rising curve of the left voltage transition by, i.e. Log ₁₀ I _ch is described.

Next, a high saturation current Fermi-FET according to the present invention will be described with reference to FIG. The high saturation current Fermi-FET 200 is the same as the Fermi-FET 20 of FIG. 1 except that the source tub region 37 and the drain tub region 38 are not present. However, as those skilled in the art are well aware, these areas are to be used as described above. Also, the gate electrode layer
28 comprises a first layer 28b of the first conductivity type, here P-type, and a second layer 28c of the second conductivity type, here N-type. “Field Effect Transistor Having Pol”
No. 08 / 087,509, entitled "Ycrystalline Silicon Gate Junction", the disclosure of which is incorporated herein by reference. Drain tub area
Either or both 37 and 38 and single layer gate 28 may also be used.

According to the present invention, the source region 23 adjacent to the channel 36
Of the second conductivity type (here, N ++) is kept at a minimum high enough to maximize the saturation current of the field effect transistor. Source area facing channel 36
The doping of 23 and drain region 24 is preferably maintained at this minimum doping, and the doping of all source and drain regions 23 and 24, respectively, is most publicly maintained at this minimum doping. Needless to say,
Higher doping levels may be used,
It will do little to increase the saturation current of the transistor.

The concentration in the channel region 36 may be higher or lower than the concentration in the tub region 22, and is lower than the concentration in the source region 23 and the drain region 24. The edges of the channel region 36 preferably abut the source and drain regions 23 and 24 or, if present, the source and drain tubs. The source and drain regions are at least as deep as the channel 36, and preferably less than the depth of the tub 22.

Substrate region 21 is of the same conductivity type as doped polysilicon gate 28b adjacent to gate insulating layer 26. Substrate 2
The doping concentration of 1 is higher than the doping concentration of the tub 22, and is preferably four times as high.

Next, it is shown that the drain saturation current of the Fermi-FET transistor is controlled by the diffusion doping concentration of the source 23 and the drain 24 adjacent to the channel 36. The highest drain saturation current is achieved for a given doping concentration when the vertical field does not allow to cross the channel 36. Thus, for a given channel length, the diffusion concentration has a minimum value above which the drain saturation current stops increasing.

Thus, there is no need to fabricate extremely short channel tab FETs to achieve high drive currents. For example, if a tab FET with a channel length of 0.8 microns is optimized for maximum drive current, fabricating shorter channel devices will be of little help in increasing drive current. Drain saturation currents of 16 amps per centimeter and 9 amps per centimeter for N-channel and P-channel devices, respectively, are achieved from tab FET device designs using 0 to 5 volts as the supply voltage. To achieve these current levels, a gate insulating layer 26 of 100 Å thick silicon nitride or 50 Å thick silicon dioxide or other gate insulating material with equivalent gate capacitance effect is required. is necessary.

Gate capacitance of the T-FET depends on the movable channel charge Q _ch per unit gate voltage (Vg-Vt). Thus, gate capacitance is proportional to cumulative efficiency. According to the present invention, it is experimentally possible that high cumulative efficiency will occur if excess charge can be stored in either or both of the source and drain diffusion injection regions facing the channel. Has been verified. Thus, φ _X is the flat band potential between the source / drain diffusion and the channel, KT / q = 26 mV at room temperature, N _do is the source-drain concentration facing the channel 36 and preferably the drain doping concentration. lighted, when the doping concentration of the N _ch channel 36: Becomes FIG. 14 shows this in a graph.

The minimum depth _Xd of the diffusion depletion region is approximated as follows.貯積been free charges is its value is constant, its sign is opposite to the overall charge in the diffusion depletion region facing the channel, the e _S is the dielectric constant of the substrate, q and 1.6 × 10 ^-19 coulombs When: Becomes

FIG. 15 shows an equivalent amount of excess carrier available in the free storage area stored in the channel area. In Figure 15, the Y _f depth deli channel 36, Z is the width of the channel 36. The following discussion ignores free charge. The components of the free charge will be discussed later.

Maximum貯積amount of free貯積charge Q _r is: _{Q r = qN do X d Y} f Z (35). If φ _X is given by equation (33), then replace equation (34) with X _d : Q _r = Y _f Z (2e _S φ _X qN _do ) ^1/2 (36) Become.

Equation (36) defines the excess charge available for injection. When the maximum gate voltage V _gmax is applied above the threshold, this total available charge must be able to fill the channel. Since the free charge flows into the channel, the carrier diffuses across the N ++ / N _ch bonding, replace them. The effective channel volume V _ch filled per diffusion is: V _ch = (ZδL _O ) / 2 (37) Therefore, when N _chex = channel excess carrier concentration; δ = excess carrier inflow depth; L _O = channel length; Z = channel width, the charge transferred to the channel is: Q _ch = (q / 2) N _chex ZδL _O (38)

It can be proven that the channel charge is also related to the gate capacitance and the gate drive voltage (Vg-Vt). The following equation holds: C _g ^* ZL _O (V _g −V _t ) = _qN chex δZL _O (39) Therefore, when Q _ch ^* is the charge per unit volume: _{qN chex} δ = C _g ^* ( V _g −V _t ) = Q _ch ^* (40).

The basic equation for the channel saturation current I _sat can be written as follows: where V _L is the lateral velocity: I _sat = C _g ^* (V _g −V _t ) ZV _L (41)

Next, conditions for controlling the lateral speed _VL will be discussed. Substituting equation (40) into equation (38) yields an important equation defining the accumulated channel charge due to source diffusion: Q _ch = (C _g ^* / 2) ZL _O (V _g −V _t ) (42) Is obtained. Substituting equation (36) to an available channel charge of formula _{(42): Y f Z (} 2e S φ X qN do) 1/2 = (C g * / 2) ZL O (V g -V t ) (43) Equation (43) is the actual gate capacitance C _g
^* Can be solved to be expressed by the diffusion impurity concentration N _do and the channel region Y _f , where Y _f = the depth of the Fermi channel adjacent to the source and drain diffusions N _do = the Fermi channel from the substrate-insulating interface 21a Average diffused impurity concentration at the depth to the bottom of the substrate L _O = channel length e _S = dielectric constant of the substrate φ _X = given by equation (33) V _gmax = expected maximum gate voltage V _t = threshold voltage given that: Is obtained.

The gate capacitance has a maximum value determined by an independent analysis, which is: Given by If the ratio of Equation (44) and Equation (45) is obtained, the following equation can be obtained as a gate capacitance factor. Is obtained.

According to equation (41), the gate capacitance factor G _f
When = 1.0, the maximum saturation current occurs for a given lateral velocity.

FIGS. 16A and 16B illustrate equation (46) for various channel lengths L _O.
As a function of the source / drain diffusion concentration N _do with respect to, and given values are Y _f = 600 Å V _gmax = 5 volt V _t = 0.8 volt δ (inflow depth) = 120 Å Also, FIG. 16A shows that T _OX = 100 Å and FIG. 16B shows that T _OX = 140 Å, and FIGS. 16A and 16B show that it is necessary to achieve the maximum saturation current. It is said that there is a limit concentration N _do , the value of which is different for different channel lengths L _O. This maximum occurs when the gate capacitance factor G _f = 1.0. This maximum depends mainly on the channel length L _O and on the insulation thickness T _OX . This limit is calculated by the following formula: Is defined by When designing Fermitab FETs, Equation (47) should be applied to the longest possible channel L _O. Under these circumstances, a short channel length tub FET will inherently have the same drain saturation current for the same gate voltage. There is very little gain in terms of drive current by making short channel devices. Fermi-tub FETs designed with channel lengths of 0.8 microns or less are more efficient than designs with MOS or MOS buried channel devices at any channel length.
Has a much higher drive current for a given gate voltage.

Next, referring to FIG. 27, the high saturation current Fermi according to the present invention will be described.
A second embodiment of the FET will be described. The high saturation current Fermi FET 300 of FIG. 27 includes a source doping gradient region 50a between the source region 23 and the channel 36, and preferably a drain doping gradient region 50b between the drain region 24 and the channel 36. Except for the respective additions, they are the same as the high saturation current Fermi-FET 200 of FIG. The source doping ramp region 50a and preferably the drain doping ramp region 50b may have a relatively high source / drain doping concentration adjacent to the source and drain regions to a relatively low channel 36 doping concentration adjacent to the channel 36. Doped with a doping gradient that decreases to

According to the present invention, the source doping gradient region 50a and the drain doping gradient region 50b preferably have a thickness S of at least 300 angstroms to support a high saturation current in the tub FET 300. I already know. . In addition, as shown in FIG.
It is also preferred that 26 and gate electrode 28 overlap source and drain doping gradient regions 50a and 50b. Again, as shown in FIG. 27, the source doping gradient region 50a and the drain doping gradient region 50b
Preferably surrounds the source 23 and the drain 24, respectively.

Source and drain doping gradient regions 50a and 50b
The following explains the theoretical reason why the high saturation current is given when the thickness of each of the layers exceeds 300 angstroms. Further, when used in conjunction with the source and drain inclined region, the minimum source and drain doping levels, if the source and drain is deeper than the Fermi channel, i.e. X _i is the Fermi channel is greater than Y _f depth becomes what gives the above formula is replaced with the depth X _j of the source and drain instead of the Y _f (47), it will also be proved that.

It has already been shown that high accumulation efficiency occurs when there is normal access to the free charge stored in the diffusion ramp opposite the Fermi-tub channel region between the source diffusion 23 and the drain diffusion 24, respectively. At the threshold, the Fermitab region 22 will be completely depleted from the bottom to the surface 21a of the substrate facing the gate insulation,
It is the result of a PN junction between Fermitab 22 and substrate 21. Depleting the Fermitab in this manner will eliminate the junction field that intersects the surface channel region 36 during majority carrier conduction.

Next, the source / drain diffusion concentration N _do required to provide the proper charge accumulation at the edge of the depleted diffusion region.
And the depth S of the gradient. At a given maximum gate voltage above the threshold, the proper charge accumulation is sufficient to fill half of the channel amount of length L _O with a large number of carriers, resulting in a critical gate capacitance value defined as Achieve C _g ^* . That is: T _OX = thickness of gate insulation 26 δ = inflow depth of carrier e _S = dielectric constant of substrate 21 e _i = dielectric constant of insulating layer 26 C _g ^* = 1 / ((T _OX / e _i ) + (Δ / 2e _S )). Referring to FIG. 27, the gate electrode
If 29 is below or below the threshold, the substrate-tub junction will completely deplete the Fermi-tub region to a portion of the periphery of the doping ramp regions 50a, 50b facing the gate insulating layer 26 and the Fermi-tub. The diffusion impurity concentration N _do and the slope thickness S must be sufficient to prevent the total diffusion slope thickness S from being consumed during depletion. The analysis described below shows that for a given maximum gate voltage, the Fermi FE
A basic formula is developed that defines the requirements for the diffusion design to achieve the maximum drain saturation current from T.

FIG. 28 shows the periphery of a diffusion where the density decreases in discrete steps from high to low density. This discrete model is useful for finding equations for diffusion design. FIG. 28 shows that a dipole charge morphology occurs at each step junction. Bound positive c
harge) is due to depletion in the diffusion region, and the free negative charge is weakly coupled to the step junction. Charge neutralization is confirmed at each step junction. The gate 28 overlaps the doping gradient regions 50a and 50b as shown in FIG.

As a result of the tub-substrate junction, the doping ramp distance S
28 is defined as X in FIG. When depletion occurs, the penetration distance X must be smaller than the distance S. The total free charge within the distance X cannot be stored due to carrier diffusion across the substrate junction required to meet the charge neutralization requirements there. If the gate voltage exceeds the threshold, free charge can accumulate in the surface channel in section SX.

The total undepleted reserve of the distributed charge can be calculated from the abrupt junction between the tub and the diffusion. It is shown in FIG. 29, where X _j = depth of source / drain diffusions 23,24 Y _d = depth of depletion during diffusion Z = channel width N _do = maximum source / drain diffusion 23/24 concentration When: Qtotal = qN _do X _j ZY _d (48) The total potential developed across N _do −N _tub is: φ _j = (1/2) (2Y _d ) E (0) = (KT / q) log _e (N _do / N _ch ) (49) Then, E (0) = qN _do Y _do / e _S (50).

Free charge is assumed to occupy the same depth Y _d. Combining Equation (49) and Equation (50) gives: φ _j = (qN _do / e _S ) Y _do ² = (KT / q) log _e (N _do / N _ch ) (51)

Solving this for Y _do : Becomes Therefore, the maximum available stockpile charge Q _R: Becomes

This total charge is distributed along the thickness S of the doping gradient region. Therefore, a free charge density N _fc = Y _do N _do / S exists along the thickness S of the doping gradient region. When the doping ramp is depleted by the distance X in FIG. 28, the available free charge left to fill half of the Fermi channel as a result of depletion inside the tub from the tub-substrate PN junction . is of貯積amount ^{_{Q r ▲ ∫ s o ▼ N}} FC dx = Y do N do that when: Becomes Based on the definition of the free charge density inside the doping gradient, the free charge Q _r is: It is. Substituting equation (52) into equation (55) yields a basic equation that determines the reserve of free charge available to fill half of the Fermi channel. It should be noted that when the drain voltage and the source voltage are both 0, the free charge in each doping gradient region at the depth _Xj becomes half of the channel amount if the gate voltage is above the threshold. It is to satisfy. Given the transition time, one cannot tolerate relying on the free charge at the bottom of the diffusion to fill the channel volume.

The貯積amount Q _r of free charges, given at the maximum value (Vg-
When equal to the amount required to fill half of the channel L _0/2 relative vt): Is obtained. Solving Equation (57) for the gate capacitance C _g ^* per square centimeter gives the basic equation that defines the gate capacitance: Is obtained. Next, a penetration distance X to the thickness S of the doping gradient region is determined as a result of depletion by the tub-substrate PN junction. Through the depletion process the charge is: Must be maintained. For the purpose of analyzing this, it is assumed that the doping gradient region is linear with respect to X, ie: N _d (X) = ((N _do −N _tub ) / S) X + N _tub (60) and phi _j = assumed _{(KT / q) log e (} (N do N a) / N i 2) (61). Substituting equation (60) into equation (59): Is obtained. Solving this gives a quadratic equation for x: The solution to this equation (63) is: It is. Therefore, equation (64) gives the solution depth X of the penetration of depletion into the doping gradient region. Note that X is a factor in equation (58). Equation (64) is used in combination with Equation (58) to calculate the gate capacitance
Determine C _g ^* and therefore the expected maximum gate voltage V _gmax
Define the drain saturation current for When Equation (58) reaches the maximum gate capacitance C _gmax ^* , a successful source-drain design for a given channel length L _O is realized.

From this analysis, it can be seen that if an inappropriate channel charge is available for a given gate voltage V _g above the threshold voltage V _t , the gate capacitance C _g ^* and the drain saturation current
You can see that I _sat is extremely low. This is the guided from a ^{_{Q ch * = C g * (}} V g -V t) and ^{_{I sat = C g * (V}} g -V t) V L Z.

FIG. 30 is a graph showing the saturation current of a 0.8 micron N-channel Fermi-FET with 100 Å thick silicon nitride and 50 Å thick silicon dioxide as the gate insulating layer. Is plotted as a function of thickness S in Angstroms. The source / drain doping concentration _Ndo was moved as a parameter, and in all cases the source / drain depth was 1500 Å. It is worth noting that the saturation current is independent of the slope S, which is greater than 300 Å, irrespective of the diffusion concentration N _do . It is also shown that the saturation current increases as the diffusion concentration increases.

FIG. 31 shows the saturation current as a function of source / drain doping concentration for the same structure as above, but with a doping gradient region thickness of S = 300 Å or more. In FIG. 31, the channel length L _O is moved as a parameter. The saturation current shows that it reaches a maximum of about 17 A / cm when the gate voltage is 5 volts and the threshold voltage is 0.8 volts. Gate capacitance
Source / drain doping concentrations above the limit do not increase the saturation current since the maximum value of C _g ^* has already been reached. To achieve the maximum saturation current compatible with the thickness of the selected insulating layer, a thin gate insulating layer is the highest requirement. Reducing the channel length of a Fermi-FET device relaxes the requirements on source / drain doping concentration for the same maximum current. Fermi FE
There is no other important reason to shorten the channel length of T.

Equations (58) and (47) show that the diffusion depth X _j replaces the Fermi depth Y _f , and that if S> 300
Å is the same except that (SX) /S=0.95. See equation (32). Therefore, the minimum diffusion concentration required to reach the maximum current is the same as equation (47) placing the X _f instead of Y _f. In all cases where X _j > Y _f , it can be used instead of the diffusion depth X _j .

Fermi-FET with Reduced Threshold Voltage Referring again to FIG.
But typically at a depth Y _f of 600 to 700 angstroms
And doping concentration N _ch per cubic centimeter
have. FIG. 17 is an explanatory diagram of a vertical electric field for the structure of FIG. N _sub = when the impurity concentration N _tub = bath (tub) impurity concentration N _i = intrinsic (intrinsic) carrier concentration e _S = permittivity KT / q = 26 millivolts at room temperature of the substrate material of substrate (Substrate) In茲, as well as Then, the tab depth Y _tub is defined by the following equation: Y _tub = Y _O + Y _f (65)

The depth Y _P of the depletion region in the substrate 21 can be expressed by the following equation: Y _P = Y _n N _tub / N _sub (68)

Referring to FIG. 17, the channel region Y _f when the gate voltage V _g = V _t is depleted by the threshold. When V _g> V _t exceeds the carrier threshold, the channel charge neutral, substrate - vertical electric field from the tab junction, as the gate voltage to the top of the excess carrier threshold V _tec increases that place Independent of the density of the excess conducting carriers stored in the channel region. The formula defining the excess carrier threshold V _tec is when N _pol is the doping concentration at the polysilicon gate-insulating layer interface in polysilicon gate 28b: It is.

The threshold voltage V _t is defined as follows: V _t = V _tec −V _comp (70) where the compensation voltage V _comp is the surface potential loss φ _S, ie: φ _S = ((qN _ch ) / 2e _S) is the sum of Y _f ² (71) becomes phi _S, which is a part of the triangle covered by oblique lines in FIG. 17. The potential V _ox developed at both ends of the gate insulating layer is as follows: V _ox = ((qN _ch ) / e _i ) Y _f T _ox (72) So the formula for the threshold voltage is finally: Can be written.

Equation (73), from the threshold voltage fundamental term V _tec and Equation (52), the depth Y _f and channel impurity concentration of the channel
It indicates that it can be transformed by N _ch . The thickness of the insulating layer has a secondary effect. Basic threshold voltage
V _tec is the doping concentration in the polysilicon gate N _POL
Note that it can be controlled by Therefore, where ΔV _t = change from twice the Fermi potential to the threshold voltage: Becomes

The depth Y _f of the channel, independently of the implanted impurity concentration N _ch, it is reasonable to limit the fixed value of about 600 angstroms. It has already been shown in the previous section that the channel depth _{Yf is} also a factor in determining the drain saturation current. Fixing the values of channel depth Y _f is allowed to independently control the saturated current and the threshold voltage. In order to achieve a very high drive current, the doping concentration N _ch in the Fermi channel Y _f must be less than 5E16 / cm ³ . Otherwise, the mobility of the carrier will decrease rapidly, at 5 volts, below the value required to support high drive current.

FIG. 18 is a plot of Equation (73) for T _OX = 100 °, N _pol = 2E19, and N _tub = 2E16. The horizontal axis represents the channel concentration, and the vertical axis represents the threshold voltage. Moving as a parameter is the depth of the channel, taking three values 600 Å, 700 Å and 800 Å. From Expression (73), the threshold voltage is independent of the substrate concentration N _sub . However, the depth of the _tub is dependent on the substrate concentration, as seen in equation (66), and when the product N _tub N _poly is equal to N _sub ² , the threshold is twice the Fermi potential of the substrate. Is set.

Therefore, as shown in FIG. 18, the threshold voltage can be decreased by increasing the doping concentration in the channel, and conversely, can be increased by decreasing the channel concentration. If one intends to operate at 3.3 volts or less, it may be desirable to lower the threshold voltage. The sub-threshold threshold is separated from the threshold voltage by twice the Fermi potential of the channel, ie, 2 (KT / q) log _e (N _ch / N _i ). This is point A in FIG.
And the point B.

Leakage current is very sensitive to threshold voltage. A typical subthreshold slope is 90 per decade.
mV. For the minimum sub-threshold leakage current, the sub-threshold threshold must occur when the gate voltage is zero or slightly positive. Sub-micron channel length FET devices have difficulties in the sub-threshold region (0 gate volt region). The voltage difference between the sub-threshold threshold and the threshold condition is typically 790 mV. If a short channel device requires a threshold voltage of, for example, 400 mV, the zero gate voltage leakage is about 5 decades above 1E-13A / 2 microns, or its value is about 1E-8A /
Micron. This leakage voltage is too high for VLSI technology to tolerate.

Therefore, the threshold voltage of the Fermi-FET will be lowered. On the other hand, by selecting the depth of the channel and tub that supply the zero vertical electrostatic field, and
By providing a larger channel doping concentration given by, the zero electrostatic field perpendicular to the substrate surface at the Fermi channel depth is still maintained. Those skilled in the art will understand that the channel doping concentration cannot be vaguely increased. In particular, above a channel concentration of 5 × 10 ¹⁶ , carrier mobility begins to decrease and the device saturation current begins to decrease. However, the channel doping concentration will increase from that doping concentration, which means that the concentration
A threshold voltage of twice the Fermi potential is generated up to × 10 ^16, and when it is necessary or desirable to lower the threshold voltage of the Fermi FET device, the threshold voltage of the Fermi FET device is deemed necessary. Lower.

For a given Fermi channel depth, eg, 600 Å, the threshold voltage and saturation current can be adjusted independently. Those skilled in the art will also understand that. Tuning the saturation current is accomplished by increasing the doping concentration of the source and drain diffusions adjacent to the channel, as described in the previous section. Adjustment of the threshold voltage is performed independently by increasing the doping concentration of the channel. Therefore, they are controlled independently.

Comparison of MOSFETs and Fermi-FETs In any prior art FET device except Fermi-FET technology, there is a vertical electric field in addition to the horizontal electric field across the channel. Horizontal electric field E ₁ is by the drain-source potential that is oriented along the channel between the source and the drain. Vertical electric fields in MOS devices are manifested by static charges generated in the depleted substrate region below the gate insulating film when the gate voltage reaches a threshold. This vertical electric field intersects the inverted minority carrier MOS channel region, resulting in the formation of an inverted layer.

Fermi-FET technology moves multiple carriers within a Fermi-channel having the same doping type as the Fermi-tub and source and drain regions. Fermi FET
This design prevents any vertical electric field due to channel crossing and any other vertical electric field caused by the majority carrier itself while excess majority carriers are flowing between the source and drain.

This section describes a closed-form equation for FET drain saturation current that includes the effects of both horizontal and vertical eigenfields. While accounting for large values of drain saturation current, greater than 7 A / cm for N-channel devices and greater than 4 A / cm for P-channel devices, small leakage currents, on the order of 1E-13 A / μm or less, reduce the vertical electric field component. Explain that it can only be achieved by removing the Fermi-FET design. Fermi-FETs conduct by storage, and block by inversion. MOSFETs conduct by inversion and shut off by accumulation. The potential difference between inversion and accumulation is, in both cases, two times the Fermi potential of the channel region.
It is twice.

The saturation current of the FET device shown in equation (14) can be described by the following basic equation.

I _sat = C _g ^* (V _g −V _t ) V _L ZCOSθ (74) where C _g ^* = gate capacitance due to mobile charge / cm ² V _g = gate voltage V _t = threshold voltage V _L = horizontal Velocity Z = channel width θ = angle between carrier flow vector field and horizontal direction.

Equation (74) does not explicitly show the effect of the channel length _Lo . Equation (74) follows from a first principle idea that the charge is the product of the capacitance and the voltage, ie, Q = CV, and the current is dQ / dt.

The expression (74), in addition to the gate voltage V _g and the threshold voltage V _t, 3 three basic parameters that determine the flow of current is present. These parameters are the gate capacitance C _g ^* , the horizontal velocity V _L and the angle θ. The horizontal velocity term accounts for the role of carrier mobility U _x , channel length _Lo and saturation velocity V _sat in determining the transconductance characteristics of the drain saturation current. The vertical electric field defines the angle θ. The gate capacitance term C _g ^* applies only to charge transfer and controls the maximum amount of charge that can flow in the channel per unit voltage, the effect of insulating film thickness and carrier flow depth. Will be described.

In a MOSFET, when the gate voltage reaches a threshold, there is a lot of static charge under the gate. This charge is present in the depleted substrate region under the gate and is necessary to form a minority carrier inversion layer. The gate capacitance _Cgo ^* = associated with this static charge _Qim
Q _im / V _t exists. There is also a gate capacitance coefficient C _gmax ^* that accounts for the flow of mobile charge in the channel.

Here, T _ox = depth of gate insulating film δ = depth of moving carrier e _i = dielectric constant of gate insulating film e _s = dielectric constant of semiconductor.

Against a threshold or more predetermined gate voltage, the total electric charge maintained by MOS ^{_{gates, Q = [C go * V}} t + (C gmax *) (V g -V t)] A (76) Where C _go ^* ≒ e _i / (2T _ox ) and the mobile charge is the second term in equation (76).

The total gate capacitance for Fermi FETs is only C _gmax ^{* for} gate voltages above threshold. Only mobile charges are in the channel region. The rate of charge of the gate capacitance for MOS devices is positive for gate voltages rising from ground to the threshold voltage, while negative for Fermi-FETs. This characteristic of the Fermi-FET provides excellent noise rejection in high-speed digital systems.

Here, leads to expression of the form is closed about the horizontal mobility including the influence of the vertical electric field E _p. This equation is based on the fact that the saturation rate is a vector quantity. This basic fact indicates that the drift velocity can reach thermal saturation only in the vector field direction. FE besides thermoelectrons
Since there is no net vertical component of velocity in the T-channel, the effect of the vertical electric field has the effect of weakening the horizontal component of velocity. The decay rate is cos θ, where θ is the angle between the vector field direction and the channel flow direction. Thus, the horizontal rate of increasing the drain current in a FET device is V ₁ cos θ, where θ is the angle between the vector field and the horizontal electric field component. This is shown in FIG.

Horizontal movement under the influence of a horizontal electric field is witty. Equation (77a) determines the horizontal mobility of the excess electrons, and equation (77b)
Determines the horizontal mobility of the hole.

The horizontal speed is the product of the horizontal electric field E ₁ and the horizontal mobility μ ₁ . E ₁ is the horizontal drain field at the source end of the channel around the excess carrier due to the pinch-off voltage, and E _c is the critical horizontal field, for example, the hole mobility is half its low field value. Therefore, Where μ _o is the low field mobility of the doped semiconductor and V _sat is the thermal saturation rate at temperature T.

Equation (78) is correct in the vector direction in addition to the horizontal direction.

Equations (77a) and (77b) need to be modified to include the effect of the vertical electric field crossing the channel to reflect the exact vertical movement in the channel. The vertical components of mobility and velocity are simply cosθ in the vector direction.
Multiplied by. Use the following definitions:

Tan θ = E _p / E _{1 ′} (80) cos θ has the following solution according to the terms of the vertical and horizontal electric field components in the channel region.

Equation (78) can be used to modify equations (77a) and (77b) to reflect the exact horizontal shift in the channel.

Since the horizontal velocity is the product of the horizontal electric field and the horizontal mobility, a general equation for the horizontal velocity for both holes and electrons can be written as:

In general, the horizontal velocity for holes and electrons is Where: Is the horizontal electric field due to drain pinch-off, Is the vertical electric field required to maintain the MOS inversion, And In _{and, E h = V dd / L} o is the horizontal electric field due to the drain voltage, a substrate concentration N _i for N _sub = Fermi FET, Is the Fermi potential and _Where L _o = channel length and V _dd = power supply voltage.

Using equations (84a) and (84b), FIGS. 20A and 20B
Is the maximum horizontal velocity curve for each of the electrons and holes. The speed in both cases is plotted as a function of drain voltage, the substrate concentration N _sub in the range 2E16 to 2E17 is plotted for MOS devices, and N _sub = N _i is plotted for Fermi FETs. . As shown, the horizontal electron velocity reaches a nearly saturated value for the Fermi-FET when the gate voltage is 5V. All excess carrier flow is below the surface, and thus the vertical electric field generated by the MOS device has a near maximum value across the carrier flow depth δ.

In both FIGS. 20A and 20B, the horizontal majority carrier velocity in the tub FET reaches a maximum and there is no vertical electric field crossing the channel. Other curves generate vertical electric fields at and above the threshold. It corresponds to a MOS device having a substrate doping concentration in the range 2E16 to 2E17.
For a minority carrier MOS structure, a vertical electric field is needed to form an inversion structure. Is affected by the drain voltage and not by the pinch-off voltage. The reason is that the drain saturation current of the MOS device is
This is because it is smaller than half the drain saturation current of the tab FET device.

21A and 21B show the coefficients cosθ for the situation described above.
Is shown. The channel length _Lo is 0.8 μm with respect to FIG.
0.5 μm for 21B. Cosθ in both cases
Has a maximum of 1.0 for Fermi FETs only.
Since the drain saturation current is L _sat = C _g ^* (V _g −V _c ) V ₁ Zcos θ, the Fermi FET achieves the maximum drive current capability.

Respect MOS device, there is a function between the vertical electric field E _p and the threshold voltage V _t. Both quantities include the substrate doping concentration. This relationship is described here so that the drain saturation current for a MOS device can be compared to the value of a Fermi-FET.

The sum of the potentials along the contour from the center of the gate electrode of the N-channel MOS device to the substrate contact is given by the following equation.

Where φ _s is the potential rise in the vertical direction intersecting the substrate region under the gate, N _sub = substrate node, N _poly = doping concentration at the _poly gate, DFTL = the source of the channel due to the vertical component of the drain field The voltage effect between both ends of the gate insulating film at the end, V _ox = the potential appearing across the gate insulating film due to the vertical electric field.

When using P-type polycrystalline silicon, the solution for the P-channel device agrees with equation (85) except for the polarity term. Using the divergence theorem and Poisson's equation,
The equations for V _ox and φ _s are given below.

Here E _s is a vertical surface electric field at the substrate under the insulating film.

N _tc is the volume density of charges captured in the gate insulating film. In FIG. (86a), the positive sign is
Used for trapped charge. Substitution gives Where C _i = capacitance of the insulating film e _i / T _ox , δ = depth of the carrier flow, and Y _i = depth of the substrate depletion layer below the gate.

The coefficients qN _ch δ, qN _sub Y _i and qN _tc T _ox can be described in terms of charge density as follows _:

qN _ch δ = Q _ch ^* , channel charge density, qN _sub Y _i = Q _sub ^* , substrate depletion layer charge density, QN _tc T _ox = Q _tc ^* , density of charges captured in the gate insulating film.

Substituting these equations into equation (87) and modifying the terms yields the following equation for the oxide voltage effect V _ox :

Surface potential phi _s has the formula.

Based on the above rules for V _ox and φ, the equation for gate voltage, equation (85), can be extended as follows:

The first voltage term in equation (90) is due to mobile charge. The second and third terms are due to the static charge in the substrate and the charge trapped in the gate insulating film, respectively. The last term is the flat band voltage and the voltage appearing across the insulating film due to the vertical component of the drain electric field. This effect is reduced by DFTL,
n Field Threshold Lowering).

From equation (90), the threshold voltage is It is.

When strong inversion occurs, the depth of the depletion layer region below the insulating film becomes It is.

Using equation (92) and the definition of charge density, the following equation defines the threshold voltage.

_{2φ f = KT / q 1n (} N sub / N i) 2 and DFTL = V _d e _s T _ox
/ 2L _o e _i ) Becomes

The term of the trapped oxide charge in the equation (94) will be described. If the trapped charge is negative, a positive sign is used. If the trapped charge is positive, a negative sign is used. Effect of the threshold voltage due to trapped charge is the square of the thickness of the gate insulating film is dependent on T _ox ^2.

The volume and area density of the trapped charge is T _ox = 100Å
It is necessary to change the threshold voltage to 100mv, It is.

It is evident from equation (95) that a large amount of trapped charge is required rather than being able to significantly change the threshold voltage. From the analysis of this threshold voltage and its dependence on the trapped charge, the actual mechanism responsible for the so-called "thermo-electron" problem with MOS devices can be inferred. The vertical electric field at the insulator-substrate interface created by the depleted substrate region in a MOS device has a significant effect on the probability of trapping electrons in the gate insulator, thereby generating "thermal electrons".

Returning to the determination of the threshold voltage for MOSFET, the expression for the threshold voltage, equation (94), open the logarithmic terms, net of the threshold voltage _{V tent = V t + KT /} q1n (N poly / N amend by specifying _sub ). Therefore, equation (94)
Is Becomes

In order to obtain the basic equations of the vertical electric field E _p, equation (96),
Solve for the substrate concentration _Nsub . E _p at the source end of the channel is given by the substrate doping concentration N _sub sections as follows.

Therefore, solving equation (96) for N _sub gives Becomes

Equation (98) into equation (97), obtain the expression for the vertical electric field E _p for MOS devices.

The trapped charge equation appears in the vertical field equation,
It can be seen that the drain electric field threshold term does not appear. A negative sign corresponds to an electron being captured. Thus, electron capture reduces the vertical MOS electric field. That is, the trapped charge may affect the drain saturation current by affecting cosθ. The vertical field in a typical MOS device that needs to be inverted is 1E5
The voltage is set to about volt / cm, which is large enough to maintain charge trapping in the insulating film. The trapped charge easily changes this value by 10%.

Equation (99) must be used to determine the MOS drain saturation current. The values for the threshold voltage must not be less than twice the Fermi potential of the channel region, if not, the leakage current is 10 increased for each increment of 80mV below the threshold 2 [phi _f Would.

Equation (99) includes the eigenvalue for the substrate density. Expression (9
It can be seen that 9) can be used to eliminate the risk of destruction of the MOS punch-through state for all channel lengths of 0.15 μm.

Equation (99) is shown as a summary. In its simplest form, the intensity of the MOS vertical electric field varies linearly with the threshold voltage and varies inversely with the thickness of the gate insulating film. MOS scaling law suggests keeping the ratio V _t / T _ox constant. However, this condition
This is a failure because the subthreshold leakage current increases by 10 for every 80 mV increment of the threshold voltage below twice the Fermi potential. The saturation current is the threshold voltage
Increasing the reduction of V _t, as predicted by equation (99). However, the leakage voltage increases dramatically.

FIG. 22A is a cross-sectional view of a representative MOS device having a “lightly doped” diffusion layer, LDD. Light doping for MOS devices is on the order of 1E19 impurity ions / cm ³ .

A diagram of the vertical electric field at the threshold for this MOS device is shown in FIG. 22B. Y _i defines the depth of the depletion region below the MOS gate at the threshold. It also shows the depth of flow below the insulating film-substrate interface, which is called the inversion depth. Excess carrier injected at this depth
Under the influence of a strong vertical electric field, the horizontal carrier speed decreases.

FIG. 23A is a cross-sectional view of an exemplary P-type “buried channel” MOS device having a lightly doped diffusion layer. A vertical electric field diagram is shown in FIG. 23B for a typical buried channel device for threshold conditions. The depth of the depleted substrate region below the gate insulating film corresponds to the gate voltage at the threshold. The buried carrier changes the threshold voltage by reducing the vertical electric field crossing the insulating film.

FIG. 24 is a diagram of the vertical electric field for the Fermi-FET of FIG. For all voltages above the threshold, a vertical electric field does not traverse the entire depth of the Fermi channel indicated by Y _f in FIG. 24. Therefore, the accumulated excess carriers flowing through this area have the greatest horizontal mobility. Further, the excess carrier threshold voltage does not depend on the thickness of the gate insulating film. This effect is due to the absence of an electrostatic vertical electric field near the threshold. Thus, the Fermi-FET drive current capability can be selected by oxide thickness and diffusion concentration without considering or changing other structural design reasons.

Fermi-tub FET saturation current for N-channel devices And for a P-channel device: It is.

The following rules can be used for all of the above equations.

, Maximum gate capacitance, F / cm ² , where δ = depth of excess injected carrier flow, T _ox = gate dielectric thickness, e _s = dielectric constant of silicon, e _i = Dielectric constant of gate insulating film, V _sat = thermal saturation rate, V _t = threshold voltage, L _o = channel length, Z = channel width, μ _xo = low electric field mobility of carrier x, N _sub = substrate doping concentration It is.

FIGS. 25A-25C are comparisons of drain saturation current as a function of gate voltage V _g for NMOS and N Fermi FETs;
It is a comparison of the channel length L _o of the running parameters. 26A-26C are for P-channel technology. In all curves, the threshold voltage is twice the Fermi potential, or about 0.8V. This threshold voltage ensures a minimum leakage current, ie, 1E-13 amps / μm, when the gate voltage is at ground potential. The thickness of the gate insulating film, 140 Å of SiO ₂ in FIG. 25A and 26A
And is 100 ° in FIGS. 25B and 26B and 50 ° in FIGS. 25C and 26C. 25C and 26C, the drain supply voltage is 3 volts rather than 5 volts in other figures. It can be seen from the figure that only Fermi-FET can generate a saturation current of 7 A / cm or more for an N-channel device and 4 A / cm or more for a P-channel device. it is obvious. These large currents are due to the absence of a vertical electric field crossing the flow channel, ie, cosθ approaching unity.

Boundary Tab Fermi FET Referring now to FIGS. 33A and 33B, the Fermi FE of FIG.
A cross-sectional view showing a part of T20 and a corresponding electric field diagram are shown.
Like numbers refer to like elements in FIG. FIG.
Does not show source and drain regions 23 and 24, respectively. The boundary tab Fermi FET is
Those skilled in the art will also understand that they do not include the source and drain implant regions 37, 38 or sidewall spacers 41.

According to the present invention, the depth and doping concentration of the Fermi-tub is limited so that the performance of the Fermi-FET achieves an optimal high driving capability and low leakage current. These restrictions are typically more severe for P-channel devices than for N-channel devices. Because the mobility of holes in the P-channel device is smaller than that in the N-channel device,
Therefore, the P-channel saturation current is not completely dependent on the mobility. However, if the boundary tabs are
It can be suitably used for both channel and P-channel devices.

For a given Fermitab and effective substrate doping concentration, a deep Fermitab design results in a large drain leakage current. If you reduce the depth of Fermitab,
The leakage current is as small as 1E-15A / cm, but the saturation current is
It is about 15% smaller than usual. If the depth of the Fermi-tub is made too shallow, the Fermi-channel will be removed and a steady state vertical electric field will be directed into the tub region close to the insulator-tub interface. This vertical electric field component greatly reduces the mobility of majority carriers and consequently reduces the channel saturation current. As mentioned above, one of the basic criteria for Fermi-FETs is that the steady-state vertical electric field
At the tab contact surface, it is not present at any gate voltage above the threshold or above, and the other electric field components are generated by the excess carrier itself.

FIG. 33B corresponds to the behavior of a normal N-channel Fermi-FET when the gate voltage is at the threshold. FIG. 33B shows a diagram of the intrinsic electric field below the gate contact of the device shown in FIG. 33A. Starting from the gate electrode, an equipotential line along a line perpendicular to the Fermi channel is given from the gate to the substrate contact, and V _t = V _pol −V _ox −φ _ch + φ _surf −V _sub (101) Yes, where It is.

Extending equation (101) from the perspective of equations (102a) to (102e) and simplifying it, And, as already described here, It is.

Therefore, equation (103) becomes Becomes

The last term in equation (104) is typically 50 mV and is ignored in the following analysis. Simplifying the equation (104) from the above viewpoint, the following equation for the threshold voltage is obtained.

When the gate voltage drops to a ground potential (N-channel device) below the threshold, an inversion state is formed in the Fermi-tub region between the drain and source diffusion layers. Simulations show that this inversion mechanism creates a unique injection barrier between the source and drain, extending from the gate contact to the tub-substrate junction. The injection barrier has a unique shape and is positioned to surround the source. FIG.
Applied 5 volts to the drain 32 and 0 volts to the gate 28 and the source 31. 3 is a simulation of a generally closed inversion region acting as an injection barrier for a Fermi FET having a channel length of 0.8 μm. The smallest inversion density line shows 1E12 per cubic centimeter.

An equation indicating the state of the closed reversal injection barrier is given below.

Therefore, Equation (107) defines the maximum depth of the Fermitab.
With a deeper tub depth, it is not possible to form the inversion injection barrier to close when 0 V is applied to the gate. As a result, an increased drain leakage current is obtained.

The minimum depth of the Fermi-tab, defined as Y _o, depth of the tab substrate in the threshold state specified by the formula (105) - to allow full depletion of the tab by tab junction I do.

When the Fermi-tub depth is shallower than the minimum value of Expression (108), a steady-state vertical electric field is formed near the insulating film-tab contact surface, and the mobility of the majority carrier is greatly reduced.
The end result is a decrease in saturation current and an increase in pinch-off voltage. However, the leakage current is 1E-15A / cm
About.

FIG. 35 graphically illustrates the maximum and minimum values indicating the high performance of Fermi-tub depth as a function of the _tub doping concentration N _tub . FIG. 35 is based on equations (107) and (108). Running parameters for maximum depth of the tab is the substrate concentration N _sub in the range of 1E17 from 5E16. The minimum tub depth depends on the substrate doping concentration _Nsub , while the maximum tub depth depends on the polysilicon gate doping concentration.

High performance Fermi-tub depth designs are within a limited range between maximum and minimum values, which maximizes saturation current and minimizes leakage current. It is also necessary to operate 0.8 μm devices at light tub doping concentrations, for example of the order of 1.5E16, in order to maximize carrier mobility. A tub concentration around 2.5E16 is suitable for a Fermi-FET having a channel length of 0.5 μm.

Defining the equation for the Fermi channel depth Y _f within the limit as Y _tub −Y _o , Becomes

The curve depth Y _f of the Fermi channel, shown in Figure 36. This curve, the depth Y _f of the Fermi channel, indicated in Angstroms as a function of Fermi tab doping concentration N _tub along the horizontal axis shows the substrate concentration N _sub as the running parameters. The surface potential φ _s is given by equation (102d). A fermi channel depth of about 350 mm is required. FIG. 37 graphically illustrates the threshold voltage as a function of the tub doping concentration, with the poly concentration N _pol in the range of 5E18 to 2E19 as the running parameter. Extremely stable threshold voltages are achieved with high-performance Fermi-FETs.

Although the above description is based on N-channel devices, a similar equation can be used for P-channel devices. All concentrations may be the same. However,
Change the type of doping from N to P and from P to N.

In the drawings and specification, there have been disclosed representative and preferred embodiments of the present invention. Although specific terminology has been used, they are used only in a general, descriptive sense and are not intended to be limiting. The scope of the invention is set forth in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view illustrating an N-channel high-current Fermi-FET, and FIGS. 2A-2C illustrate preferred doping profiles and geometries of the high-current Fermi-FET of FIG. 1 having a 0.8 μm channel. FIG. 3, FIG. 3 is an enlarged cross-section showing a portion of the high current Fermi-FET of FIG. 1, FIGS. 4A and 4B show the simulated doping saturation currents of the N-channel and P-channel Fermi-FETs, respectively, for channel length and gate insulation layer thickness. 4C is a characteristic diagram showing the relationship between the simulated gate capacitance and the thickness of the insulating layer of a Fermi-FET, and FIG. 5A is a simulated transistor drain current characteristic of a conventional 0.8 μm N-channel MOSFET. 5B and 5C show 0.8 μm N-channel high current Fermi F
6A and 6B show simulated base current and sub-threshold leakage characteristics of N-channel and P-channel high-current Fermi FETs, respectively. FIGS. 8A-8C are simulated worst-case comparisons of drain current versus drain bias for various sidewall spacer structures of a current Fermi FET, FIGS. 8A-8C are enlarged cross-sectional views of the sidewall spacer structure shown in FIG. 9A is a cross-sectional view showing a first example of a short-channel low-leakage-current Fermi-FET, FIG. 9B is a cross-sectional view showing a second example of a short-channel low-leakage-current Fermi-FET, and FIGS. 10A and 10B are 0.5 μm-channel low-leakage of FIG. FIG. 10C and FIG. 10D show preferred doping profiles and geometries for designing current Fermi-FETs. FIGS. 10C and 10D show the 0.5 μm channel low leakage of FIG. 9B. FIG. 11 is an illustration showing a preferred doping profile and geometry for designing a current Fermi-FET, FIG. 11 is a characteristic diagram showing the base and sub-threshold voltage-current characteristics of a field effect transistor, and FIGS. 12A and 12B are electric fields showing a drain induced injection. FIG. 13 is an N-channel high current low leakage current Fermi FE of the present invention.
FIG. 14 is a cross-sectional view showing the configuration of T. FIG. 14 is an explanatory view showing accumulated free charges accumulated in a source and / or drain diffusion injection area facing the channel of the transistor of FIG. 13. FIG. 16A and 16B show the gate capacitance factor as a function of source / drain diffusion concentration for various channel lengths. FIG. 17 shows the threshold voltage of the transistor of FIG. FIG. 18 is an explanatory diagram showing an electric field, FIG. 18 is an explanatory diagram showing a state in which the threshold voltage is reduced by increasing the channel doping concentration of the transistor in FIG. 13, FIG. 19 is an explanatory diagram showing the saturation speed of a field-effect transistor in a vector amount, 20A and 20B are explanatory diagrams showing the maximum lateral velocities for electrons and holes, respectively. FIGS. 21A and 21B are FIGS. 20A and 2B respectively. FIG. 22A is a cross-sectional view showing an N-channel MOS device in which lightly doped diffusion is performed, FIG. 22B is an explanatory diagram showing an orthogonal electric field of the device of FIG. 22A, and FIG. FIG. 23B is a cross-sectional view showing a buried channel MOS device in which diffusion is performed, FIG. 23B is an explanatory diagram showing an orthogonal electric field of the device of FIG. 23A, FIG. 24 is an explanatory diagram showing an orthogonal electric field of the Fermi-FET transistor of FIG. 25C illustrates NMOS and N-Fermi-FET drain saturation current as a function of gate function and channel length. FIGS. 26A through 26C illustrate PMOS and P-Fermi-FET drain saturation current as a function of gate function and channel length. FIG. 27 is an N-channel high current low leakage current Fermi FE of the present invention.
FIG. 28 is an enlarged cross-sectional view of a part of the Fermi-FET of FIG. 27, and FIG. 29 is an undepleted reservoir of charges distributed adjacent to the source region of the Fermi-FET of FIG. FIG. 30 shows the saturation current for the Fermi-FET of FIG. 27 as a function of the thickness of the doping gradient region, and FIG. 31 shows the saturation current for the Fermi-FET of FIG. 27 as the source / drain doping concentration. FIG. 33A and FIG. 33B are each an illustration showing a portion of the Fermi-FET of FIG. 1 and its corresponding electric field, FIG. 34A is an illustration showing a simulation of a fully confined inversion region, FIG. 35 is an explanatory diagram showing a simulation of an inversion implantation barrier in which confinement has failed. FIG. 35 is an explanatory diagram showing the maximum and minimum values of Fermi-tub depth. Doping concentrations and diagram as a function of substrate concentration, FIG. 37 is an explanatory diagram showing a threshold voltage as a function of the tabs doping concentration and a polysilicon gate density.

──────────────────────────────────────────────────続 き Continuation of the front page (31) Priority claim number 177,847 (32) Priority date January 5, 1994 (1994.1.5) (33) Priority claim country United States (US) Preliminary examination (72) Inventor Vinyl Albert W. North Carolina, United States 27511 Carry Queens Ferry Road 810 (72) Inventor Dennen Michael W. North Carolina, United States 27615 Raleigh Windjammer Drive 8820 (56) References JP 62-66659 (JP, A) JP-A-55-98844 (JP, A) WO 90/10309 (WO, A1) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (1)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type, a tab region of a second conductivity type on a surface of the substrate, and a tab region of a second conductivity type on a surface of the substrate and separated from each other. A source region (23) and a drain region (24), a source implantation region (37a) of the second conductivity type adjacent to the source region and facing the drain region, and a source region and a drain region of a tub region on the substrate surface. A channel (26) of the second conductivity type located between the gate electrode and the gate insulating layer (26) between the source region and the drain region on the substrate surface; A source electrode, a drain electrode, and a gate electrode (31, 32, 28) in contact with each other, wherein the channel extends from the substrate surface at a first predetermined depth (Y _f ); At a second predetermined depth (Y ₀ ) And at least one of the first and second predetermined depths is selected such that a zero electrostatic field orthogonal to the substrate surface is generated at the first predetermined depth. And the tub region extends from the substrate surface to the inside of the substrate at a third predetermined depth, and at least the third predetermined depth is set to be equal to twice the Fermi potential of the semiconductor substrate. A field effect transistor selected to generate a threshold voltage.