JP3274653B2 - MOS type field effect transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS field effect transistor and a method of manufacturing the same, and more particularly, to a MOS field effect transistor suitable for use in connecting circuits having different power supply voltages.

[0002]

2. Description of the Related Art In order to improve performance such as operation speed,
The size of the MOS field effect transistor has been reduced according to the scaling rule in the MOS transistor. According to this scaling rule, in order to increase the operating speed of a transistor by a factor of K, the gate length and the gate insulating film thickness must be reduced to 1 / K. However, the intensity of the electric field applied to the gate insulating film cannot be arbitrarily increased from the viewpoint of the reliability of the device.
It is required to be.

[0003] With the advance of microfabrication technology used in the manufacture of semiconductor devices, the size of MOS field-effect transistors in semiconductor devices has been reduced for each technology generation. However, if the power supply voltage is changed for each technology generation, in the case of MOS-type logic circuits, the input / output levels do not match in a system using various semiconductor devices, and semiconductor devices with different power supply voltages are directly connected to each other. It becomes impossible to do. In order to avoid such a problem, it is necessary to provide an additional device or circuit such as a level shifter, or to prepare a buffer for unifying input / output levels in the semiconductor device.

For example, when the internal logic circuit portion of a semiconductor device is operated at a power supply voltage of 3.3 V according to the scaling rule, the gate oxide film thickness is set to 10 to 12 nm. In order to enable direct connection with the device, it is necessary to form a buffer composed of an output transistor having a gate oxide film thickness of about 15 nm at the output of the semiconductor device. That is, it becomes necessary to form a plurality of MOS field effect transistors having different gate insulating film thicknesses in the same semiconductor chip,
There is a disadvantage that the manufacturing process becomes very complicated.

On the other hand, it has been proposed to prevent the power supply voltage from being directly applied to the gate insulating film and to substantially reduce the intensity of the electric field applied to the gate insulating film. For example, Japanese Unexamined Patent Publication No. 5-55560 discloses a technique in which a polysilicon (polycrystalline silicon) layer serving as a gate electrode has a two-layer structure, and an electric field in a gate insulating film is reduced by changing impurity concentrations. ing. Hereinafter, this technique will be described.

FIG. 5A is a sectional view showing the structure of a MOS field effect transistor proposed in Japanese Patent Application Laid-Open No. 5-55560. Here, a P-channel MOS field effect transistor will be described.

A source region 18 and a drain region 17 are formed on an N-type semiconductor substrate 11, and a gate electrode is formed via a gate insulating film 12. The gate electrode has a two-layer structure including a low impurity concentration polysilicon gate layer 19 immediately above the gate insulating film 12 and a high impurity concentration polysilicon gate layer 20 laminated thereon. FIG. 5B shows this M
FIG. 4 is a diagram for explaining the operation of the OS type field effect transistor, and shows a bias state in which a relatively high positive voltage (drain voltage V _DD ) is applied to the drain region 17; The source region 18 is set at the ground potential, the gate electrode is biased to a negative potential by the gate voltage V _G. In this state, the low impurity concentration polysilicon gate layer 1 of the gate electrode is formed.
9 in the region near the drain, the drain region 17
The depletion layer 21 is formed by the relatively high voltage applied to the gate electrode, and as a result, the drain-gate voltage, that is, V _DD +
VG is _divided by the gate insulating film 12 and the depletion layer 21 so that the electric field applied to the gate insulating film 12 is substantially reduced.

[0008]

As described above, conventionally, in order to connect a semiconductor device capable of operating at a high speed to which a power supply voltage in accordance with a scaling law is applied to a semiconductor device having a higher power supply voltage, one semiconductor device is required. It is necessary to prepare a plurality of gate insulating films having different thicknesses in the chip or to form the gate electrodes in a two-layer configuration having different impurity concentrations. In the former case, gate oxidation needs to be performed multiple times,
In addition, a plurality of photolithography steps are required to select transistors having the same gate oxide film thickness, so that there is a problem that the manufacturing process becomes very complicated. In the latter case, at least two polysilicon growth steps and at least two impurity introduction steps are required to stack polycrystalline silicon layers having different impurity concentrations, and a MOS type electric field used at a low power supply voltage is required. In that an additional process for forming an effect transistor is required,
In addition, there is a problem that the manufacturing process becomes very complicated. Further, when the lower polysilicon layer (the one in contact with the gate insulating film) is formed by vapor phase growth, the film thickness accuracy must be at least about 50 nm. However, there is also a problem that the gate electrode has an unnecessarily thick gate electrode and it is difficult to finely process the gate electrode.

An object of the present invention is to improve the element structure, thereby alleviating the electric field intensity applied to the gate insulating film, enabling high-speed operation, and facilitating connection with circuits of different power supply voltages. It is an object of the present invention to provide a MOS field effect transistor that can be used and a method for manufacturing the MOS field effect transistor.

[0010]

A MOS field effect transistor according to the present invention comprises a semiconductor substrate of one conductivity type, a gate insulating film formed on the semiconductor substrate, and at least a part formed on the gate insulating film. In a MOS field effect transistor including a gate electrode made of a polycrystalline silicon layer and a source region and a drain region formed in the semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate, the gate electrode is formed in the polycrystalline silicon layer. In order to minimize the effective concentration near the interface with the gate insulating film, there is a continuous concentration gradient of impurities of the opposite conductivity type in the thickness direction of the gate electrode, and the gate is applied by applying a high electric field. A depletion layer is formed near the interface with the gate insulating film in the electrode.

In the MOS field effect transistor of the present invention, it is desirable to adopt a self-aligned LDD (Lightly Doped Drain) structure.

According to a first method for manufacturing a MOS field effect transistor of the present invention, a semiconductor substrate of one conductivity type, a gate insulating film formed on the semiconductor substrate, and at least a part formed on the gate insulating film are formed. In a method of manufacturing a MOS field effect transistor including a gate electrode made of a polycrystalline silicon layer and a source region and a drain region formed in a semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate, After forming the gate insulating film,
A first step of forming a polycrystalline silicon film and processing the polycrystalline silicon film into a shape of a gate electrode; and, after performing the first step, ion-implanting impurities of the opposite conductivity type,
Forming a source region and a drain region, and simultaneously introducing an impurity of the opposite conductivity type into the polycrystalline silicon film, wherein the polycrystalline silicon layer of the gate electrode has a vicinity of an interface with the gate insulating film. To minimize the effective concentration at
A continuous concentration gradient composed of impurities of the opposite conductivity type is formed in the thickness direction of the gate electrode, and the effective concentration of the impurities of the opposite conductivity type near the interface with the gate insulating film is such that a high electric field is applied. As a result, a MOS field effect transistor having a concentration at which a depletion layer is formed near the interface with the gate insulating film in the gate electrode is manufactured.

According to a second method of manufacturing a MOS field effect transistor of the present invention, a semiconductor substrate of one conductivity type, a gate insulating film formed on the semiconductor substrate, and at least a part formed on the gate insulating film are formed. A gate electrode formed of a polycrystalline silicon layer, and a source region and a drain region formed in the semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate, and the source region is relatively formed with a source diffusion layer having a relatively high impurity concentration. The source region includes a source-side LDD layer having a low impurity concentration, and the drain region includes a drain diffusion layer having a relatively high impurity concentration and a drain-side LDD layer having a relatively low impurity concentration. LDD on the source side without overlapping with the gate electrode
In a method of manufacturing a MOS field effect transistor in which a layer and a drain-side LDD layer overlap a gate electrode via a gate insulating film, after forming the gate insulating film on a surface of a semiconductor substrate, a polycrystalline silicon film is formed. A first step of forming and processing the polycrystalline silicon film into the shape of the gate electrode; and, after the first step, the source side LD is self-aligned by ion implantation of an impurity of the opposite conductivity type.
A second step of forming a D layer and a drain-side LDD layer, and simultaneously introducing an impurity of the opposite conductivity type into the polycrystalline silicon film;
A third step of forming a sidewall on the side surface of the gate electrode after the second step, and a self-aligned source diffusion layer and a self-aligned impurity by ion implantation of an impurity of the opposite conductivity type after the third step. Forming a drain diffusion layer and simultaneously introducing an impurity of the opposite conductivity type into the polycrystalline silicon film, and forming an effective region near the interface with the gate insulating film in the polycrystalline silicon layer of the gate electrode. Is formed in the thickness direction of the gate electrode so as to minimize the concentration of the impurity, and the effective concentration of the impurity of the opposite conductivity type near the interface with the gate insulating film is formed. Is a concentration at which a depletion layer is formed near the interface with the gate insulating film in the gate electrode by applying a high electric field.
A field-effect transistor.

[0014]

Next, an embodiment of the present invention will be described with reference to the drawings.

<< First Embodiment >> FIG. 1 shows a first embodiment of the present invention.
The manufacturing steps of the MOS field effect transistor according to the first embodiment are shown in order. Here, the case of an N-channel MOS type field effect transistor will be described.

In this transistor, a gate insulating film 12 is formed on the surface of a P-type semiconductor substrate 11, and a gate polycrystalline silicon electrode 13 which is a gate electrode made of polycrystalline silicon is provided on the gate insulating film 12. On the side surface of the gate polycrystalline silicon electrode 13, a sidewall 16 made of silicon oxide is formed. The polysilicon layer constituting the gate polysilicon electrode 13 has N
A type impurity is introduced, and its impurity concentration profile is controlled so as to have a continuous concentration gradient that is minimized near the interface with the gate insulating film 12.

The portions on both sides of the gate polycrystalline silicon electrode 13 in the semiconductor substrate 11 are a drain region and a source region, respectively. The drain region is relatively deep N
^{The structure is such that the +} -type drain diffusion layer 17 and the relatively shallow N-type drain-side LDD layer 14 overlap each other, and the end position of the drain diffusion layer 17 on the gate polycrystalline silicon electrode 13 side is planar. In general, this corresponds to the intersection of the surface of the sidewall 16 and the surface of the gate insulating film 12. On the other hand, the end of the drain-side LDD layer 14 on the side of the gate polysilicon electrode 13 extends so as to overlap a part of the gate polysilicon electrode 13 in a planar position. Similarly, the source region has a structure in which a relatively deep N ⁺ -type source diffusion layer 18 and a relatively shallow N-type source-side LDD layer 15 are overlapped. The end position on the 13 side generally corresponds to the position of the intersection of the surface of the sidewall 16 and the surface of the gate insulating film 12 in plan view. Source side LDD layer 15
The end on the gate polycrystalline silicon electrode 13 side extends so as to overlap a part of the gate polycrystalline silicon electrode 13 in a planar position. Here, LDD (Lightly Doped Drai
n) A layer is originally a part of the drain region, and is a region in which the impurity concentration is reduced in order to reduce the electric field near the drain, but the source region is also self-aligned at the same time as the drain region. In general, the low impurity concentration region formed on the source region side is also referred to as an LDD layer.

Next, the manufacturing process of the MOS field effect transistor will be described. First, a gate insulating film 12 is formed on a P-type semiconductor substrate 11 by a thermal oxidation method. Here, the thickness of the oxide film (the thickness of the gate insulating film 12) is set to 10 to 12 nm. A non-doped polycrystalline silicon layer is formed on the entire surface and patterned into a desired gate electrode shape to form a gate polycrystalline silicon electrode 13. In addition,
The thickness of the polycrystalline silicon layer is 150 nm to 200 nm. Then, phosphorus (P), which is an N-type impurity, is ion-implanted over the entire surface. Here, the ion implantation conditions are preferably such that the implantation energy is 30 keV and the dose is about 1 × 10 ¹⁴ cm ⁻² . Thereafter, annealing is performed at 900 ° C. for about 10 minutes in an N ₂ atmosphere. As a result, the phosphorus introduced into the polycrystalline silicon is diffused throughout the polycrystalline silicon and has a substantially uniform concentration distribution. In this example, the concentration is 8 × 10 ¹⁸ cm ⁻³ . The phosphorus implanted in the semiconductor substrate 11 forms a drain-side LDD layer 14 and a source-side LDD layer 15.
This state is shown in FIG.

Next, a silicon oxide film is grown to a thickness of 100 nm over the entire surface by a vapor phase growth method, and is etched back by a highly anisotropic etching method such as a reactive ion etching (RIE) method to form a gate polycrystal. A side wall 16 is formed on a side wall of the silicon electrode 13.
Next, arsenic (As), which is an N-type impurity, is ion-implanted under the conditions of an implantation energy of 50 keV and a dose of 2 to 4 × 10 ¹⁵ cm ⁻² to introduce arsenic into the gate polysilicon electrode 13 and to form a drain diffusion layer. 17 and a source diffusion layer 18 are formed. After this, RTA (rapid thermal an
The implanted impurities are activated by a nealing (rapid thermal annealing) method or the like. If necessary, heat treatment is performed using a furnace tube. Here, in the gate polycrystalline silicon electrode 13 due to the previously implanted phosphorus, the minimum value of the N-type impurity concentration is 8 ×
It is about 10 ¹⁸ cm ^−3, and arsenic implanted for forming the drain diffusion layer 17 and the source diffusion layer 18 is added to this. Thus, as shown in FIG. 1B, the MOS transistor of the present embodiment is manufactured.

FIG. 2 shows the MOS thus manufactured.
2 shows the N-type impurity concentration in the gate polycrystalline silicon electrode 13 of the field-effect transistor. Here, an impurity concentration profile in the XY section in FIG. 1B when the thickness of the gate polycrystalline silicon electrode 13 is 150 nm is shown. In the vicinity of the electrode surface X, the impurity concentration is as high as 1 × 10 ²⁰ to 1 × 10 ²¹ cm ^-3 , whereas in the vicinity Y of the interface with the gate insulating film 12, the impurity concentration is 8 × 1 20.
The density is about 0 ¹⁸ to 1 × 10 ¹⁹ cm ^−3, and there is a concentration gradient that is continuous with the impurity concentration so that the concentration becomes minimum near the interface with the gate insulating film 12.

Next, the operation of the field effect transistor will be described with reference to FIG. FIG. 3 shows a state where a bias is applied to this field-effect transistor. Here, in the case where the thickness of the gate insulating film 12 is set to about 11 nm and the internal logic circuit is operated at a high speed at a power supply voltage of 3.3 V, a transistor of an interface portion to a circuit having a power supply voltage of 5 V according to this embodiment The case where the MOS type transistor is applied will be described.

The drain voltage V _D =
It is assumed that 5 V is applied and gate polycrystalline silicon electrode 13 and source diffusion layer 18 are at the ground potential. Further, the gate polycrystalline silicon 1 near the interface with the gate insulating film 12 is formed.
3 has an N-type impurity concentration of 8 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³
It is assumed to be about. Under such conditions, where the gate polysilicon electrode 13 and the drain-side LDD layer 14 overlap, a depletion layer 21 of about 10 nm is formed.
It is formed in gate polycrystalline silicon electrode 13 so as to be in contact with gate insulating film 12. As a result, the capacitor formed by the gate insulating film 12 and the capacitor formed by the depletion layer 21 exist in series, and the power supply voltage 5V is divided by these two capacitors. When the depletion layer 21 in the gate electrode is 10 nm as in this example, about 3.8 V is applied to the gate insulating film 12 and 1.2 V is applied to the depletion layer 21, and 5 V is applied to the gate insulating film 12. so that the drain voltage V _D is not applied directly.

<< Second Embodiment >> Next, a second embodiment of the present invention will be described.
An embodiment will be described. Here, a description will be given of a manufacturing process for forming a high-speed logic unit to be operated at high speed and a high-voltage interface unit serving as an interface to a circuit with a higher power supply voltage in the same semiconductor chip.

The difference from the first embodiment is that FIG.
As shown in (A), the gate polysilicon electrode 22 of the MOS field effect transistor in the high voltage interface section
On the other hand, impurities of opposite conductivity type such as boron (B)
That is, about 10 ¹⁸ cm ^{-3 is} introduced. On the other hand, the gate polysilicon electrode 13 of the MOS field effect transistor of the high-speed logic section is formed of non-doped polysilicon. After forming the gate polycrystalline silicon electrodes 13 and 22 in this manner, phosphorus (P) is ion-implanted,
A drain-side LDD layer 14 and a source-side LDD layer 15 are formed, and each gate polycrystalline silicon electrode 13, 2 is formed.
2 to introduce phosphorus.

Subsequently, as in the case of the first embodiment, a side wall 16 made of an oxide film is formed for each of the gate polycrystalline silicon electrodes 13 and 22, and as shown in FIG. At the same time, arsenic (As) is ion-implanted with a high concentration into the transistors of the high-speed logic unit and the high-voltage interface unit. As a result, high-concentration N-type impurities are introduced into the gate polycrystalline silicon electrode 13 of the transistor in the high-speed logic section, and the gate resistance is reduced, so that the transistor can operate at high speed. On the other hand, in the transistor of the high-voltage interface section, the arsenic concentration near the interface between the gate polycrystalline silicon electrode 22 and the gate insulating film 12 is canceled out by boron introduced in advance, and as a result, depletion is likely to occur near this interface. Has become. Therefore, application of an overvoltage to the gate insulating film 12 can be prevented.

[0026]

As described above, according to the present invention, the impurity in the gate polysilicon electrode is made to have the same conductivity type as that of the impurities in the source region and the drain region, and the depth of the impurity in the gate electrode is further reduced. In the case where a high voltage is applied between the drain and the gate electrode, the concentration distribution in the direction is inclined so that the concentration distribution in the direction is inclined so that the concentration becomes minimum near the interface with the gate insulating film. Depletion of the polycrystalline silicon prevents a high voltage from being directly applied to the gate insulating film. This has the effect of enabling compatibility between high-speed logic circuits and high-voltage interface circuits without sacrificing microfabrication or gate oxide film reliability, while minimizing the increase in manufacturing processes. is there.

[Brief description of the drawings]

FIGS. 1A and 1B are cross-sectional views illustrating a MOS field-effect transistor according to a first embodiment of the present invention by showing manufacturing steps in order.

FIG. 2 is a graph showing an impurity profile in a gate polysilicon electrode of the MOS field effect transistor shown in FIG.

FIG. 3 is a diagram illustrating the operation of the MOS field effect transistor shown in FIG.

FIGS. 4A and 4B are cross-sectional views illustrating a semiconductor device according to a second embodiment of the present invention by sequentially showing manufacturing steps.

5A is a cross-sectional view illustrating a configuration of a conventional MOS field effect transistor, and FIG. 5B is a diagram illustrating an operation of the MOS field effect transistor illustrated in FIG. 5A.

[Explanation of symbols]

 Reference Signs List 11 semiconductor substrate 12 gate insulating film 13, 22 gate polycrystalline silicon electrode 14 drain side LDD layer 15 source side LDD layer 16 side wall 17 drain diffusion layer 18 source diffusion layer 19 low impurity concentration polysilicon gate layer 20 high impurity concentration polysilicon Gate layer 21 Depletion layer

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-179768 (JP, A) JP-A-4-142777 (JP, A) JP-A-5-55560 (JP, A) JP-A-3-3 148135 (JP, A) JP-A-2-265248 (JP, A)

Claims (5)

(57) [Claims] A semiconductor substrate of one conductivity type; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the gate insulating film and at least a part of which is formed of a polycrystalline silicon layer; In a MOS field effect transistor formed in a substrate and having a source region and a drain region of a conductivity type opposite to that of the semiconductor substrate, an interface between the gate insulating film and a polycrystalline silicon layer of the gate electrode is formed. There is a continuous concentration gradient of the opposite conductivity type impurity in the thickness direction of the gate electrode so that the effective concentration is minimized in the vicinity, and the gate in the gate electrode is formed by applying a high electric field. A MOS type field effect transistor wherein a depletion layer is formed near an interface with an insulating film. 2. A semiconductor substrate of one conductivity type; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the gate insulating film and at least partially formed of a polycrystalline silicon layer; In a method of manufacturing a MOS field effect transistor formed in a substrate and having a source region and a drain region of a conductivity type opposite to that of the semiconductor substrate, after forming the gate insulating film on the surface of the semiconductor substrate, A first step of forming a crystalline silicon film and processing the polycrystalline silicon film into the shape of the gate electrode; and ion-implanting the impurity of the opposite conductivity type after performing the first step. Forming a source region and a drain region, and simultaneously introducing the opposite conductivity type impurity into the polycrystalline silicon film. A continuous concentration gradient of the impurity of the opposite conductivity type in the thickness direction of the gate electrode so that the effective concentration is minimized in the vicinity of the interface with the gate insulating film in the pole polycrystalline silicon layer. Is formed, and the effective concentration of the opposite conductivity type impurity near the interface with the gate insulating film is depleted near the interface with the gate insulating film in the gate electrode by applying a high electric field. A method for manufacturing a MOS field effect transistor, comprising manufacturing a MOS field effect transistor having a concentration at which a layer is formed. 3. A semiconductor substrate of one conductivity type, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film and at least partially formed of a polycrystalline silicon layer, A source region and a drain region formed in the substrate and having a conductivity type opposite to that of the semiconductor substrate, wherein the source region has a relatively high impurity concentration and a source diffusion layer having a relatively low impurity concentration; Wherein the drain region comprises a drain diffusion layer having a relatively high impurity concentration and a drain side LDD layer having a relatively low impurity concentration, and the source diffusion layer and the drain diffusion layer overlap with the gate electrode. The source side LDD layer and the drain side LDD layer do not overlap with the gate electrode via the gate insulating film. In the method for manufacturing a MOS field effect transistor, a polycrystalline silicon film is formed after the gate insulating film is formed on the surface of the semiconductor substrate, and the polycrystalline silicon film is processed into a shape of the gate electrode. After the first step and the first step, the source-side LD is self-aligned by ion-implanting the impurity of the opposite conductivity type.
A second step of forming a D layer and the drain-side LDD layer, and simultaneously introducing the impurity of the opposite conductivity type into the polycrystalline silicon film; and a sidewall on the side surface of the gate electrode after performing the second step. Forming the source diffusion layer and the drain diffusion layer in a self-aligned manner by ion-implanting the impurity of the opposite conductivity type after performing the third step. A fourth step of introducing a conductive type impurity into the polycrystalline silicon film, wherein the effective concentration is minimized in the polycrystalline silicon layer of the gate electrode near the interface with the gate insulating film. As a result, a continuous concentration gradient of the opposite conductivity type impurity is formed in the thickness direction of the gate electrode, and the effective concentration of the opposite conductivity type impurity near the interface with the gate insulating film is formed. But, Manufacturing a MOS field-effect transistor having a concentration at which a depletion layer is formed near an interface between the gate electrode and the gate insulating film in the gate electrode by applying an electric field; Method. 4. The method for manufacturing a MOS field effect transistor according to claim 2, wherein the polycrystalline silicon film formed in the first step is non-doped. 5. The polycrystalline silicon film formed in the first step includes the one conductivity type impurity, and the second conductivity type in the polycrystalline silicon film is subjected to ion implantation in the second step. 4. The method for manufacturing a MOS field effect transistor according to claim 2, wherein impurities of the type are eliminated.