JP3275310B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device manufactured using a scan stepper.

[0002]

2. Description of the Related Art FIG. 5 is a schematic view of a chip layout of a conventional semiconductor device manufactured using a scan stepper. In the figure, the left side shows the layout on the mask, and the right side shows the corresponding actual device shape (pattern shape on the wafer). The exposure of the scan stepper is performed by scanning in the vertical direction in the figure (here, from bottom to top).

In the MOSFET on the chip, the longitudinal direction of the gate pattern is arranged in a direction orthogonal to the scan stepper exposure scanning direction. At this time, the gate pattern formed on the wafer by the scan stepper is:
The shape is distorted under the influence of the aberration (coma aberration) of the projection lens of the exposure apparatus, and the line width on the chip center line side is narrow.

FIGS. 6 and 7 are enlarged views of the MOSFET portion of FIG. FIG. 6 shows a layout diagram on a mask, and FIG. 7 shows a corresponding actual device shape (pattern shape on a wafer). Each gate pattern is arranged in a direction orthogonal to the scan stepper exposure scanning direction, and the pattern line width on the chip center line side is narrow. In particular, the portion of the gate pattern protruding from the MOSFET channel to the element isolation region has a discontinuous shape, and the pattern becomes thinner and the protrusion retreats significantly. Here, Tr1 and Tr2 and Tr3 and Tr
4 is, for example, N of the flip-flop in the sense amplifier circuit.
Like a chMOSFET, it is a MOSFET that functions as a pair on a circuit.

[0005]

However, in the above-mentioned prior art, there is a problem that the characteristics of the MOSFET vary greatly. In particular, variations in the characteristics of the paired MOSFETs are likely to occur, deteriorating the circuit characteristics. Further, this problem is caused by a MOSFET disposed at an end of the reticle in a direction orthogonal to the scanning direction.
It was easy to occur in.

[0006] The above-mentioned problem occurs because pattern distortion is caused by aberration (coma aberration) of the projection lens of the scan stepper. Therefore,
If the optical axis is near the center of the reticle, MOS transistors particularly arranged on both ends of the reticle in the direction orthogonal to the scanning direction
FET is affected. That is, in FIGS. 5 and 7,
The gate pattern formed on the wafer is distorted under the influence of the aberration (coma aberration) of the projection lens of the exposure apparatus, and the pattern tends to be thinner on the chip center side. The portion of the gate pattern protruding from the MOSFET channel toward the element isolation region has a discontinuous shape, and the pattern becomes thinner and the protrusion retreats significantly. Therefore, in this part MOSFET
Short channel effect appears, the degree of which is likely to vary, and M
OSFET characteristic variations occur. Pair MOS
Also for the FETs (Tr1, Tr2), characteristic variations due to this will occur. Especially, pair MOS
In the case of the FETs (Tr3, Tr4), since this tendency appears only in Tr4, the characteristic variation is remarkable.

When the optical axis is deviated from the chip center line (reticle center line), for example, when the optical axis is on the right side of the chip center line in FIG.
ET has little effect, but MO on the left side of the chip center line
In an SFET, the effect of pattern distortion increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to improve the circuit characteristics of a semiconductor device manufactured by using a scan stepper, in particular, by suppressing variation in characteristics of paired transistors. It is in.

[0009]

The present invention provides the following semiconductor devices (1) to (4) to achieve the above object. (1) The gate and drain of the first MOSFET are respectively
Connected to the drain and source of the second MOSFET
Has a transistor pair, in a semiconductor device manufactured using a scanning stepper, before in a direction perpendicular to the scanning direction during scanning stepper exposure (scanning direction)
The gate patterns of the first and second MOSFETs are arranged in the longitudinal direction , and the portions of the gate patterns of the first and second MOSFETs where contact holes are arranged are both chips. A semiconductor device which is placed on a center line side. (2) The semiconductor device according to (1), wherein the first and second MOSFETs are arranged on a reticle at an end in a direction orthogonal to the scanning direction. (3) There are a plurality of chips on the reticle, and the first and second chips are attached to an end chip in a direction orthogonal to the scanning direction .
The semiconductor device according to (1), wherein two MOSFETs are arranged. (4) The first and second MOSFETs are sense amplifiers
The semiconductor device according to any one of (1) to (3), being a pair transistor of a flip-flop in a circuit .

[0010]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic view of a chip layout of a semiconductor device of the present invention manufactured using a scan stepper. In the drawing, the left side shows the layout on the mask, and the right side shows the corresponding actual device shape (finished pattern shape on the wafer). The exposure of the scan stepper is performed by scanning in the vertical direction in the figure (here, from bottom to top).

In the figure, among the MOSFETs on the chip 1, those located at the left and right ends in the chip have the longitudinal direction of the gate pattern 3 arranged in a direction orthogonal to the scan stepper exposure scanning direction. The portion of the gate pattern 3 where the contact pattern 4 is arranged is located on the chip center line side.

FIGS. 2 and 3 are enlarged views of the MOSFET portion of FIG. FIG. 2 shows a layout diagram on a mask, and FIG. 3 shows a corresponding actual device shape (finished pattern shape on a wafer). Each of the gate patterns 13 and 17 is arranged in a direction orthogonal to the scan stepper exposure scanning direction (vertical direction in the figure), and a portion where the contact patterns 14 and 18 are arranged is located on the chip center line side. Here, Tr1 and Tr2 are MOSFETs that function as a pair on a circuit such as an Nch MOSFET of a flip-flop, and have respective gates,
The drain is connected to the complementary signal lines 11 and 15.

In FIG. 3, in the completed gate pattern 17, the line width on the side opposite to the chip center (right side in the figure) tends to be large and the line width on the chip center side (left side in the figure) tends to be small. Since the contact pattern 18 is arranged on the chip center side of the gate pattern 17 and the gate pattern is set to be wide on the mask pattern at this portion, the tendency of the gate pattern line width on the chip center side to be narrow is not visible.

According to the present embodiment, variation in the characteristics of the paired transistors can be suppressed, and the circuit characteristics can be improved. This is because the influence of pattern distortion due to aberration (coma aberration) of the projection lens of the scan stepper is less likely to occur. That is, in FIGS. 1 and 3, the gate pattern formed on the wafer is distorted in shape due to the influence of the aberration (coma aberration) of the projection lens of the exposure apparatus, but the pattern tends to be thin. Since there is a pattern wider than the gate length corresponding to the contact arrangement on the chip center side, the pattern is prevented from being thinned. Also in the paired MOSFETs (Tr1, Tr2), the gate patterns of the pair are aligned in the same direction, and similarly, pattern narrowing due to coma aberration is avoided, so that characteristic variations due to this are suppressed.

The influence of coma aberration is caused by the MOS disposed at the end of the reticle in the direction perpendicular to the scanning direction.
Since it is particularly large in an FET, it is effective in suppressing variations. When the optical axis deviates from the chip center line (reticle center line), for example, in the case where the optical axis is on the right side of the chip center line in FIG. The MOSFET located on the left side of the center line of the chip is greatly affected by the pattern distortion, and is effective in suppressing the variation.

FIG. 4 shows, as another embodiment, a chip layout when a plurality of chips are provided on a reticle. Here, six chips A to F are arranged on the reticle 20, and patterning is performed on the wafer in units of six chips. In the MOSFETs disposed at the ends of the chips A, D, C, and F at the ends in the direction perpendicular to the scan stepper exposure scanning direction, the gate pattern 23
The longitudinal direction is arranged in a direction perpendicular to the scanning direction. The portion of the gate pattern 23 where the contact pattern 24 is arranged is located on the reticle center line side.

[0017]

As described above, according to the present invention, in a semiconductor device manufactured using a scan stepper, in particular, variation in characteristics of a pair transistor can be suppressed, and circuit characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic view of a chip layout of a semiconductor device of the present invention manufactured using a scan stepper.

FIG. 2 is a layout diagram on a mask in which the MOSFET portion of FIG. 1 is enlarged.

FIG. 3 is a diagram showing an actual device shape corresponding to the layout diagram of FIG. 2;

FIG. 4 is a chip arrangement diagram when a plurality of chips are present on a reticle in the present invention.

FIG. 5 is a schematic view of a chip layout of a conventional semiconductor device manufactured using a scan stepper.

FIG. 6 is a layout diagram on a mask in which the MOSFET portion of FIG. 5 is enlarged.

7 is a diagram showing an actual device shape corresponding to the layout diagram of FIG. 6;

[Explanation of symbols]

 1 Chip 2 Diffusion layer pattern 3 Gate pattern 4 Contact pattern 11 Complementary signal line 12 Diffusion layer pattern 13 Gate pattern 14 Contact pattern 15 Complementary signal line 16 Diffusion layer pattern 17 Gate pattern 18 Contact pattern 20 Reticle 21 Chip 22 Diffusion layer pattern 23 Gate pattern 24 Contact pattern

Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 21/8234 H01L 21/027 H01L 21/28 H01L 27/088

Claims (4)

(57) [Claims] 1. A gate and a drain of a first MOSFET.
Are connected to the drain and source of the second MOSFET, respectively.
In a semiconductor device having a paired transistors connected and manufactured using a scan stepper, a gate pattern of the first and second MOSFETs is arranged in a direction orthogonal to a scan direction (scan direction) at the time of scan stepper exposure. The first and second MOSFEs are arranged in the longitudinal direction.
A semiconductor device, wherein the portions of the T gate pattern where the contact holes are arranged are both located on the chip center line side. 2. The semiconductor device according to claim 1, wherein said first and second MOSFETs are arranged on an end of a reticle in a direction orthogonal to said scanning direction. 3. A plurality of chips on a reticle, and the chip at an end in a direction orthogonal to the scanning direction is
2. The semiconductor device according to claim 1, wherein first and second MOSFETs are arranged. Wherein said first and second MOSFET is Sen
4. The semiconductor device according to claim 1, wherein the semiconductor device is a pair transistor of a flip-flop in the amplifier circuit . 5.