JP3276254B2 - Horizontal sync pulse separation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal synchronizing pulse separating circuit for separating only a horizontal synchronizing pulse from a composite synchronizing signal of a television picture signal.

[0002]

2. Description of the Related Art FIG. 4 is an external view of a small liquid crystal television. The small liquid crystal television 1 includes a liquid crystal display panel 1a for displaying an image, a printed wiring board 1b provided on the back side of the liquid crystal display panel 1a, and an outer frame 1c. The printed wiring board 1b is formed in substantially the same shape as the liquid crystal display panel 1a, and various circuits necessary for displaying an image on the liquid crystal display panel 1a are mounted. In such a small liquid crystal television 1, the image display size of the liquid crystal display panel 1a is very small, about 5 inches, and the external dimensions and thickness dimension of the printed wiring board 1b are severely restricted. The printed wiring board 1b includes, in addition to a liquid crystal driving circuit for driving the liquid crystal display panel 1a, a tuner circuit for processing a high-frequency signal, an audio circuit, a luminance signal processing circuit for processing a luminance signal for forming a video signal, and a color signal processing circuit. Many circuits for processing various signals, such as a color signal processing circuit for processing signals and a power supply circuit, are mounted.

[0003]

Incidentally, there is a horizontal synchronizing pulse separating circuit which separates only a horizontal synchronizing signal component from a composite synchronizing signal forming a television picture signal as a part of the liquid crystal driving circuit. Conventionally, this horizontal sync pulse separation circuit
It has been configured by combining an analog integrating circuit and a commercially available dedicated IC. For this reason, there is a problem that the mounting area of the horizontal synchronization pulse separation circuit cannot be suppressed. Further, the conventional horizontal synchronizing pulse separation circuit has a problem in that the characteristics change due to the fluctuation of the ambient temperature and the power supply voltage and the influence of noise.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and is intended to provide a horizontal synchronization pulse separation circuit which can reduce the mounting area and operate stably with respect to fluctuations in ambient temperature, power supply voltage, and noise. For the purpose of providing.

[0005]

Horizontal sync pulse separation circuit according to claim 1 Means for Solving the Problems] In order to achieve the above object, Horizontal Sync
Counting clock pulses in synchronization with the
More has a horizontal synchronizing signal and the same frequency, a first pulse having a level displacement point before and after the serration present in at least a vertical sync signal, synchronized with the first pulse
Counting the number of clock pulses to have the same frequency as the horizontal synchronizing signal and at least the first
A counter for generating a second pulse having a level displacement point before the displacement point of the pulse of
Ri by the taking the logical sum of the pulse, the equalizing pulse and serration not synchronized with the horizontal synchronizing signal thereby removing respectively from said composite synchronizing signal, generating an unnecessary pulse not synchronized with the horizontal synchronizing signal within the vertical synchronizing signal a first OR gate which receives as input said composite synchronizing signal and the second pulse, and removing pulse generation means for generating a vac pulse timing including said unnecessary pulse, said dividing <br/> pulse logical sum of the output signal of the first OR gate
And a second OR gate for removing unnecessary pulses included in the output of the first pulse removing means.

[0006]

[0007]

According to a second aspect of the present invention, in the horizontal synchronizing pulse separating circuit according to the first aspect , the removal pulse generating means includes an inverter for inverting the composite synchronizing signal;
An AND gate that takes the logical product of the second pulse and the output signal of the inverter; and a high voltage applied as data, and the output signal of the AND gate as a clock pulse;
And a delay-type flip-flop that inputs the composite synchronization signal as a clear signal.

[0009]

According to the horizontal synchronizing pulse separation circuit of the present invention, a horizontal synchronizing signal can be obtained in a video signal period in a composite synchronizing signal separated from a television video signal. In the vertical blanking period, equivalent pulses and serrations not synchronized with the horizontal synchronization signal are removed, and only pulses synchronized with the horizontal synchronization signal are obtained. Therefore, a continuous horizontal synchronization pulse is obtained in synchronization with the horizontal synchronization signal in the video signal period and the vertical blanking period.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the horizontal synchronizing pulse separating circuit according to the present invention will be described below in detail with reference to FIGS. Here, FIG. 1 is a diagram showing a configuration of a horizontal synchronizing pulse separation circuit of the present embodiment, and FIG. 2 is a diagram showing a waveform near a vertical blanking period of a first field of a TV video signal conforming to the NTSC system. FIG. 3 is a diagram showing a waveform near the vertical blanking period of the second field.

In FIG. 1, a negative composite sync signal A (see FIGS. 2 and 3) separated from a television video signal is input to an input terminal a. This composite synchronizing signal A is 1
It is roughly constituted by a horizontal synchronizing signal A1 arranged every horizontal scanning period (hereinafter abbreviated as 1H) and a vertical synchronizing signal A2 having a pulse width of 3H. Further, serrations A3 are inserted into the vertical synchronization signal A2 at 0.5H intervals. In an equivalent pulse period before and after the vertical synchronization signal A2,
The equivalent pulse A4 is inserted at intervals of 0.5H. That is, the composite synchronizing signal A is formed such that the time of the falling edge of each horizontal synchronizing signal A1 is 1H interval, and in the vertical synchronizing signal A2 and the equivalent pulse period,
Since the serration A3 and the equivalent pulse A4 are inserted, the time of the falling edge portion is formed to be 0.5H intervals.

The composite synchronization signal A is input to the counter 1. The counter 1 is configured to start counting clock pulses in synchronization with the falling edge of the horizontal synchronizing signal A1, and the counter 1 corresponds to about 0.25H from the falling edge of the horizontal synchronizing signal A1. And outputs a signal B (see FIGS. 2 and 3) which falls when the number of clock pulses corresponding to about 0.5H is counted. Here, since the counter 1 is configured not to operate on a pulse (equivalent pulse and serration not synchronized with the horizontal synchronization signal A1) input within 0.5H after the signal B rises, the counter 1 is vertically operated. The signals B are output at 1H intervals during the blanking period. Also, counter 1
Starts a counting operation in synchronization with the rising edge of the signal B, and starts counting when the number of clock pulses corresponding to the time obtained by subtracting the pulse width of the horizontal synchronizing signal A1 from 0.5H rises. When the number of clock pulses corresponding to the pulse width of the signal A1 is counted, a falling signal C (see FIGS. 2 and 3) is output.

The OR gate 2 comprises a composite synchronization signal A and a signal B.
And outputs a signal D (see FIGS. 2 and 3). This signal D is a signal in which the serration A3 and the equivalent pulse A4 that are not synchronized with the horizontal synchronization signal A1 during the vertical synchronization signal A2 and the equivalent pulse period are removed from the composite synchronization signal A. However, the signal D includes unnecessary pulses (a), (b), and (c) which are not synchronized with the horizontal synchronization signal A1, and is used to obtain the signal G (the horizontal synchronization pulse finally obtained). These unnecessary pulses (a),
It is necessary to remove (b) and (c).

The components described below are provided to remove the unnecessary pulses (a), (b), and (c) from the signal D. The AND gate 3 outputs the composite synchronization signal A
Is ANDed by the inverter 4 with the signal C to output the signal E. This signal E is a signal of only serrations A3 arranged at 1H intervals as shown in FIGS. Delay type flip-flop 5
(Hereinafter, abbreviated as D-FF5), a signal E is input to a CK terminal as a clock signal, a composite synchronization signal A is input to a CLR terminal, and “H (high voltage)” is applied to a D terminal. . Then, the D-FF 5 reads the voltage “H” of the D terminal at the rising edge of the signal E, and clears the signal F at the falling edge of the serration A3 of the composite synchronization signal A to output the signal F (see FIGS. 2 and 3). I do. The signal F obtained in this manner includes the unnecessary pulses (a), (b),
(C) rises at times t0, t2, and t4 before the occurrence, and the fall time t of the serration A3
The signals fall at 1, t3, and t5, respectively.

The OR gate 6 performs a logical OR operation of the signal F and the signal D including the unnecessary pulses (a), (b) and (c), and obtains the unnecessary pulses (a), (b) and (c). Is output to the output terminal b. This signal G is a signal of 1H interval in which the falling edge of each pulse is synchronized with the falling edge of the horizontal synchronization signal A1 even in the vertical blanking period.

According to the horizontal synchronizing pulse separating circuit having the above configuration, the following effects can be obtained since the circuit is constituted only by the digital circuit. (1) Since a circuit can be configured by one PLD (programmable logic device), the number of components can be reduced, and the mounting area on a printed wiring board can be reduced. (2) Low power consumption is possible. (3) The circuit operation becomes stable against changes in the ambient temperature. (4) The circuit operation is hardly affected by the power supply voltage. (5) It is hardly affected by noise.

Note that the horizontal synchronizing pulse separating circuit has a P
It can be applied to AL and SECAM television video signals.

[0018]

According to the horizontal synchronizing pulse separating circuit according to the present invention, the mounting area on the printed wiring board can be suppressed, the power consumption can be reduced, and the size of the small liquid crystal television can be further reduced. . In addition, since stable operation can be obtained with respect to fluctuations in the ambient temperature and the power supply voltage and intrusion of noise, it is possible to improve the operation performance of the small liquid crystal television.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a horizontal synchronization pulse separation circuit according to one embodiment of the present invention.

FIG. 2 shows a first example of the horizontal synchronization pulse separation circuit according to the embodiment.
6 is a timing chart illustrating an operation in a field.

FIG. 3 shows a second example of the horizontal synchronization pulse separation circuit according to the embodiment.
6 is a timing chart illustrating an operation in a field.

FIG. 4 is a diagram showing an example of the appearance of a small liquid crystal television.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Counter 2, 6 OR gate 3 AND gate 4 Inverter 5 D-FF a Input terminal b Output terminal

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N ^5/ 04-5/12

Claims (2)

(57) [Claims] 1. A clock synchronized with a horizontal synchronizing signal (A)
By counting the pulses, a first pulse (B) having the same frequency as the horizontal synchronizing signal and having at least a level displacement point before and after the serration present in the vertical synchronizing signal , Synchronous clock pulse
The by counting has the horizontal sync signal and the same frequency, and a second pulse (C) and a counter to produce a (1) having a level displacement point on at least the first pulse of the displacement temae , ORing a composite synchronization signal with the first pulse
I Ri, the equalizing pulse and serration not synchronized with the horizontal synchronizing signal thereby removing respectively from said composite synchronizing signal, a first OR gate for generating an unnecessary pulse not synchronized with the horizontal synchronizing signal within the vertical synchronizing signal (2) And a removal pulse (F) having the second pulse and the composite synchronizing signal as inputs and having a timing including the unnecessary pulse.
And removing pulse generation means for generating (4-5), the output signal of the said removing pulse first pulse rejection means
Ri by the taking the logical sum of the (D), the first Oage
Second ore for removing unnecessary pulses contained in the output of the
Horizontal synchronizing pulse separation circuit, characterized in that it comprises a chromatography preparative (6), the. 2. The apparatus according to claim 1, wherein said removal pulse generating means includes:
An inverter for inverting a period signal, and the second pulse
AND gate for ANDing with the output signal of the inverter
And a high voltage is applied as data, and the AND gate
Output clock signal as a clock pulse; and
Delay type free input that inputs a signal as a clear signal
And a flip-flop.
2. The horizontal synchronization pulse separation circuit according to claim 1, wherein