JP3277451B2 - Viterbi decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoder for equalizing the waveform of input data by a partial response method, and detecting a most probable data sequence by utilizing a correlation between data. The present invention relates to a Viterbi decoding device suitable for use in a magnetic recording / reproducing device, a magneto-optical recording / reproducing device, and the like.

[0002]

2. Description of the Related Art In recent years, in a recording / reproducing apparatus such as a digital video tape recorder or an optical disk apparatus, a PRM combining a partial response system and a Viterbi decoding system has been used.
L (Partial Response Maximum)
A signal processing technique called “m Liquidihood” system has attracted attention.

[0003] In other words, the PRML method uses partial response (PR: Partially) for equalization for adjusting the shape of a reproduced waveform.
al Response) method and the maximum likelihood (ML: Maximum Likelihood) for data detection.
d) A Viterbi decoding method, which is a decoding method, is used. By using such a PRML method, the recording density can be increased to about 1.2 to 1.5 times by signal processing without largely changing the existing recording / reproducing system. Further, the PRML method has a feature that waveform equalization can be performed while maintaining a high S / N ratio of data read from a recording medium, and a data error rate that does not cause a practical problem can be secured. ing.

For example, when digital data is recorded on an optical disk by an optical disk recording / reproducing apparatus using the PRML system, the digital data recorded on the optical disk is reproduced with a frequency characteristic having a high frequency drop due to the characteristics of a head amplifier. Is done.

[0005] The reproduced data I (t) is supplied to a Viterbi decoding device as shown in FIG. That is, FIG.
As shown in (1), reproduction data I (t) is supplied to an equalization circuit 201 having an arbitrary frequency characteristic,
Thus, the reproduced data I (t) is converted into output data r (t) having a fixed response, that is, an impulse response.
The output data r (t) obtained by the equalization circuit 201
Is an automatic gain control (AGC).
(in Control) circuit 202. AG
The C circuit 202 outputs the output data r from the equalization circuit 201.
The level variation of (t) is removed, and the output data r (t) from which the level variation is removed is supplied to the analog / digital (A / D) converter 203. The A / D converter 203 converts the output data r (t) from the AGC circuit 202 into digital data r
^d (t) and supplies the digital data r ^d (t) to the Viterbi decoding circuit 204.

Here, there are a number of methods for the partial response depending on what kind of intersymbol interference is given. These methods can be classified based on the impulse response of the output data r (t) obtained by the equalization circuit 201, and include PR (1,1) and PR (1,2,1). P
R (1, 1) is a method for suppressing high frequency component noise, and by using this method, the Viterbi decoding circuit 2
04 can be simplified. In addition, PR
When (1, 2, 1) is used, the Viterbi decoding circuit 204
Is complicated, but the S / N ratio can be further improved. Thus, depending on which method you use,
Which frequency component is emphasized is determined.

Since the output data r (t) obtained by waveform equalization using the partial response method has a known impulse response, the original digital data I ( t) can be inferred.

The Viterbi decoding circuit 204 uses this analogy to detect the most probable data sequence by effectively utilizing the correlation between data so that the effect of noise generated during recording and reproduction is minimized. That is, when there is intersymbol interference, the fact that only a limited pattern appears in the data sequence obtained by sampling the reproduced data is used to compare the pattern with the actual sampling result. Detect errors. Then, a pattern most similar to the sampling result is detected and its error is corrected. Further, a pattern that can be obtained by the reproduced data is determined not only by the intersymbol interference but also by the recording code. In consideration of such restrictions, the Viterbi decoding circuit 204 increases the accuracy of error correction.

[0009]

The error correction capability of the Viterbi decoding circuit 204 exhibits an effective effect because the spectrum of the noise contained in the digital data r ^d (t) supplied to the Viterbi decoding circuit 204 is effective. Is a characteristic having a characteristic of rising from a white level to a high frequency range. However, as shown in FIG. 10, the Viterbi decoding circuit 204
, Digital data r ^d directly from the A / D converter 203
(T) was supplied. That is, the Viterbi decoding circuit 20
The digital data r ^d (t) supplied to No. 4 had not been subjected to noise suppression processing. For this reason,
If the digital data r ^d (t) contains a large amount of low-frequency noise components, the error correction capability of the Viterbi decoding circuit 204 may be reduced, resulting in erroneous correction.

Therefore, the present invention has been made in view of the above-mentioned conventional circumstances, and has the following objects.

[0011] That is, an object of the present invention is to provide a Viterbi decoding device with improved error correction accuracy.

[0012]

In order to solve the above-mentioned problems, a Viterbi decoding apparatus according to the present invention comprises a first waveform equalizing means for equalizing a waveform of an input signal and converting the input signal into a signal having a partial response characteristic. Level control means for removing a level fluctuation of an output signal of the first equalization means; conversion means for digitizing an output signal of the level control means;
A noise suppression means for performing noise suppression processing on an output signal of the conversion means; and a Viterbi decoding circuit for decoding an output signal of the noise suppression means, wherein the noise suppression means performs the Viterbi decoding on the output signal of the conversion means. A sub-decoding means capable of more reliably decoding noise in a band in which a circuit is likely to malfunction; and a second means for re-equalizing an output signal of the sub-decoding means and converting the output signal into a signal having a partial response characteristic. Waveform equalizing means, first delay means for adjusting the phase of the output signal of the converting means to the phase of the output signal of the second waveform equalizing means, and the output signal of the second waveform equalizing means; First calculating means for obtaining a difference from the output signal of the first delay means, extracting means for extracting a low-frequency component of the output signal of the first calculating means, and phase of the output signal of the converting means A second delay unit that adjusts the phase of the output signal of the extraction unit; and a second delay unit that obtains a difference between the output signal of the extraction unit and the output signal of the second delay unit and supplies the difference signal to the Viterbi decoding circuit. 2 arithmetic means.

Further, a Viterbi decoding apparatus according to the present invention is characterized in that the sub-decoding means outputs the most significant bit data of the signal digitized by the conversion means as a generation signal.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

[0015] The Viterbi decoding device according to the present invention includes, for example,
High-frequency signal obtained from a magneto-optical disk
This is called F signal. 1) A device for equalizing the waveform of I _a (t) by a partial response (PR) method and decoding it by a Viterbi decoding method.
As shown in (1), an equalizer (EQ: Equalizer) 1 for equalizing the waveform of the input reproduced RF signal I _a (t),
Automatic gain control (AGC: Automatic Gain Cont) for removing the level fluctuation of the output signal of the equalizer 1
(A / D) converter 2, an analog / digital (A / D) converter 3 for digitizing an output signal of the AGC circuit 2,
The apparatus includes a noise suppression unit 4 that performs a noise suppression process on an output signal of the D converter 3 and a Viterbi decoding circuit 5 that decodes an output signal of the noise suppression unit 4.

The noise suppression means 4 includes a PR equalizer 41 for equalizing the waveform of the most significant bit data of the output signal of the A / D converter 3 by a partial response method, and an output signal of the A / D converter 3. Circuit (DL) 42 for delaying the phase of
And an adder 43 for obtaining a difference between the output signal of the PR equalizer 41 and the output signal of the delay circuit 42, and a filter (LPF: LF) for extracting a low-frequency noise component of the added output signal of the adder 43.
ow pass filter) 44 and a delay circuit (DL) 45 for delaying the phase of the output signal of the A / D converter 3
A delay circuit (DL) 46 for delaying the phase of the output signal of the delay circuit 45; an output signal of the filter 44 and the delay circuit 4
And an adder 47 for obtaining a difference from the output signal of the sixth output signal.

The Viterbi decoding device 100 shown in FIG.
Is, for example, as shown in FIG.
Of the Viterbi decoding device 10
0, the reproduced RF signal I _a (t) is the data S read from the magneto-optical disk 102 by the reproducing head PD.
(T) is a signal amplified by the reproduction amplifier 103.

Here, data S (t) to which data compression and an error code have been added are recorded on the magneto-optical disk 102. Further, the data S (t) has been subjected to a precoding process to prevent the propagation of a data error before recording the data on the magneto-optical disk 102. That is, in the data S (t), inter-symbol interference reverse to that given by the recording / reproducing system to the record-encoded data is added in advance. Thus, the waveform of the reproduction RF signal I (t) has a one-to-one correspondence with the recording waveform.

The data S (t) as described above is recorded on the magneto-optical disk 102 by the recording head LD driven by the drive circuit 101.
Play obtained from the RF signal I _a (t) is supplied to the equalizer 1 Viterbi decoder 100.

The equalizer 1 employs, for example, a transversal filter equalization system for equalizing a waveform using a transversal filter. This transversal filter is, as shown in FIG. 3, a digital filter FIR (Finite).
And a delay circuit D _{−N + 1 to} D _N−1 having a tap at each pulse transmission time interval T, and a weight coefficient cn (n = −N,...) For each tap. .., -1, 0, 1,..., N)
A gain control circuit C _-N -C _N multiplying the gain adjusting circuit C _-N
To C _N are added to each other. The number of taps in the transversal filter and the tap weighting factor cn are designed so that the waveform of the output signal I _b (t) of the equalizer 1 becomes a waveform of PR (1, 2, 1). ing.

As shown in FIG. 4, when the peak value of the output signal I _a (t) of the equalizer 1 is normalized by “2”, the characteristic of PR (1, 2, 1) becomes as follows. An amplitude of 1/2 (= 1) appears before and after the sampling timing. Further, as shown in FIG. 5, PR (1, 2, 1) has a delay element D for one sampling time and (1+
D) It can be said that this is a method for giving the ^two characteristics.

The weight coefficient cn of the tap is, for example, as shown in FIG. 6, the difference X between the input waveform and the target waveform at each discrimination point.
Are updated in accordance with the algorithm of the least squares error method (MSE method) so that the sum of the squares of ₁ , X ₂ , X ₃ ,... When the tap weight coefficient cn is updated, the reproduced RF signal I _a (t) is
The waveform is equalized while automatically adjusting to be close to the waveform of (1, 2, 1).

Thus, the target waveform PR
Since the equalized output signal I _b (t) obtained by waveform equalization close to (1, 2, 1) is not completely equalized as shown in FIG. 7, an equalization error Δk occurs. ing. The equalized output signal I _b (t) having such an equalization error Δk is represented by A
It is supplied to the GC circuit 2.

The AGC circuit 2 removes a level fluctuation of the equalized output signal I _b (t) from the equalizer 1. That is, AGC
The circuit 2 controls the amplitude characteristic and the DC component of the equalized output signal I _b (t) to an arbitrary reference level and supplies them to the A / D converter 3.

The A / D converter 3, a signal I _C for level variation in the AGC circuit 2 is removed (t), for example, converted into 8-bit digital data I _e (t), the digital data I _e (T) is supplied to the delay circuit 42 and the delay circuit 45, respectively, and the most significant bit (MSB) data I _{d of the} 8-bit digital data I _e (t) as shown in FIG.
(T) is supplied to the PR equalizer 41.

That is, in this embodiment, the most significant bit data I _d (t) is replaced with the 8-bit digital data I _d (t).
_The sub decoding result is different from that of the Viterbi decoding circuit 5 obtained from _e (t). Such a method of using the most significant bit data I _d (t) to obtain a sub-decoding result is based on a compact disk (CD: Compact d).
isc) It is generally used in players and the like, and is equivalent to a method of comparing reproduced RF signals at a center level.

Here, it is necessary that the sub-decoding result has a noise band component different from the noise band component affected by the Viterbi decoding circuit 5. Therefore, since the Viterbi decoding circuit 5 has a feature that is easily affected by the low-frequency noise component, the most significant bit data I _d (t) that is strong in the low-frequency noise component is used as a sub-decoding result. Also, the most significant bit data I _d (t)
Is generally a 10 ^-2 byte error rate (BER: By)
te Err Rate).

The PR equalizer 41 employs a transversal filter equalization method as in the case of the above-described equalizer 1, and outputs the most significant bit data I / O from the A / D converter 3.
Waveform equalization is performed on _d (t) so as to have a target PR (1, 2, 1) characteristic. Note that the waveform equalization processing in the PR equalizer 4 is the same as the waveform equalization processing in the equalizer 1, and the details are omitted. That is, the PR equalizer 41
Converts the most significant bit data I _d (t) into ideal 8-bit digital data I _f (t) having the target PR (1, 2, 1) characteristics as shown in FIG. The digital data _If (t) is supplied to the adder 43. here,
The digital data I _f (t) usually contains an error of about 10 ⁻² BER or less.

On the other hand, the delay circuit 42 is formed of a shift register, and receives the digital data I / D from the A / D converter 3.
_e (t) is delayed by a time equal to the delay amount of the PR equalizer 41, and the phase difference with the digital data _If (t) output from the PR equalizer 41 is set to "0". Then, the delay circuit 42 supplies the delayed digital data I _g (t) to the adder 43.

The adder 43 calculates the difference between the digital data I _g (t) from the delay circuit 42 and the digital data I _f (t) from the PR equalizer 41. That is, by subtracting the digital data I _g (t) from the digital data I _f (t), obtaining a noise component I _h of the signal supplied to the A / D converter _{3 I C (t) (t} ). However, this noise component I)
Contains an error corresponding to 10 ⁻² BER. Here, the noise component I _h (t) is 10 ⁻² generated by the PR equalizer 41.
It includes errors less than BER, but these errors include
Due to the characteristics of the most significant bit data I _d (t), it is assumed that it contains many high-frequency components and few low-frequency noise components. Such a noise component I _h (t) is supplied to the filter 44.

The filter 44, the low-frequency noise components I _i (t) extracted from the noise component I _h from the adder 43 (t), and supplies the low-frequency noise components I _i (t) to the adder 47 .

On the other hand, the delay circuit 45 has the same delay amount as the above-described delay circuit 42, and delays the digital data I _e (t) from the A / D converter 3 by a time equal to the delay amount. , And supplies the delayed digital data I _e (t) to the delay circuit 46 at the next stage.

The delay circuit 46 has a time equivalent to make the digital data I _e (t) from the preceding delay circuit 45 coincide with the inter-axis of the low-frequency noise component I _i (t) output from the filter 44. The delayed low-frequency noise component I
_i (t) is used as a low-frequency noise component I _j (t) as an adder 47.
To supply.

The adder 47 calculates the difference between the digital data I _e (t) from the delay circuit 46 and the low-frequency noise component I _j (t) from the filter 44. That is, the digital data I
By subtracting the low-frequency noise component I _j (t) from _e (t), the Viterbi decoding circuit 5 generates data I _k (t) containing a large amount of high-frequency noise component that exerts a strong effect. _k (t) is supplied to the Viterbi decoding circuit 5.

The Viterbi decoding circuit 5 detects the most probable data sequence based on the data I _k (t) from the adder 47.

For example, if the partial response characteristic is PR
The operation of the Viterbi decoding circuit 5 in the case of (1, 2, 1) will be described below.

As described above, PR (1, 2, 1) is affected by intersymbol interference over three sampling periods. Therefore, assuming that there is no noise source, the sampling value s (t) at a certain time is the data Sd (t) corresponding to a certain time and the data [Sd (t−2), Sd ( t-1)]. The combination of data at the last two sampling times is called a state. A state transition in a time-series manner is referred to as a “retless diagram”. FIG. 10 shows a retless diagram of PR (1, 2, 1). In this retres diagram, the number next to the arrow is data at the time of the end point of the arrow. The ideal sampling value y (k) that does not include noise for each transition state (i.e., arrow) from time k-1 to time k is determined by the partial response characteristic. FIG. 11 shows y (k) in PR (1, 2, 1).
Shows the value of When the actual sampling value in the transition from the time k-1 to the time k is s (k), the likelihood of the transition assuming that the transition is in a certain transition state on the Littres diagram is determined by the transition. It is called the state (ie, arrow) branch metric. As a specific evaluation value of the branch metric, for example, {y (k) -s (k)} ²
Is used. In this case, the smaller the branch metric, the higher the degree of certainty. A certain data series is represented as one path on the retres line. The sum of the branch metrics on this path is called the path metric of the path, and represents the likelihood of the data sequence corresponding to the path. The Viterbi decoding circuit is a circuit that obtains a path with a minimum path metric and outputs a data sequence corresponding to this path.

The specific configuration of the Viterbi decoding circuit 5 is shown in the block diagram of FIG. That is, the Viterbi decoding circuit 5
Is the branch metric calculation circuit 51 and the ACS (Ad
d, Compare, Select) circuit 52 and a path memory circuit 53.

The branch metric calculation circuit 51 calculates a branch metric corresponding to each state transition.

The ACS circuit 52 is a path metric memory for storing a path metric that reaches each state at time k-1, a circuit for adding a branch metric to the path metric at time k-1 according to the retless diagram, and a circuit at time k. The circuit includes a circuit for comparing the size of the path metric to be joined, and a circuit for selecting a path metric having a small value according to the comparison result. The selected value updates the path metric memory as a new path metric. The paths selected by the ACS circuit 52 in this way are only the number of states (4 in the case of PR (1, 2, 1)) at the current time, but these paths are called surviving paths. If you follow the surviving paths in the past, at one point you will find one path. Before this point, the path is determined as the path that minimizes the path metric.

The path memory circuit 53 includes the ACS circuit 5
2 stores the surviving path according to the result selected, and outputs the most probable data sequence corresponding to the determined path.

As described above, in this embodiment, the data I in which the low-frequency noise component has been
_{Since k} (t) is supplied to the Viterbi decoding circuit 5, it is possible to compensate for the shortcomings of the Viterbi decoding circuit 5 which is susceptible to low-frequency noise components, and the error correction capability of the Viterbi decoder 5 exhibits an effective effect. can do.

The present invention can be applied not only to the above-described Viterbi decoding device but also to a decoding device in which two decoding circuits having different effects depending on the noise band are combined. For example, a decoding circuit strong against low-frequency noise components may be used as a sub-decoding circuit for obtaining a sub-decoding result, and a decoding circuit strong against high-frequency noise components may be used instead of the Viterbi decoding circuit 5. As described above, since a decoding circuit effective for each noise band can be selected and used, a carrier-to-noise ratio (C / N: Carrier to Noise rate) is used.
Even when decoding a reproduced RF signal having poor io), a decoded output equivalent to that of the related art can be obtained. Therefore, information can be recorded at a higher density on a magneto-optical disk or the like.

That is, for an input signal having a poor C / N, B
Since a decoded signal having a low ER can be obtained, it is effective for a recording / reproducing apparatus having an increased recording density. In addition, since the decoding efficiency of the Viterbi decoding circuit can be theoretically increased beyond the limit, the application range of the Viterbi decoding device to which the PRML method combining the partial response method and the Viterbi decoding method is applied can be expanded.

In the above embodiment, the sub-decoding result has a noise band component different from the noise band affected by the Viterbi decoding circuit 5.
The present invention is not limited to this, and any circuit having a strong component in a noise band in which the Viterbi decoding circuit 5 easily malfunctions may be used.

[0046]

In the Viterbi decoding apparatus according to the present invention, the first
The waveform equalizing means equalizes the waveform of the input signal and converts it into a signal having partial response characteristics. The level control means removes a level fluctuation of the output signal of the first equalization means. The conversion means digitizes an output signal of the level control means. The sub-decoding means generates a noise signal in a band where the Viterbi decoding circuit is liable to malfunction from the output signal of the conversion means. The second waveform equalizer re-equalizes the output signal of the sub-decoder to convert the output signal into a signal having partial response characteristics. The first delay means is
The phase of the output signal of the conversion means is matched with the phase of the output signal of the second waveform equalization means. The first calculating means calculates a difference between the output signal of the second waveform equalizing means and the output signal of the first delay means. The extracting means extracts a low-frequency component of the output signal of the first calculating means. The second delay unit adjusts the phase of the output signal of the conversion unit to the phase of the output signal of the extraction unit. The second calculating means calculates a difference between the output signal of the extracting means and the output signal of the second delay means. The Viterbi decoding circuit decodes the output signal of the second operation means. Since the signal whose low-frequency noise component is suppressed is supplied to the Viterbi decoding circuit, the effect of the error correction capability of the Viterbi decoding circuit can be efficiently exhibited. Therefore, the accuracy of error correction can be improved.

In the Viterbi decoding device according to the present invention,
The sub-decoding means outputs the most significant bit data of the signal digitized by the conversion means as a generation signal. Since the most significant bit data is data that is hardly affected by a low-frequency noise component, a signal having a noise band different from the noise band of the output signal of the Viterbi decoding circuit is generated from the output signal of the conversion unit. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a Viterbi decoding device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a recording / reproducing system of a magneto-optical disk to which the Viterbi decoding device is applied.

FIG. 3 is a block diagram illustrating a configuration of a transversal filter.

FIG. 4 is a waveform chart for explaining characteristics of an equalization circuit in PR (1, 2, 1).

FIG. 5 is a circuit diagram for explaining characteristics of an equalization circuit in PR (1, 2, 1).

FIG. 6 is a waveform chart for explaining the least square error method.

FIG. 7 is a waveform diagram showing a signal in which an equalization error has occurred.

FIG. 8 is a waveform chart showing the most significant bit data.

FIG. 9 is a waveform chart showing a signal having a target waveform characteristic.

FIG. 10 is a retres diagram of PR (1, 2, 1).

FIG. 11 is a diagram illustrating a value of y (k) in PR (1, 2, 1).

FIG. 12 is a block diagram illustrating a specific configuration example of a Viterbi decoding circuit.

FIG. 13 is a block diagram illustrating a configuration of a conventional Viterbi decoding device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Equalizer 2 AGC circuit 3 A / D converter 4 Noise suppression means 5 Viterbi decoding circuit 41 PR equalizer 42,45,46 Delay circuit 43,47 Adder 44 Filter 100 Viterbi decoding device

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ identification code FI H04L 25/08 H04L 25/08 B (58) Fields investigated (Int.Cl. ⁷ , DB name) H03M 13/00 G11B 20 / 00 H04B 3/00 H04L 25/00 H04L 1/00

Claims (2)

(57) [Claims] 1. A first waveform equalizing means for equalizing a waveform of an input signal to convert the input signal into a signal having a partial response characteristic, and a level control means for removing a level fluctuation of an output signal of the first equalizing means. A conversion means for digitizing an output signal of the level control means, a noise suppression means for performing noise suppression processing on an output signal of the conversion means, and a Viterbi decoding circuit for decoding an output signal of the noise suppression means, The noise suppressing means includes: a sub-decoding means capable of more reliably decoding noise in a band in which the Viterbi decoding circuit easily malfunctions from an output signal of the conversion means; and a waveform output signal of the sub-decoding means. A second waveform equalizing means for re-equalizing and converting the signal into a signal having a partial response characteristic, and a phase of an output signal of the converting means being equal to the second waveform equalization First delay means for adjusting the phase of the output signal of the stage, first arithmetic means for calculating a difference between the output signal of the second waveform equalization means and the output signal of the first delay means, Extracting means for extracting a low-frequency component of the output signal of the first calculating means; second delay means for adjusting the phase of the output signal of the converting means to the phase of the output signal of the extracting means;
A Viterbi decoding device, comprising: a second operation unit that obtains a difference between an output signal of the extraction unit and an output signal of the second delay unit and supplies the difference signal to the Viterbi decoding circuit. 2. The Viterbi decoding device according to claim 1, wherein the sub-decoding means outputs the most significant bit data of the signal digitized by the conversion means as a generation signal.