JP3281204B2 - Wiring structure and method for forming via hole - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure particularly suitable for wiring of a semiconductor device, and to a via hole forming method for forming a via hole in the wiring structure.

[0002]

2. Description of the Related Art Conventionally, FETs have been used in GaAs ICs.
In the case where the source is grounded, the FET is provided on the substrate surface on the front side, and a via hole penetrating the substrate is formed immediately below the source electrode of the FET. Then, an earth electrode is provided on the back substrate surface, and the source electrode of the FET and the earth electrode are electrically connected via via holes.

[0003]

However, in the above-described conventional wiring structure, a via hole having a depth from the rear substrate surface to the source electrode must be provided directly below the source electrode in parallel with the active layer of the FET. The source electrode and the ground electrode cannot be electrically connected. Since such a deep via hole must be provided in parallel with the active layer, it is difficult to increase the integration density. Usually, a via hole is formed by wet etching.
This is because the diameter of the via hole increases as the depth of the via hole increases.

When the substrate is divided into IC chips,
In order to divide the chip so as not to damage the C chip, it is desired to increase the thickness of the substrate. However, the depth of the via hole is increased by the thickness of the substrate, and the via hole diameter is increased, so that the integration density cannot be increased.

In order to further enhance the heat radiation efficiency of the FET, it is preferable to provide a via hole directly below the active layer. However, in the conventional wiring structure, if the via hole is provided immediately below the active layer, the ground electrode is electrically connected to the active layer. Since the connection is made, the FET cannot be operated normally.

Further, in the FET, there is a problem that the potential of the active layer fluctuates due to the side gate effect or the back gate effect, and as a result, the electric characteristics of the FET fluctuate. Similar problems occur with electrical circuit elements other than FETs, such as bipolar transistors, diodes, inductors, capacitors or resistors. In order to prevent such a change in the electric characteristics, it is effective to stabilize the peripheral potential of the electric circuit element.

An object of the present invention is to provide a wiring structure capable of further increasing the integration density in order to solve the above-mentioned conventional problems, and further to form a via hole in this wiring structure. It is a second object of the present invention to provide a via hole forming method suitable for the above.

Another object of the present invention is to provide a wiring structure capable of increasing the integration density and stabilizing the peripheral potential of the electric circuit element.

[0009]

In order to achieve the first object, a wiring structure according to the first aspect of the present invention comprises a semiconductor substrate and n (n is a natural number) wirings stacked on the substrate surface. A laminate for wiring is constituted by the unit layer,
The wiring unit layer is constituted by a conductive layer and an insulating layer sequentially provided from the substrate surface side, and the wiring unit layer is formed to extend in a plane along the substrate surface.

[0010] According to such a wiring structure, an electric circuit element and a via hole are provided at any suitable position of the wiring laminate, and a desired electric circuit element and a conductive layer of a wiring unit layer corresponding to the element are formed. Can be electrically connected via a via hole provided between the element and the conductive layer. For example, an electric circuit element can be provided on the n-th wiring unit layer counted from the substrate surface side. Alternatively, an electric circuit element can be provided on a substrate surface or a surface layer thereof, and a wiring unit layer can be provided on the electric circuit element via an insulating layer. Alternatively, the electric circuit element can be provided on the substrate surface opposite to the substrate surface on which the wiring unit layer is provided or on the surface thereof. Alternatively, when a plurality of wiring unit layers are provided, an electric circuit element is provided on the insulating layer of the wiring unit layer,
Another wiring unit layer can be provided on the electric circuit element via an insulating layer.

In addition, since the wiring unit layer extends in a plane along the substrate surface, if the via hole and the conductive layer of the wiring unit layer overlap each other in a plan view, the via hole is formed. Even if you change the arrangement position of
The corresponding electric circuit element and the conductive layer of the wiring unit layer can be electrically connected to each other. Therefore, the degree of freedom of wiring increases. In addition, the electrical connection between the respective electric circuit elements via the conductive layer of the wiring unit layer can reduce the wiring density.

According to another aspect of the present invention, there is provided a semiconductor device comprising:
The wiring structure according to claim 1 is the wiring structure according to claim 1,
An electric circuit element provided on the n-th wiring unit layer counted from the substrate surface side, wherein the conductive layer of the n-th wiring unit layer stabilizes or controls the peripheral potential of the electric circuit element; Characterized in that it is an electrode for

According to such a wiring structure, since the wiring unit layer extends in a plane along the substrate surface,
By keeping the conductive layer of the n-th wiring unit layer at a constant potential, the peripheral potential of the electric circuit element provided on the n-th wiring unit layer can be stabilized. The peripheral potential of the electric circuit element can be variably controlled by arbitrarily and suitably changing the potential of the conductive layer of the n-th wiring unit layer.

According to another aspect of the present invention, there is provided a semiconductor device comprising:
The method for forming a via hole according to claim 1 includes forming a via hole in the wiring unit layer of the wiring structure according to claim 1.
When etching the insulating layer of the wiring unit layer located at the final reaching depth of the via hole, an etchant or etching for selectively etching the insulating layer of the wiring unit layer without etching the conductive layer of the wiring unit layer. It is characterized by using gas.

According to such a via hole forming method, since the etching can be reliably stopped at the conductive layer of the wiring unit layer, the depth of the via hole can be accurately controlled.

According to another aspect of the present invention, there is provided a semiconductor device comprising:
In the method for forming a via hole according to the first aspect, when forming the via hole in the semiconductor substrate having the wiring structure according to the first aspect, when etching the semiconductor substrate to form the via hole,
An etchant or an etching gas for selectively etching a semiconductor substrate without etching a conductive layer of a wiring unit layer is used.

According to such a via hole forming method, since the etching can be reliably stopped at the conductive layer of the wiring unit layer, the depth of the via hole can be accurately controlled.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. The drawings are only schematically shown to the extent that the invention can be understood, and thus the invention is not limited to the illustrated examples.

FIGS. 1 and 2 are a sectional view and a plan view, respectively, schematically showing the structure of the first embodiment of the present invention. FIG. 1 shows a cross section corresponding to a cross section taken along line II of FIG. In FIG. 2, a source electrode, a drain electrode, a gate electrode, and a wiring electrode are omitted to facilitate understanding of the drawing.

As shown in these figures, the wiring structure of this embodiment is composed of n (n is a natural number) wiring unit layers 12 stacked on the semiconductor substrate 10 and the substrate surface 10a.
To form a laminated body L for wiring, the wiring unit layer 12 is composed of the conductive layer 121 and the insulating layer 122 provided sequentially from the substrate surface 10a side, and the wiring unit layer 12 is formed on the substrate surface 10a. It extends in the direction along the plane.

In this embodiment, n = 1, and n (n = 1) wiring unit layers 12 are stacked on the front surface 10a of the GaAs semiconductor substrate 10. The wiring unit layer 12 includes an n ⁺ -AlGaAs conductive layer 121 and an undoped GaAs insulating layer 122 provided sequentially from the substrate surface 10a side. The conductive layer 121 and the insulating layer 122 of the wiring unit layer 12 are
a Extends to the entire area.

Furthermore, the wiring structure of this embodiment
The electric circuit element 14 provided on the n-th (n = 1) th wiring unit layer 12 counted from the 0a side;
0, and the via hole 16 is disposed immediately below the electric circuit element 14.

Here, an FET (Field Effect Transistor) is used as the electric circuit element 14 using the element configuration layer 18 provided on the n-th (n = 1) th wiring unit layer 12.
r) For example, a GaAs FET having a recess structure is formed. For this reason, the element configuration layer 18 is composed of the n-GaAs active layer 18 sequentially provided on the insulating layer 122 of the wiring unit layer 12.
1 and an n ⁺ -GaAs contact layer 182. Then, an insulating layer 20 for element isolation, for example, an impurity ion implantation region is provided in the element constituting layer 18. In the figure, a region into which impurity ions for forming the insulating layer 20 are implanted is indicated by a dot, and a region into which impurity ions for forming the insulating layer 20 are implanted and a region into which the impurity ions are not implanted are shown. The boundaries of the area are indicated by dotted lines.

The insulating layer 20 is formed of the conductive layer 12 of the n-th (n = 1) -th wiring unit layer 12 from the upper surface of the element forming layer 18.
The insulating layer 20 surrounds the island region 22 in which the electric circuit element 14 is disposed in a closed loop. This insulating layer 20 is shown with diagonal hatching in FIG.

As a result, the element forming layer 18 in the island-shaped region 22 is formed.
And the element forming layer 18 in a region other than the island-shaped region 22,
The (n = 1) -th wiring unit layer 12 is electrically insulated and separated by the insulating layer 122 and the insulating layer 20 for element isolation.

Further, the element forming layer 18 in the island region 22
A recess 24 having a depth from the upper surface of the contact layer 182 to the active layer 181 is provided. The active layer 181 is formed through the recess 24.
Is exposed, and the gate electrode 26 is provided on the channel region 181a. Also recess 24
As a result, the contact layer 182 of the island region 22 is divided into the first main electrode region 182a of the active layer 181 which corresponds to the source region 181b here and the second main electrode region 182b which corresponds to the drain region 181c here. Then, a first main electrode, here, a source electrode 28, is provided on one divided portion 182a, and a second main electrode, here, a drain electrode 30, is provided on the other divided portion 182b.

Accordingly, the electric circuit element 14 includes the active layer 181
Channel region 181a, source region 181b, and drain region 181c, a gate electrode 26 provided on the channel region 181a, a source electrode 28 provided on the source region 181b via a contact layer separation portion 182a, and a drain region. And a drain electrode 30 provided on the contact layer 181c via a contact layer dividing portion 182b.

The insulating layer 20 in a region adjacent to the source electrode 28 is used as an insulating layer for forming a via hole, and a via hole 32 is provided in the insulating layer 20 in this region. The via hole 32 is formed to a depth from the surface on which the source electrode 28 is provided to the conductive layer 121 of the lowermost wiring unit layer 12, and the lowermost conductive layer 121 is exposed via the via hole 32. A wiring electrode 34 is provided from the exposed conductive layer 121 to the source electrode 28, and the conductive layer 12
1 and the source electrode 28 are connected by a wiring electrode 34 via a via hole 32.

On the substrate 10 immediately below the electric circuit element 14,
A via hole 16 is provided. The via hole 16 is formed to a depth from the rear substrate surface 10 b to the conductive layer 121 of the lowermost wiring unit layer 12, and the lowermost conductive layer 121 is exposed through the via hole 16. And back electrode 3
6 is provided over the entire surface of the rear substrate surface 10 b, and the lowermost conductive layer 121 and the back electrode 36 are connected via the via hole 16.

Although only one electric circuit element 14 is shown in the figure, a plurality of electric circuit elements 14 are provided on the wiring unit layer 12 and an insulating layer is provided for each electric circuit element 14. 20, via holes 32, wiring electrodes 34,
The via hole 16 is provided, and the source electrode 28 of each electric circuit element 14 is connected to the back electrode 36 via the via hole 32, 16.

According to this embodiment, the source electrode 28
The wiring electrode 34 is electrically connected to the wiring electrode 34, and the wiring electrode 34 is a high-concentration impurity added layer n via the via hole 32.
⁺ -AlGaAs is electrically connected to the conductive layer 121. The n ⁺ -AlGaAs conductive layer 121 has a resistance value as low as that of the metal layer because impurities are added at a high concentration. Since n ⁺ -AlGaAs conductive layer 121 is electrically connected to back electrode 36 via via hole 16, source electrode 28 can have the same potential as back electrode 36.

Since the wiring unit layer 12 extends in a plane, if the via hole 16 on the back side of the substrate is provided in a region overlapping with the wiring unit layer 12 in plan view, the back electrode 36 is connected to the wiring. Conductive layer 121 of unit layer 12
Can be connected to Therefore, even if the arrangement position (or formation position) of the via hole 16 on the back side of the substrate is deviated from the design position due to photolithography for forming the via hole and a mask deviation in the etching process, etc., the back electrode 36 and the wiring unit layer There is very little possibility that connection failure with the 12 conductive layers 121 will occur. In order to prevent the occurrence of connection failure, it is effective to extend the wiring unit layer 12 in a plane over the entire surface of the substrate.

In the prior art, a via hole having a depth from the source electrode 28 to the rear substrate surface 10b is formed.
The source electrode 28 and the back electrode 36 are formed through the via hole.
And was connected. On the other hand, in this embodiment, the depth of the via hole 32 is the depth from the surface on which the source electrode 28 is provided to the conductive layer 121 of the wiring unit layer 12, and the depth of the via hole 16 is the rear substrate surface 10b. , The source electrode 28 and the back surface electrode 36 are connected by using the via holes 32 and 16 which are shallower than the via holes formed conventionally. Can be. The diameter of the via hole can be reduced as much as the depth can be reduced. In particular, in the case where a plurality of electric circuit elements 14 are provided on the wiring unit layer 12, by reducing the diameter of the via hole 32 on the front side of the substrate, the integration density of the electric circuit elements 14 on the front side of the substrate can be increased. There is.

Further, since the via hole 16 on the back side of the substrate is provided directly below the electric circuit element 14, the heat dissipation efficiency of the electric circuit element 14 can be increased by the via hole 16. In addition, when the back electrode 36 is provided over the entire surface of the back substrate surface 10b, the back substrate surface 10b
Since the only electric circuit element provided on the upper surface is the back electrode 36, there is no need to consider increasing the integration density of the electric circuit elements on the back side of the substrate, and the diameter of the via hole 16 on the back side of the substrate can be increased. By providing the via hole 16 having a large diameter, the heat radiation efficiency of the electric circuit element 14 can be further increased. When a plurality of electric circuit elements 14 are provided on the front side of the substrate, it is preferable to provide via holes 16 directly below each electric circuit element 14 so as to enhance the heat radiation efficiency of each electric circuit element 14.

Further, since the electric circuit element 14 is provided on the wiring unit layer 12, even if the via hole 16 on the back side of the substrate is provided immediately below the electric circuit element 14, the electric circuit element 14 is exposed via the via hole 16. Never. Therefore, even if the via hole 16 is provided directly below the electric circuit element 14,
Since the back electrode 36 does not directly contact the electric circuit element 14, the operation of the electric circuit element 14 is not impaired.

Next, FIGS. 3 to 6 are sectional views showing the main manufacturing steps of the wiring structure shown in FIG. 1 step by step.

Hereinafter, an example of a method of manufacturing the wiring structure shown in FIG. 1 will be described with reference to FIGS. 3 to 6 and an embodiment of the invention according to claim 5 and an embodiment of the invention according to claim 6 will be described. explain. In the embodiment of the invention as defined in claim 5, in the wiring structure of FIG.
When forming the insulating layer 122 of the wiring unit layer 12 located at the final reaching depth of the via hole 32, that is, the design depth, when forming the wiring unit layer 1,
An etchant or an etching gas for selectively etching the insulating layer 122 of the wiring unit layer 12 without etching the second conductive layer 121 is used.
According to the embodiment of the present invention, in forming the via hole 16 in the semiconductor substrate 10 in the wiring structure of FIG. 1, when the semiconductor substrate 10 is etched to form the via hole 16, a wiring unit layer is formed. 12 conductive layers 12
An etchant or an etching gas that selectively etches the semiconductor substrate 10 without etching the semiconductor substrate 10 is used.

First, a GaAs substrate 1 is formed by an MBE method or the like.
The n ⁺ -AlGaAs conductive layer 121, the undoped GaAs insulating layer 122, and the n-Ga
As active layer 181 and n ⁺ -GaAs contact layer 18
2 is formed (FIG. 3A).

Next, impurity ions, here, oxygen ions, are implanted by ion implantation to a depth from the contact layer 182 to the conductive layer 121 to form the insulating layer 20 which is an inactive region. The insulating layer 20 surrounds the periphery of the island-shaped region 22 to be a formation region (FIG. 3B).

Next, the source electrode 28 is formed by a lift-off method.
And the drain electrode 30 is formed on the contact layer 182 of the island-shaped region 22 at a position corresponding to the source region 181b and the drain region 181c of the active layer 18 (FIG. 3).
(C)).

Next, the source electrode 28 and the drain electrode 30
A recess 24 is formed in the contact layer 182 therebetween, and the channel region 181a of the active layer 181 is exposed through the recess 24. Thereafter, the exposed channel region 181a is formed.
A gate electrode 26 is formed thereon (FIG. 4A).

Next, a resist mask 38 for forming a via hole is formed on the gate electrode 26 (FIG. 4B).
The resist mask 38 has an opening 38 a that exposes a formation region of the via hole 32 on the front side of the substrate.

Next, the insulating layer 20 is interposed via the resist mask 38.
Is etched to form a via hole 32 in the insulating layer 20, and the conductive layer 121 is exposed through the via hole 32 (FIG. 4C). At this time, an etchant that etches the insulating layer 20 but does not etch the conductive layer 121, for example, a citric acid solution is used. The citric acid solution is applied to the insulating layer 20, that is, the contact layer 182, the active layer 181, the insulating layer 122, and the conductive layer 1 each having oxygen ions implanted therein.
21 is etched, but the conductive layer 121 into which oxygen ions have not been implanted is not etched. Therefore, the etching stops when the conductive layer 121 to which oxygen ions are not implanted is reached.

When the etching is stopped, the resist mask 3
Then, a resist mask 40 for forming a wiring electrode is formed on the gate electrode 26 (FIG. 5A). The resist mask 40 has an opening 40a exposing a region where the wiring electrode 34 is formed.

Next, the resist mask 4 is formed by a vacuum evaporation method.
0 is deposited via the wiring electrode material 42 (FIG. 5).
(B)). After that, the resist mask 40 is removed, and the wiring electrode 34 made of the wiring electrode material 42 remaining in the region where the wiring electrode 34 is formed is obtained.

Next, a resist mask 44 for forming a via hole is formed on the backside substrate surface 10b (FIG. 5).
(C)). The resist mask 44 has an opening 44a exposing a region where the via hole 16 on the back side of the substrate is formed. Compared with the conventional case, the width of the opening 44a of the resist mask 44 can be made 10 times or more, and the alignment accuracy of the exposure mask used for forming the resist mask 44 can be moderately reduced to about ± 5 μm.

Next, the substrate 10 is etched through the resist mask 44 to form a via hole 16 on the back side of the substrate (FIG. 6A). In this etching, the substrate 10 is etched, but the conductive layer 1 into which oxygen ions have not been implanted.
Reference numeral 21 denotes an etchant that is not etched, for example, a citric acid solution. With the use of the citric acid solution, the etching stops at the conductive layer 121 where oxygen ions have not been implanted.

After the etching is stopped, the etching mask 44 is removed. Thereafter, a back electrode 36 is formed over the entire back substrate surface 10b by a vacuum deposition method.
(B)), the wiring structure of FIG. 1 is completed.

As described above, in the etching for forming the via holes 32 and 16, the etching is automatically stopped at the conductive layer 121 into which oxygen ions have not been implanted, so that over-etching does not occur, and therefore, wiring failure occurs. And the electric circuit element 14 can be prevented from being damaged.

FIGS. 7 and 8 are a sectional view and a plan view schematically showing the structure of another embodiment of the present invention. FIG.
8 shows a cross section corresponding to a cross section taken along the line VII-VII in FIG. In FIG. 8, a source electrode, a drain electrode, a gate electrode, and a wiring electrode are omitted to facilitate understanding of the drawing.

Hereinafter, points different from the embodiment of FIG. 1 will be described, and detailed description of the same points as those of the embodiment of FIG. 1 will be omitted.

In this embodiment, n = 2 and n (= 2) wiring unit layers 46 and 12 are stacked on the front substrate surface 10a, and these wiring unit layers 46 and 12 are stacked.
And the substrate 10 constitute a laminate L for wiring.

The wiring unit layers 46 are sequentially extended on the substrate surface 10a in a plane over the entire substrate surface 10a.
And 12 are provided, and the wiring unit layer 46 is
N ⁺ -AlGaAs conductive layer 46 provided sequentially from the side
1 and an undoped GaAs insulating layer 462. Then, the electric circuit element 14 is provided on the n-th (n = 2) wiring unit layer 12.

In a region adjacent to the source electrode 28, an insulating layer 48 for forming a via hole, for example, an ion implantation region is provided. The insulating layer 48 is, for example, a region into which oxygen ions are implanted. When viewed in plan, part or all of the insulating layer 48 is provided so as to overlap the insulating layer 20, and the insulating layer 48 is formed on the conductive layer 461 of the lowermost wiring unit layer 46 from the surface on which the source electrode 28 is provided. It is formed to the maximum depth. In the figure, regions into which impurity ions for forming the insulating layers 20 and 48 are implanted are indicated by dots, and regions where impurity ions for forming the insulating layers 20 and 48 are implanted and The boundaries of the non-implanted regions are indicated by dotted lines.

Then, a via hole 32 is provided in the insulating layer 48. The via hole 32 is formed at a depth from the surface on which the source electrode 28 is provided to the conductive layer 461 of the lowermost wiring unit layer 46, and the lowermost conductive layer 461 is exposed through the via hole 32. The wiring electrode 34 is provided from the exposed lowermost conductive layer 461 to the source electrode 28, and the conductive layer 461 and the source electrode 28 are connected by the wiring electrode 34 via the via hole 32.

Further, the via hole 16 is formed on the substrate surface 1 on the back side.
0b to the lowermost conductive layer 461, and the back surface electrode 36 and the lowermost conductive layer 461 are connected via the via hole 16.

Further, the insulating layer 20 in a region adjacent to the drain electrode 30 is used as an insulating layer for forming a via hole, and a via hole 50 is provided in the insulating layer 20 in this region. The via hole 50 is formed at a depth from the surface on which the drain electrode 20 is provided to the conductive layer 121 of the remaining wiring unit layer 12, and the remaining conductive layer 121 is exposed through the via hole 50. Then, a wiring electrode 52 is provided from the exposed conductive layer 121 to the drain electrode 30, and the conductive layer 121 and the drain electrode 30 are connected by the wiring electrode 52 via the via hole 50.

Although only one electric circuit element 14 is shown in the figure, a plurality of electric circuit elements 14 are provided on the wiring unit layer 12, and each of the electric circuit elements 14 is provided with an insulating layer. 20, via holes 32, wiring electrodes 34,
Via hole 16, via hole 50, and wiring electrode 52
To connect the source electrode 28 of each electric circuit element 14 to the back electrode 36 via the via holes 32 and 16, respectively.
Are connected to the common conductive layer 121 and the via hole 50, respectively.

According to this embodiment, the source electrode 28
The wiring electrode 34 is electrically connected to the wiring electrode 34, and the wiring electrode 34 is a high-concentration impurity added layer n via the via hole 32.
⁺ -AlGaAs is electrically connected to the conductive layer 461. Since the n ⁺ -AlGaAs conductive layer 461 is doped with impurities at a high concentration, the resistance value is as low as that of the metal layer. Since the n ⁺ -AlGaAs conductive layer 461 is electrically connected to the back electrode 36 via the via hole 16, the source electrode 28 and the back electrode 36 can have the same potential.

Since the drain electrode 30 is connected to the wiring electrode 52 and the wiring electrode 52 is connected to the n ⁺ -AlGaAs conductive layer 121 via the via hole 50,
The drain electrode 30 can have the same potential as the n ⁺ -AlGaAs layer 121.

In this embodiment, as in the embodiment shown in FIG. 1, even if the arrangement position (or formation position) of the via hole 16 on the back side of the substrate deviates from the design position, the back electrode 36 is formed.
There is very little possibility that a connection failure between the first conductive layer 461 and the lowermost conductive layer 461 will occur. To prevent poor connection,
It is effective to extend the lowermost wiring unit layer 46 over the entire surface of the substrate.

The depth of the via hole 32 is a depth from the surface on which the source electrode 28 is provided to the lowermost conductive layer 461, and the depth of the via hole 16 is from the back substrate surface 10 b to the lowermost conductive layer. 461, so that the depth of the via hole 3 is smaller than that of the conventionally formed via hole.
The source electrode 28 and the back surface electrode 36 can be connected by using 2 and 16. The diameter of the via hole can be reduced as much as the depth can be reduced. In particular, when a plurality of electric circuit elements 14 are provided on the uppermost wiring unit layer 12, the integration density of the electric circuit elements 14 on the front surface of the substrate can be increased by reducing the diameter of the via hole 32 on the front surface of the substrate. There is an advantage that you can.

Since the via hole 16 on the back side of the substrate is provided immediately below the electric circuit element 14, the via hole 16 can enhance the heat radiation efficiency of the electric circuit element 14. In addition, when the back electrode 36 is provided over the entire surface of the back substrate surface 10b, the back substrate surface 10b
Since the only electric circuit element provided on the upper surface is the back electrode 36, there is no need to consider increasing the integration density of the electric circuit elements on the back side of the substrate, and the diameter of the via hole 16 on the back side of the substrate can be increased. By providing the via hole 16 having a large diameter, the heat radiation efficiency of the electric circuit element 14 can be further increased. When a plurality of electric circuit elements 14 are provided on the front side of the substrate, it is preferable to provide via holes 16 directly below each electric circuit element 14 so as to enhance the heat radiation efficiency of each electric circuit element 14.

Since the electric circuit element 14 is provided on the wiring unit layer 12, even if the via hole 16 on the back side of the substrate is provided immediately below the electric circuit element 14, the electric circuit element 14 is exposed via the via hole 16. Never. Therefore, even if the via hole 16 is provided directly below the electric circuit element 14,
Since the back electrode 36 does not directly contact the electric circuit element 14, the operation of the electric circuit element 14 is not impaired.

Further, in this embodiment, the following effects can be expected. That is, the conductive layer 121 of the wiring unit layer 12
As a result, the drain electrodes 30 of the plurality of electric circuit elements 14 can be connected in common, so that the wiring density, particularly the wiring density on the surface on which the drain electrodes 30 are provided, can be reduced. Therefore, it is possible to increase the degree of freedom in wiring layout, particularly on the wiring surface of the drain electrode 30, and to increase the integration density of the electric circuit elements 14.
In order to increase the degree of freedom in wiring management or increase the integration density of the electric circuit elements 14, it is effective to extend the conductive layer 121 of the wiring unit layer 12 in a planar manner over the entire substrate surface 10a.

Next, another two embodiments of the present invention will be described. In one embodiment, when the via hole 32 is formed in the wiring unit layers 12 and 46 in the wiring structure of FIG. 7, the wiring unit layer 46 located at the final reaching depth of the via hole 32, that is, the design depth is formed.
When the insulating layer 461 is etched, an etchant or an etching gas for selectively etching the insulating layer 462 of the wiring unit layer 46 without etching the conductive layer 461 of the wiring unit layer 46 is used.

For example, a citric acid solution may be used as an etchant. The citric acid solution contains the insulating layer 48, that is, the contact layer 182 into which oxygen ions are respectively implanted.
Active layer 181, insulating layer 122, conductive layer 121, insulating layer 4
61 and the conductive layer 462 are etched, but the conductive layer 461 to which oxygen ions are not implanted is not etched.
Therefore, the etching stops when the conductive layer 461 to which oxygen ions have not been implanted is reached.

In another embodiment, when forming the via hole 50 in the wiring unit layer 12 in the wiring structure of FIG. 7, the wiring unit layer located at the final reaching depth of the via hole 50, that is, the design depth is formed. 12 insulating layers 121
When etching is performed, an etchant or an etching gas that selectively etches the insulating layer 122 of the wiring unit layer 12 without etching the conductive layer 121 of the wiring unit layer 12 is used.

For example, a citric acid solution may be used as an etchant. The citric acid solution contains the insulating layer 20, that is, the contact layer 182 into which oxygen ions are respectively implanted.
The active layer 181, the insulating layer 122, and the conductive layer 121 are etched, but the conductive layer 12 into which oxygen ions have not been implanted.
1 does not etch. Therefore, the etching stops when the conductive layer 121 to which oxygen ions are not implanted is reached.

Another embodiment of the present invention will be described. In this embodiment, when the via hole 16 is formed in the semiconductor substrate 10 in the wiring structure of FIG. 7, when the semiconductor substrate 10 is etched to form the via hole 16, the conductive layer 461 of the wiring unit layer 46 is etched. Instead, an etchant or an etching gas that selectively etches the semiconductor substrate 10 is used.

For example, a citric acid solution may be used as an etchant. The citric acid solution etches the substrate 10 but does not implant oxygen ions in the conductive layer 121.
Does not etch. Therefore, the etching stops when the conductive layer 121 to which oxygen ions are not implanted is reached.

FIGS. 9 and 10 are a sectional view and a plan view, respectively, which schematically show the structure of the fourth embodiment of the present invention. FIG. 9 shows a cross section corresponding to a cross section taken along line IX-IX in FIG. In FIG. 10, a source electrode, a drain electrode, a gate electrode, and a wiring electrode are omitted to facilitate understanding of the drawing.

This embodiment is also an embodiment of the first aspect of the present invention. Hereinafter, differences from the embodiment of FIG. 1 will be described.
Detailed description of the same points as in the embodiment of FIG. 1 is omitted.

In this embodiment, n = 3 and n (= 3) wiring unit layers 54, 46, and 12 are formed on the substrate surface 1 on the front side.
0a, the wiring unit layers 5
The stacked body L for wiring is constituted by the substrates 4, 46, 12 and the substrate 10.

The wiring unit layers 5 are sequentially extended on the substrate surface 10a in a plane over the entire substrate surface 10a.
4, 46, and 12 are provided, and the wiring unit layer 54 is composed of an n ⁺ -AlGaAs conductive layer 541 and an undoped GaAs insulating layer 542 sequentially provided from the substrate surface 10a side. Then, the electric circuit element 14 is provided on the n-th (n = 3) wiring unit layer 12.

An insulating layer 48 for forming a via hole, for example, an ion implantation region is provided in a region adjacent to the source electrode 28. The insulating layer 48 is, for example, a region into which oxygen ions are implanted. When viewed in plan, part or all of the insulating layer 48 is provided so as to overlap the insulating layer 20, and the insulating layer 48 is formed on the conductive layer 541 of the lowermost wiring unit layer 54 from the surface on which the source electrode 28 is provided. It is formed to the maximum depth.

The via hole 32 is provided in the insulating layer 48. The via hole 32 is formed at a depth from the disposition surface of the source electrode 28 to the conductive layer 541 of the lowermost wiring unit layer 54, and the lowermost conductive layer 541 is exposed through the via hole 32. Then, the wiring electrode 34 is provided from the exposed lowermost conductive layer 541 to the source electrode 28, and the conductive layer 541 and the source electrode 28 are connected by the wiring electrode 34 via the via hole 32.

Further, the via hole 16 is formed in the substrate surface 1 on the back side.
Ob is formed to a depth from 0b to the lowermost conductive layer 541, and the back electrode 36 and the lowermost conductive layer 541 are connected through the via hole 16.

Further, the conductive layer 121 of the n-th (n = 3) wiring unit layer 12 is used as an electrode for stabilizing or controlling the peripheral potential of the electric circuit element 14.

Here, the insulating layer 20 is used as an insulating layer for forming a via hole. The insulating layer 20 includes a source electrode 28
Alternatively, it has a depth from the surface on which the drain electrode 30 is provided to the n-th (n = 3) th, that is, the conductive layer 121 of the uppermost wiring unit layer 12. Then, a via hole 58 is provided at any suitable place of the insulating layer 20. Via hole 58,
The uppermost conductive layer 121 is formed at a depth from the surface on which the source electrode 28 or the drain electrode 30 is provided to the uppermost conductive layer 121, and the uppermost conductive layer 121 is exposed through the via hole 58. Then, the electrode terminals 60 are provided from the uppermost conductive layer 121 to the wiring surface of the source electrode 28 or the drain electrode 30.

Further, an insulating layer 62 for forming a via hole, for example, an ion implantation region is provided in a region adjacent to the drain electrode 30. The insulating layer 62 is, for example, a region into which oxygen ions are implanted. When viewed in plan, part or all of the insulating layer 62 is provided so as to overlap with the insulating layer 20, and the insulating layer 62 is
It is formed at a depth from the surface on which the drain electrode 30 is provided to the conductive layer 461 of the remaining wiring unit layer 46 (intermediate wiring unit layer 46).

Then, a via hole 50 is provided in the insulating layer 62. A via hole 50 is formed at a depth from the surface on which the drain electrode 30 is provided to the conductive layer 461 of the intermediate wiring unit layer 46, and the intermediate conductive layer 4 is formed through the via hole 50.
Expose 61. Then, the exposed intermediate conductive layer 46
The wiring electrode 52 is provided from 1 to the drain electrode 30, and the conductive layer 461 and the drain electrode 30 are connected by the wiring electrode 52 via the via hole 62.

In the figure, regions into which impurity ions for forming the insulating layers 48, 20, and 62 are implanted are indicated by dots, and impurity regions for forming the insulating layers 48, 20, and 62 are shown. The boundary between the ion-implanted region and the non-implanted region is indicated by a dotted line. Although only one electric circuit element 14 is shown in the drawing, a plurality of electric circuit elements 14 are provided on the wiring unit layer 12, and an insulating layer 20 is provided for each electric circuit element 14. Via hole 32,
A wiring electrode 34, a via hole 16, a via hole 50, and a wiring electrode 52 are provided. The source electrode 28 of each electric circuit element 14 is connected to the back electrode 36 via the via hole 32, 16, respectively. The fourteen drain electrodes 30 are each connected to a common conductive layer 46.
1 and a via hole 50. The conductive layer 12 for stabilizing the peripheral potential of the electric circuit element 14
1 and its electrode terminals 60
And a common conductive layer and electrode terminal.

According to this embodiment, the source electrode 28
The wiring electrode 34 is electrically connected to the wiring electrode 34, and the wiring electrode 34 is a high-concentration impurity added layer n via the via hole 32.
⁺ -AlGaAs is electrically connected to the conductive layer 541. The n ⁺ -AlGaAs conductive layer 541 has a resistance value as low as that of the metal layer because impurities are added at a high concentration. Since the n ⁺ -AlGaAs conductive layer 541 is electrically connected to the back electrode 36 via the via hole 16, the source electrode 28 can have the same potential as the back electrode 36.

The drain electrode 30 is connected to the wiring electrode 52, and the wiring electrode 52 is connected to the n ⁺ -AlGaAs conductive layer 461 via the via hole 50.
The drain electrode 30 can have the same potential as the n ⁺ -AlGaAs layer 461.

Since the electrode terminal 60 is connected to the n ⁺ -AlGaAs conductive layer 121 through the via hole 58, a constant potential is supplied to the conductive layer 121 through the electrode terminal 60, so that the potential of the conductive layer 121 is reduced. Can be stabilized.

In this embodiment, as in the embodiment of FIG. 1, even if the arrangement position (or formation position) of the via hole 16 on the back side of the substrate deviates from the design position, the back electrode 36 is formed.
There is very little possibility that a connection failure between the first conductive layer 541 and the lowermost conductive layer 541 will occur. To prevent poor connection,
It is effective to extend the lowermost wiring unit layer 54 over the entire surface of the substrate.

The depth of the via hole 32 is a depth from the surface on which the source electrode 28 is provided to the lowermost conductive layer 541, and the depth of the via hole 16 is from the back substrate surface 10 b to the lowermost conductive layer. 541, so that the depth of the via hole 3 is smaller than that of the via hole formed conventionally.
The source electrode 28 and the back surface electrode 36 can be connected by using 2 and 16. The diameter of the via hole can be reduced as much as the depth can be reduced. In particular, when a plurality of electric circuit elements 14 are provided on the uppermost wiring unit layer 12, the integration density of the electric circuit elements 14 on the front surface of the substrate can be increased by reducing the diameter of the via hole 32 on the front surface of the substrate. There is an advantage that you can.

Further, since the via hole 16 on the back side of the substrate is provided immediately below the electric circuit element 14, the heat dissipation efficiency of the electric circuit element 14 can be increased by the via hole 16. In addition, when the back electrode 36 is provided over the entire surface of the back substrate surface 10b, the back substrate surface 10b
Since the only electric circuit element provided on the upper surface is the back electrode 36, there is no need to consider increasing the integration density of the electric circuit elements on the back side of the substrate, and the diameter of the via hole 16 on the back side of the substrate can be increased. By providing the via hole 16 having a large diameter, the heat radiation efficiency of the electric circuit element 14 can be further increased. When a plurality of electric circuit elements 14 are provided on the front side of the substrate, it is preferable to provide via holes 16 directly below each electric circuit element 14 so as to enhance the heat radiation efficiency of each electric circuit element 14.

Since the electric circuit element 14 is provided on the wiring unit layer 12, even if the via hole 16 on the back side of the substrate is provided immediately below the electric circuit element 14, the electric circuit element 14 is exposed via the via hole 16. Never. Therefore, even if the via hole 16 is provided directly below the electric circuit element 14,
Since the back electrode 36 does not directly contact the electric circuit element 14, the operation of the electric circuit element 14 is not impaired.

Further, in this embodiment, the following effects can be expected. First, the conductive layer 4 of the intermediate wiring unit layer 46
61, the drain electrodes 30 of the plurality of electric circuit elements 14
Can be commonly connected, so that the wiring density, particularly the wiring density on the surface on which the drain electrode 30 is provided, can be reduced.
Therefore, it is possible to increase the degree of freedom in wiring layout, particularly on the wiring surface of the drain electrode 30, and to increase the integration density of the electric circuit elements 14. Increase the degree of freedom in wiring management or electric circuit element 1
In order to increase the integration density of No. 4, it is effective to extend the conductive layer 461 of the wiring unit layer 46 in a plane over the entire substrate surface 10a. Further, since the potential of the conductive layer 121 of the uppermost wiring unit layer 12 can be kept constant and stabilized via the electrode terminals 60, the operating characteristics of the electric circuit element 14 can be stabilized. In particular, when the electric circuit element 14 is an FET, the side gate effect or the back gate effect of the FET can be prevented. Further, the potential of the conductive layer 121 of the uppermost wiring unit layer 12 is
Since it can be arbitrarily and suitably changed via the electrode terminal 60, the degree of freedom in circuit design can be increased. Further, by providing the three wiring unit layers 12, 46, and 54 for wiring, the wiring density, particularly the wiring density on the surface on which the source electrode 28 or the drain electrode 30 is provided, can be effectively reduced. The degree of integration can be increased.

Next, another three embodiments of the present invention will be described. In one embodiment, in forming the via hole 32 in the wiring unit layers 12, 46, 54 in the wiring structure of FIG. 9, the wiring unit layer located at the final reaching depth of the via hole 32, that is, the design depth is formed. When the insulating layer 541 of the wiring unit 54 is etched, an etchant or an etching gas that selectively etches the insulating layer 542 of the wiring unit layer 54 without etching the conductive layer 541 of the wiring unit layer 54 is used. .

For example, a citric acid solution may be used as an etchant. The citric acid solution contains the insulating layer 48, that is, the contact layer 182 into which oxygen ions are respectively implanted.
Active layer 181, insulating layer 122, conductive layer 121, insulating layer 4
61, the conductive layer 462, the insulating layer 541, and the conductive layer 541 are etched, but the conductive layer 541 to which oxygen ions are not implanted is not etched. Therefore, the etching stops when the conductive layer 541 to which oxygen ions have not been implanted is reached.

In another embodiment, a via hole 50 is formed in the wiring unit layers 12 and 46 in the wiring structure of FIG.
When the insulating layer 461 of the wiring unit layer 46 located at the final reaching depth of the via hole 50, that is, the design depth is etched, the wiring unit layer 46
An etchant or an etching gas for selectively etching the insulating layer 462 of the wiring unit layer 46 without etching the conductive layer 461 is used.

For example, a citric acid solution may be used as an etchant. The citric acid solution contains the insulating layer 62, that is, the contact layer 182 into which oxygen ions are respectively implanted,
Active layer 181, insulating layer 122, conductive layer 121, insulating layer 4
62 and the conductive layer 461 are etched, but the conductive layer 461 into which oxygen ions are not implanted is not etched.
Therefore, the etching stops when the conductive layer 461 to which oxygen ions have not been implanted is reached.

In another embodiment, when forming the via hole 58 in the wiring unit layer 12 in the wiring structure of FIG. 9, the wiring unit layer located at the final reaching depth of the via hole 58, that is, the design depth is formed. 12 insulating layers 121
When etching is performed, an etchant or an etching gas that selectively etches the insulating layer 122 of the wiring unit layer 12 without etching the conductive layer 121 of the wiring unit layer 12 is used.

For example, a citric acid solution may be used as an etchant. The citric acid solution contains the insulating layer 20, that is, the contact layer 182 into which oxygen ions are respectively implanted.
The active layer 181, the insulating layer 122, and the conductive layer 121 are etched, but the conductive layer 12 into which oxygen ions have not been implanted.
1 does not etch. Therefore, the etching stops when the conductive layer 121 to which oxygen ions are not implanted is reached.

Another embodiment of the present invention will be described. In this embodiment, when the via hole 16 is formed in the semiconductor substrate 10 in the wiring structure of FIG. 9, when the semiconductor substrate 10 is etched to form the via hole 16, the conductive layer 541 of the wiring unit layer 54 is etched. Instead, an etchant or an etching gas that selectively etches the semiconductor substrate 10 is used.

For example, a citric acid solution may be used as an etchant. The citric acid solution etches the substrate 10 but does not implant oxygen ions in the conductive layer 541.
Does not etch. Therefore, the etching stops when the conductive layer 541 to which oxygen ions have not been implanted is reached.

The present invention is not limited only to the above-described embodiment, and accordingly, the arrangement position, the number of arrangements,
Dimensions, shapes, configurations, forming materials, conductivity types and others
Any changes can be made within the spirit of the invention.

For example, in the above-described embodiment, an example has been described in which a GaAs FET having a recess structure is provided as the electric circuit element 14. In addition, a GaAs FET such as a compound semiconductor element such as a HEMT or an InPFET or an element semiconductor element such as a Si. An electric circuit element 14 using a material other than the above can also be used. From the viewpoint of the function of the electric circuit element 14, besides the FET, for example, a unipolar transistor,
A bipolar transistor, a diode, an inductor, a capacitor, a resistor, or an electrode can be the electric circuit element 14. In addition to providing one type of electric circuit element 14, various electric circuit elements such as a unipolar transistor, a bipolar transistor, and a diode exemplified here may be provided in combination. The circuit design, especially the connection relation, is not limited to the illustrated example, and can be arbitrarily and suitably changed according to the design.

A metal layer having a flat surface may be formed on the back electrode 36 by plating or the like, and this metal layer may be used as a PHS (plated heat sink). PHS can also function as a back electrode. By providing the PHS, the heat radiation efficiency can be increased.

As the conductive layer of the wiring unit layer, n ⁺
A semiconductor layer other than the -AlGaAs layer, for example, an n ⁺ -InP layer may be used, or a metal layer of Al, Ge, In, or the like may be used.

In the above-described embodiment, the first main electrode 28
Is a source electrode, the first main electrode region 181b is a source region,
The second main electrode 30 is a drain electrode, and the second main electrode region 181
Although c is a drain region, the first main electrode 28 may be a drain electrode, the first main electrode region 181b may be a drain region, the second main electrode 30 may be a source electrode, and the second main electrode region 181c may be a source region. .

The wiring structure of the present invention is suitable for use in forming a GaAs IC or other semiconductor integrated circuit or semiconductor device.

[0106]

As is clear from the above description, according to the wiring structure of the first aspect of the present invention, since the wiring unit layer extends in a plane along the substrate surface, As long as the via hole and the conductive layer of the wiring unit layer overlap each other, even if the arrangement position of the via hole is freely changed, the corresponding electric circuit element and the conductive layer of the wiring unit layer may Can be electrically connected to each other. Therefore, the degree of freedom of wiring increases. In addition, the electrical connection between the respective electric circuit elements via the conductive layer of the wiring unit layer can reduce the wiring density. By increasing the number of wiring unit layers provided, the wiring density can be further reduced.

Therefore, according to the first aspect of the present invention,
The integration density of electric circuit elements provided in this wiring structure can be increased.

According to the wiring structure of the fourth aspect, in the wiring structure of the first aspect, the conductive layer of the n-th wiring unit layer (ie, the uppermost wiring unit layer immediately below the electric circuit element) is formed. And electrodes for keeping or controlling the peripheral potential of the electric circuit element constant. Therefore, by keeping the potential of the n-th wiring unit layer constant, the peripheral potential of the electric circuit element can be stabilized. By stabilizing the peripheral potential, the operating characteristics or electrical characteristics of the electric circuit element can be stabilized. Alternatively, the peripheral potential of the electric circuit element can be arbitrarily and variably controlled through the conductive layer of the n-th wiring unit layer. By variably controlling the peripheral potential, the degree of freedom in circuit design can be increased.

Therefore, according to the wiring structure of the fourth aspect, the integration density of the electric circuit element can be increased, and furthermore, the operating characteristics or electric characteristics of the electric circuit element can be stabilized or the circuit structure can be improved. The degree of freedom in design can be increased.

According to the via hole forming method of the fifth aspect, when forming the via hole in the wiring unit layer of the wiring structure of the first aspect, the final reaching depth of the via hole (ie, the design depth) Since the etching can be reliably stopped at the conductive layer of the wiring unit layer located in (1), the depth of the via hole can be controlled accurately.

Therefore, according to the via hole forming method according to the fifth aspect, it is possible to provide a via hole forming method suitable for forming a via hole in the wiring structure according to the first aspect of the present invention.

According to the via hole forming method of the present invention, when forming the via hole in the semiconductor substrate having the wiring structure of the present invention, the etching can be reliably stopped at the conductive layer of the wiring unit layer. Therefore, the depth of the via hole can be accurately controlled.

Therefore, according to the via hole forming method of the sixth aspect, it is possible to provide a via hole forming method suitable for forming a via hole in the wiring structure of the first aspect of the present invention.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing a configuration of an embodiment.

FIG. 2 is a plan view schematically showing a configuration of an embodiment.

FIGS. 3A to 3C are cross-sectional views schematically showing manufacturing steps of the embodiment.

FIGS. 4A to 4C are cross-sectional views schematically showing manufacturing steps of the embodiment.

FIGS. 5A to 5C are cross-sectional views schematically showing manufacturing steps of the embodiment.

FIGS. 6A and 6B are cross-sectional views schematically showing manufacturing steps of the embodiment.

FIG. 7 is a cross-sectional view schematically showing a configuration of an example.

FIG. 8 is a plan view schematically showing a configuration of an example.

FIG. 9 is a cross-sectional view schematically showing a configuration of an example.

FIG. 10 is a plan view schematically showing a configuration of an example.

[Explanation of symbols]

 10: Semiconductor substrate 12, 46, 54: Wiring unit layer 121, 461, 541: Conductive layer 122, 462, 542: Insulating layer 14: Electric circuit element 16, 32, 50, 58: Via hole

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 21/28 H01L 21/306 H01L 21/768 H01L 29/812

Claims (6)

(57) [Claims] 1. A GaAs substrate and n (n is a natural number) wiring unit layers stacked on a substrate surface to form a laminated body for wiring, wherein the wiring unit layer is formed on the GaAs substrate. A wiring structure comprising a conductive layer and an insulating layer provided sequentially from a surface side, wherein the wiring unit layer extends in a plane along a direction along the GaAs substrate surface. 2. The wiring structure according to claim 1, wherein said wiring unit layer extends in a region over the entire surface of said GaAs substrate. 3. The wiring structure according to claim 1, wherein an electric circuit element provided on an n-th wiring unit layer counted from the GaAs substrate surface side, and a via hole provided in the GaAs substrate. A wiring structure, wherein the via hole is disposed immediately below the electric circuit element and at a depth reaching a conductive layer of a first wiring unit layer. 4. The wiring structure according to claim 1, further comprising an electric circuit element provided on an n-th wiring unit layer counted from the GaAs substrate surface side, wherein the n-th wiring unit layer is provided. Wherein the conductive layer is an electrode for stabilizing or controlling the peripheral potential of the electric circuit element. 5. The method of forming a via hole for forming a wiring electrode in an m-th (natural number of 1 ≦ m ≦ n) wiring unit layer of the wiring structure according to claim 1, By implanting from the nth wiring unit layer to a depth reaching a part of the conductive layer of the mth wiring unit layer, an insulating layer is partially formed, and oxygen ions are implanted into the wiring unit layer. When the formed insulating layer is etched, the insulating layer formed by implanting oxygen ions is selectively etched without etching the conductive layer of the m-th wiring unit layer, and the conductive layer reaches the conductive layer. A method of forming a via hole, wherein the conductive layer is exposed at a depth. 6. In forming a via hole for forming a back electrode in the GaAs substrate according to claim 1, when etching the GaAs substrate to form the via hole, a first wiring unit layer is formed. Selectively etching the GaAs substrate without etching the conductive layer;
A method for forming a via hole, wherein the method includes exposing the conductive layer to a depth reaching the conductive layer.