JP3281236B2 - Scanning circuit and matrix type image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data signal line driving circuit provided in a matrix type image display device used for a display device such as a TV or a computer, a scanning circuit used for the scanning signal line driving circuit, and scanning of the same. The present invention relates to a matrix type image display device including a circuit.

[0002]

2. Description of the Related Art As the above-mentioned matrix type image display device, a device having a configuration shown in FIG. 15 is conventionally known. In this image display device, a data signal line 201 or a scanning signal line 202 is provided orthogonal to one or each of a pair of substrates, and a pixel is formed at an intersection of both signal lines 201 and 202. The data signal line 201 includes:
A data signal to be applied to the pixel is supplied from the data signal line driving circuit 203, and a scanning signal for selecting a pixel to supply the data signal (image signal) supplied to the data signal line 201 is supplied to the scanning signal line 202. Are supplied from the scanning signal line driving circuit 204.

FIG. 16 shows a schematic configuration of the data signal line driving circuit 203. The data signal line driving circuit 203 is a scanning circuit that outputs pulse signals one after another at regular time intervals.
5 and a sample-and-hold circuit 206 that receives a signal from the scanning circuit 205 and samples and outputs a data signal input from the outside. On the other hand, the configuration of the scanning signal line driving circuit 204 is almost the same, and a buffer circuit is used instead of the sample and hold circuit 206.

[0004] Each of the driving circuits requires a scanning circuit. As means for forming the scanning circuit, a method using a shift register and a method of performing a simple logical operation on the input of a plurality of pulse signals to generate a pulse signal are described. And a method of using a decoder circuit or a multiplexer circuit for outputting the same. FIG. 17 shows a circuit configuration using a decoding circuit as an example of the latter.

This circuit is composed of a scan control signal line 301 and a logical operation circuit 302.
02 performs a logical operation on a signal input from the scan control signal line 301 and outputs the result. Here, by performing a different operation for each logical operation circuit 302, a scanning signal having a different timing is output for each output as shown in the timing chart of FIG.

[0006]

By the way, in recent years, SVGA or XG
Display using a high-definition and high-frequency image signal such as A or high-definition has been required. At this time, it is difficult to operate the scanning circuit 205 and the sample-and-hold circuit 206 at a sufficient speed with respect to the frequency of the image signal. For this reason, as shown in FIGS. 19 and 20, a method of providing a plurality of systems of the logical operation circuit 302 and the scan control signal lines 301 shown in FIG. 17 and making the phases of the signals of the respective scan control signal lines 301 different is used. is there. As a result, a signal whose phase is shifted by a time shorter than the sampling pulse is output to each of the adjacent logic operation circuits 302 and the image signal is temporally processed in accordance with the output, thereby displaying a high-definition and high-frequency image signal. It can be performed.

In this case, as is apparent from FIG. 19, since the number of scan control signal lines 301 is increased, a large number of wiring cross sections are generated. Since the parasitic capacitance generated in the wiring is increased due to the parasitic capacitance generated in the cross portion, not only the circuit scale is increased but also the increase in power consumption due to the parasitic capacitance has been a problem.

Further, the delay time and the rise / fall time vary depending on the characteristics of the circuit for driving each of the scan control signal lines 301. For this reason, a pulse signal is output at a timing other than the timing at which it should be output, which adversely affects the sample and hold circuit and the like.

SUMMARY OF THE INVENTION The present invention has been made to solve such problems of the prior art, and reduces the number of wirings required by a scanning circuit constituting a driving circuit to reduce the circuit scale and power consumption. It is another object of the present invention to provide a scanning circuit capable of suppressing generation of glitches in an output.
It is another object of the present invention to provide a matrix-type image display device capable of obtaining a good output result on a display image by suppressing the occurrence of glitches.

[0010]

In order to achieve the above object,
The scanning circuit of the present invention comprises: L scan control signal lines used to set the direction and order of scanning; and logic of signals on M scan control signal lines among the L scan control signal lines. A first logical operation circuit that outputs a pulse signal by an operation, and a pulse signal that is set by a pulse signal output by the first logical operation circuit and output by a first logical operation circuit subsequent to the first logical operation circuit A flip-flop circuit to be reset, N timing control signal lines for setting timing of a scanning signal to be finally output, pulse signals of the N timing control signal lines, and pulse signals output from the flip-flop circuit And a second logical operation circuit for outputting a scanning signal by the logical operation of

[0011] Alternatively, the scanning circuit of the present invention comprises an L scan control signal line used to set the direction and order of scanning, and a glitch prevention pulse signal for transmitting a glitch prevention pulse for preventing glitches. A first logical operation circuit for outputting a pulse signal by performing a logical operation of the signal on the M scan control signal lines of the L scan control signal lines and the glitch prevention pulse; and the first logical operation Set by the pulse signal output from the circuit,
A flip-flop circuit reset by a pulse signal output from the first logical operation circuit subsequent to the first logical operation circuit, L timing control signal lines for setting the timing of the finally output scan signal, A second logical operation circuit that outputs a scanning signal by a logical operation of the N timing control signal lines and the pulse signal output from the flip-flop circuit.

Alternatively, the scanning circuit according to the present invention comprises an L scan control signal line used for setting a scanning direction and an order, and a glitch prevention pulse signal for transmitting a glitch prevention pulse for preventing a glitch from occurring. The signal on the M scan control signal lines of the L scan control signal lines or the signal on the M scan control signal lines of the L scan control signal lines and the glitch prevention. A first logical operation circuit that outputs a pulse signal by a logical operation with a pulse; and a first logical operation circuit that is set by the pulse signal output by the first logical operation circuit and that is subsequent to the first logical operation circuit. A flip-flop circuit reset by the output pulse signal,
N timing control signal lines for setting the timing of a scanning signal to be finally output, and a logical operation of the N timing control signal lines and a pulse signal output from the first logical operation circuit or the flip-flop circuit And a second logical operation circuit for outputting a scanning signal.

In each of the above configurations, a relationship L = M may be established between the total number L of the scan control signal lines and the number M of the scan control signal lines used by the first logical operation circuit.

Alternatively, a relationship of L = M × 2 is established between the total number L of the scan control signal lines and the number M of the scan control signal lines used by the first logical operation circuit, and the L scans The control signal lines are constituted by M sets of two scan control signal lines having opposite polarities, and the first logical operation circuit constitutes each set for each of the M sets of scan control signal lines. Either one of the two scan control signal lines may be used.

Alternatively, when the scanning circuit operates,
Of the L scan control signal lines, the signals on the M scan control signal lines and the remaining signals have opposite polarities and the combination of the M scan control signal lines having the same polarity has a fixed period. May be used.

In each of the above configurations, a signal on at least one of the scan control signal line and the glitch prevention pulse signal line may be used as a signal on the timing control signal line.

In each of the above configurations, there may be a plurality of outputs of the first logical operation circuit, whereby the same number of flip-flop circuits as the outputs of the first logical operation circuit may be controlled.

Further, the matrix type image display device of the present invention is a matrix type image display device including a data signal line drive circuit and a scan signal line drive circuit, wherein the data signal line drive circuit and the scan signal line are provided. At least one of the driving circuits can include any one of the above-described scanning circuits.

The operation of the present invention will be described below.

According to the present invention, the scanning signal is output by the logical operation of the output of the flip-flop circuit and the signal of the timing control signal line. Therefore, it is not necessary to provide a plurality of scanning control signal lines having different phases. The number of lines can be reduced. This reduces the crossover of the wiring,
Since the parasitic capacitance generated in the wiring is reduced, power consumption can be reduced as compared with the related art.

Further, the flip-flop circuit is designed so that the signal is not set or reset unless a signal having a pulse width sufficiently larger than a glitch generated by the first logic operation circuit is input due to a timing shift of a signal on the scan control signal line. Thus, a malfunction of the flip-flop circuit can be prevented, and a scanning signal can be output at a required timing.

Alternatively, glitch generation itself can be prevented by inputting a glitch prevention pulse for preventing the generation of glitch to the first logical operation circuit, and the scan can be performed at the required timing without malfunction of the flip-flop circuit. It can output signals.

Similarly, by inputting a glitch prevention pulse to the first logical operation circuit, the occurrence of glitches is suppressed, malfunction of the flip-flop circuit is prevented, and an output timing control signal line with the first logical operation circuit or the flip-flop circuit is provided. By performing a logical operation on these signals and outputting the signals, a scanning signal can be output at a required timing without glitches in a relatively simple circuit configuration.

In the above case, by adopting a configuration in which the relation L = M is established between the total number L of the scan control signal lines and the number M of the scan control signal lines used by the first logical operation circuit, The number of signal lines can be reduced.

Alternatively, the relationship L = M × 2 is established between the total number L of the scan control signal lines and the number M of the scan control signal lines used by the first logical operation circuit, and the L scan control signals are provided. The signal lines are constituted by M sets of two scan control signal lines having opposite polarities, and the first logical operation circuit constitutes each set for each of the M sets of scan control signal lines. By using one of the two scan control signal lines, the configurations of the first and second logical operation circuits and the flip-flop circuit can be the same in each stage.

Alternatively, when the scanning circuit operates,
Of the L scan control signal lines, the signals on the M scan control signal lines and the remaining signals have opposite polarities, and the combination of the M scan control signal lines having the same polarity has a constant period. With the switching configuration, the number of scan control signal lines can be reduced as much as possible, and at least the configuration of the first logical operation circuit can be the same in each stage.

In each of the above configurations, the signal on at least one of the scan control signal line and the glitch prevention pulse signal line is used as the signal on the timing control signal line, thereby further reducing the number of signal lines. Can be reduced.

Further, in each of the above structures, the first logical operation circuit outputs a plurality of signals, thereby controlling the same number of flip-flop circuits as the number of outputs, thereby reducing the number of elements used as a whole. Easy to do.

Further, the above-described scanning circuit is provided with at least one of the data signal line driving circuit and the scanning signal line driving circuit of the matrix type image display device including the data signal line driving circuit and the scanning signal line driving circuit. In this configuration, power consumption can be reduced and glitches can be prevented, so that a good output result can be obtained for a displayed image.

[0030]

Embodiments of the present invention will be specifically described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a scanning circuit according to a first embodiment of the present invention. In the present embodiment, the number of the scan control signal lines 101 is four for the sake of simplicity, but may be five or more.

This scanning circuit includes a scan control signal line 10
1, first logical operation circuit 102, flip-flop circuit 1
03, a timing control signal line 104 and a second logical operation circuit 105. First logical operation circuit 10
2 inputs the result of the logical operation of the signal input from the scan control signal line 101 to the set terminal (S) or the reset terminal (R) of the flip-flop circuit 103. At this time, the first logical operation circuit 10 that inputs a signal to the set terminal is supplied to one flip-flop circuit 103.
The signal of the first logical operation circuit 102, which is two stages later than two, is input to the reset terminal. Flip-flop circuit 10
3 inputs the signals to the four second logical operation circuits 105, respectively, and the second logical operation circuit 105 is connected to the signal input from the flip-flop circuit 103 and the timing control signal line 1.
A logical operation is performed with the signal of No. 04, and the operation result is output.

FIG. 2 shows a timing chart of this circuit. The signal of the scan control signal line 101-1 is a signal having a constant cycle T and a duty ratio of 50%, and the signals of the scan control signal lines 101-2 to 10-4 are respectively lower scan control signal lines 101-1 by 10 bits. These signals are synchronized with the fall of each of the signals No. to No. 3 and have a cycle twice as long. The operation of each first logical operation circuit 102 differs for each circuit.
The logical operation circuit 102-1 is connected to the scan control signal line 101-
When all of the signals 1 to 4 are Low, the first logical operation circuit 102-2 outputs a pulse signal when the signal of the scan control signal line 101-1 is Hi and the scan control signal line 1 is high.
When all of the signals 01-2 to 4 are Low, the first logical operation circuit 102-3 sets the signal of the scan control signal line 101-2 to Hi, and sets the scan control signal lines 101-1 and 31-1.
A pulse signal is output when all the signals of No. 4 are Low.
Therefore, the odd-numbered first logical operation circuit 102 is synchronized with the fall of the scan control signal line 101-1 while the even-numbered first logical operation circuit 102 is connected to the scan control signal line 101-1. In synchronism with the rise, a signal whose pulse width is T / 2 and whose phase is shifted by T / 2 in the adjacent first logical operation circuit 102 is output.

Here, the flip-flop circuit 103-1
Is set in synchronization with the rise of the output of the first logical operation circuit 102-1 and reset in synchronization with the rise of the output of the first logical operation circuit 102-3. For this reason,
The flip-flop circuit 103-1 is set and reset in synchronization with the fall of the signal on the scan control signal line 101-1.

On the other hand, the signal on the timing control signal line 104-1 is obtained by dividing the signal on the scan control signal line 101-1 by T / T with respect to the period T of the signal on the scan control signal line 101-1.
16 and the timing control signal line 10
Reference numerals 4-2 to 4-2 denote signals obtained by delaying the signals on the timing control signal lines 104-1 to 104-3 by T / 8. For this reason,
The signals on the timing control signal lines 104-1 to 10-4 fall sequentially after the flip-flop circuit 103-1 is set, and the signals on the timing control signal lines 104-1 to 10-4 before the flip-flop circuit 103-1 is reset. Rise sequentially. At this time, the second logical operation circuit 105-1
To 4 output the NOR of the output signal of the negative logic of the flip-flop circuit 103-1 and the signal of the timing control signal lines 104-1 to 104-4.
A pulse signal is output during a period in which the signals on the timing control signal lines 104-1 to 104-4 are at a low level from the time when 03-1 is set until the time when it is reset. This allows
Signals having the same pulse width and the timing shifted by a certain time interval are output.

Similarly, the flip-flop circuit 103-2
Are set and reset in synchronization with the rise of the signal on the scan control signal line 101-1.

On the other hand, the timing control signal lines 104-1 to 104-1
4 rises sequentially after the flip-flop circuit 103-2 is set, and the signal of the flip-flop circuit 10-2
The signals sequentially fall before 3-2 is reset.

At this time, the second logical operation circuits 105-5 to 105-5
Numeral 8 (outputs of 105-7 and 8 in FIG. 2 are omitted) outputs the logical product of the positive logic output signal of the flip-flop circuit 103-2 and the signals of the timing control signal lines 104-1 to 10-4. The flip-flop circuit 103
A pulse signal is output during a period in which the signals of the timing control signal lines 104-1 to 104-4 are at the Hi level from the time when -2 is set to the time when the signal is reset. As a result, signals having the same pulse width and shifted in timing at fixed time intervals are output.

The scanning circuit configured as described above outputs a signal having a constant pulse width and a timing shift at regular time intervals, and operates as a scanning circuit.

At this time, the number of signal lines input to the scanning circuit is 4 + 4 = 8, which is a half as compared with 4 × 4 = 16 in the conventional method shown in FIGS. As a result, the circuit scale and the parasitic capacitance generated in the wiring can be made smaller than before.

Here, assuming that the frequency of the signal on the scan control signal line 101-1 is f, the scan control signal line 101-1
The frequency of the -2 signal is f / 2, and the scan control signal line 10
The frequency of the signal 1-3 is f / 4, and the scan control signal line 1
The frequency of the signal 01-4 is f / 8. Therefore, 1
The signals on the scan control signal lines 101-1 to 101-4 are set to Hi for one second.
The number of times of switching from low to high or low to high is 2 · f, f, f / 2, f / 4, respectively, and (2 + 1 + 1/2 + ／) · in the entire scan control signal line.
f = 15 · f / 4 times.

In the conventional method, since four lines are required, 4.15 · f / 4 = 1 in the entire scan control signal line.
In this embodiment, since only four timing control signal lines 104 having a frequency f are required in this embodiment, even if the scan control signal line and the timing control signal line are combined, the number is one.
5 · f / 4 + 4 · 2 · f = 47 · f / 4 times, which is smaller than in the conventional case, and the power consumption can be reduced in parallel with the fact that the parasitic capacitance generated in the wiring can be reduced.

Further, since the scan signal is output by the logical operation of the signal of the flip-flop circuit 103 and the timing control signal line 104, the first logical operation circuit 102
If the flip-flop circuit 103 is designed so as not to be set or reset unless a signal having a pulse width sufficiently larger than the glitch generated by the occurrence of the glitch can be prevented, the malfunction of the flip-flop circuit 103 can be prevented, and the scanning signal can be generated at the required timing. Can be output.

(Second Embodiment) FIG. 3 shows a scanning circuit according to a second embodiment of the present invention.

This scanning circuit includes a scan control signal line 10
1, first logical operation circuit 102, flip-flop circuit 1
03, a timing control signal line 104, a second logical operation circuit 105, and a glitch prevention pulse signal line 106. The first logic operation circuit 102 performs a logical operation on a signal input from one of the scan control signal line 101 and the two anti-glitch pulse signal lines 106 to a set terminal or a reset terminal of the flip-flop circuit 103. To enter. At this time, for one flip-flop circuit 103, the signal of the first logical operation circuit 102 which is two stages later than the first logical operation circuit 102 which inputs a signal to the set terminal is input to the reset terminal. The flip-flop circuit 103 inputs signals to the four second logical operation circuits 105, respectively,
Reference numeral 5 performs a logical operation on a signal input from the flip-flop circuit 103 and a signal on the timing control signal line 104, and outputs an operation result.

FIG. 4 is a timing chart of this scanning circuit.
Shown in The signals on the scan control signal lines 101-1 to 101-3 correspond to the signals on the scan control signal lines 101-2 to 10-4 of the first embodiment. On the other hand, the anti-glitch pulse signal line 1
The signal 06-1 has a period T and a signal level Lo of 3T / 8 with respect to a period T at which the signal of the scan control signal line 101 switches, and the signal of the scan control signal line 101-1 T / 16 from rising and falling
The signal of the anti-glitch pulse signal line 106-2 is a signal that falls with only a delay.
06-1 is delayed by T / 2.

The operation of each first logical operation circuit 102 is different for each circuit, and the first logical operation circuit 102-1 includes scan control signal lines 101-1 to 31-1 and glitch prevention pulse signal line 1.
A pulse signal is output when all of the signals 06-1 are Low. The first logical operation circuit 102-2 includes the scan control signal lines 101-1 to 3 and the glitch prevention pulse signal line 10.
A pulse signal is output when all of the signals 6-2 are Low. The first logical operation circuit 102-3 outputs the signal Hi of the scan control signal line 101-1 and the scan control signal line 1
A pulse signal is output when all of the signals on 01-2, 3 and the glitch prevention pulse signal line 106-1 are Low. Therefore, the odd-numbered first logical operation circuit 102 is synchronized with the fall of the signal on the glitch prevention pulse signal line 106-1 while the even-numbered first logical operation circuit 102 is connected to the glitch prevention pulse signal line. In synchronization with the fall of the signal 106-2, a signal having a pulse width of 3T / 8 and a phase shifted by T / 2 in the adjacent first logical operation circuit 102 is output. At this time, the signal on the glitch prevention pulse signal line 106 falls after the signal on the scan control signal line 101 switches, and rises before the signal on the scan control signal line 101 switches.
Does not output a signal at the timing when the signal on the scan control signal line 101 is switched, so that it is possible to prevent the occurrence of a glitch due to the timing shift of the scan control signal line 101.

Here, the flip-flop circuit 103-1
Is set in synchronization with the rise of the output of the first logical operation circuit 102-1 and reset in synchronization with the rise of the output of the first logical operation circuit 102-3. For this reason,
The flip-flop circuit 103-1 is set and reset in synchronization with the fall of the signal on the glitch prevention pulse signal line 106-1.

On the other hand, the signal on the timing control signal line 104-1 is a signal having a period T and a duty ratio of 50% that falls T / 16 later than the fall of the glitch prevention pulse signal line 106-1. Control signal line 1
04-2 to 4-4 are the timing control signal lines 104-1.
3 are signals delayed by T / 8. Therefore, the signals on the timing control signal lines 104-1 to 104-1 fall sequentially after the flip-flop circuit 103-1 is set, and the timing control signal lines 104-1 to 104-1 before the flip-flop circuit 103-1 is reset. The signal of No. 4 sequentially rises.

At this time, the second logical operation circuits 105-1 to 105-1
4 outputs a NOR of the output signal of the negative logic of the flip-flop circuit 103-1 and the signals of the timing control signal lines 104-1 to 104-4.
A pulse signal is output during a period in which the signals on the timing control signal lines 104-1 to 104-4 are at a low level from when the signal 3-1 is set to when the signal 3-1 is reset. As a result, signals having the same pulse width and shifted in timing at fixed time intervals are output.

Similarly, flip-flop circuit 103-2
Are set and reset in synchronization with the fall of the signal on the glitch prevention pulse signal line 106-2.

On the other hand, as for the signal on the timing control signal line 104, the signals on the timing control signal lines 104-1 to 104-4 rise sequentially after the flip-flop circuit 103-2 is set, and the flip-flop circuit 103-2 is reset. Before that, the signals on the timing control signal lines 104-1 to 104-4 sequentially fall.

At this time, the second logical operation circuits 105-5 to 105-5
Numeral 8 (outputs of 105-7 and 8 in FIG. 4 are omitted) outputs the logical product of the positive logic output signal of the flip-flop circuit 103-2 and the signals of the timing control signal lines 104-1 to 10-4. Therefore, the flip-flop circuit 103-
A pulse signal is output during a period in which the signals on the timing control signal lines 104-1 to 104-4 are at the Hi level from when the signal 2 is set to when the signal is reset. As a result, signals having the same pulse width and shifted in timing at fixed time intervals are output.

The scanning circuit configured as described above outputs a signal having a constant pulse width and a timing shift at regular time intervals, and operates as a scanning circuit.

At this time, the number of signal lines input to the scanning circuit is 3 + 4 + 2 = 9, which is about a half as compared with 4 × 4 = 16 in the conventional method shown in FIGS. As a result, the circuit scale and the parasitic capacitance generated in the wiring can be made smaller than before.

In addition, similarly to the first embodiment, the total number of times that the signal of the scan control signal line 101 and the signal of the anti-glitch pulse signal line 106 are switched from Hi to Low or from Low to Hi in one second is smaller than that in the related art. Therefore, power consumption can be reduced in parallel with the fact that the parasitic capacitance can be reduced.

Further, since the first logical operation circuit 102 does not generate a glitch, the flip-flop circuit 103 does not malfunction and a scanning signal can be output at a required timing.

(Third Embodiment) FIG. 5 shows a scanning circuit according to a third embodiment of the present invention.

The scanning circuit includes a scan control signal line 10
1, first logical operation circuit 102, flip-flop circuit 1
03, a timing control signal line 104, a second logical operation circuit 105, and a glitch prevention pulse signal line 106. The first logical operation circuit 102 performs a logical operation on a signal input from one of three of the six scan control signal lines 101 and one of the two glitch prevention pulse signal lines 106, Circuit 10
3 is input to the set terminal or the reset terminal. At this time, for one flip-flop circuit 103, the signal of the first logical operation circuit 102 that is two stages later than the first logical operation circuit 102 that inputs a signal to the set terminal is input to the reset terminal. The flip-flop circuit 103 inputs signals to the four second logical operation circuits 105, respectively.
The second logical operation circuit 105 is a flip-flop circuit 103
Performs a logical operation on the signal input from the controller and the signal on the timing control signal line 104, and outputs the operation result.

FIG. 6 is a timing chart of this scanning circuit.
Shown in The signals on the scan control signal lines 101-1 to 3-5 are the scan control signal lines 101-1 to 101-1 of the second embodiment.
3 and the scan control signal line 101-
The signals 2, 4, and 6 are connected to the scan control signal line 101-1,
These signals are obtained by inverting the polarities of the signals 3 and 5. on the other hand,
The signal on the anti-glitch pulse signal line 106 corresponds to the signal on the anti-glitch pulse signal line 106 of the second embodiment.

One of the scan control signal lines 101-5 and 6 is connected to a terminal A of each first logical operation circuit 102, and one of the scan control signal lines 101-3 and 101 is connected to a terminal B. One of the scan control signal lines 101-1 and 2 is connected to C, and the anti-glitch pulse signal line 10 is connected to the terminal D.
Either one of 6-1 and 6-1 is input, and the combination differs for each first logical operation circuit 102. The first logical operation circuit 102-1 includes a scan control signal line 101-
1, 3, 5 and the signals of the anti-glitch pulse signal line 106-1 are input, and when all of them are low, a pulse signal is output. The first logical operation circuit 102-2 outputs the scan control signal line 101-1, 3, 5 and the signal of the glitch prevention pulse signal line 106-2 are input, and all of them are Lo.
The pulse signal is output at the time of w, and the first logical operation circuit 102
-3, the signals of the scan control signal lines 101-2, 10-3, and the glitch prevention pulse signal line 106-1 are input, and when all of them are low, a pulse signal is output. Therefore, the odd-numbered first logical operation circuit 102 is synchronized with the fall of the signal on the glitch prevention pulse signal line 106-1 while the even-numbered first logical operation circuit 102 is connected to the glitch prevention pulse signal line. In synchronism with the fall of the signal 106-2, a signal whose pulse width is 3T / 8 and whose phase is shifted by T / 2 by the adjacent first logical operation circuit 102 is output. At this time, since the signal on the glitch prevention pulse signal line 106 falls after the signal on the scan control signal line 101 switches, and rises before the signal on the scan control signal line 101 switches, each first logical operation circuit 102 No signal is output at the timing at which the signal on the scan control signal line 101 switches, so that the occurrence of a glitch due to a shift in the timing of the scan control signal line 101 can be prevented.

Here, the flip-flop circuit 103-1
Is set in synchronization with the rise of the output of the first logical operation circuit 102-1 and reset in synchronization with the rise of the output of the first logical operation circuit 102-3. For this reason,
The flip-flop circuit 103-1 is set and reset in synchronization with the fall of the signal on the glitch prevention pulse signal line 106-1.

On the other hand, the signal on the timing control signal line 104-1 is delayed by T / 16 with respect to the period T of the signal on the scan control signal line 101-1 from the fall of the anti-glitch pulse signal line 106-1. The falling signal is a signal having a period T and a duty ratio of 50%, and the signals on the timing control signal lines 104-3, 5, and 7 are
4-1 and 3 and 5 are T / 8 delayed signals,
The signals on the timing control signal lines 104-2, 4, 6, and 8 are signals obtained by inverting the polarities of the signals on the timing control signal lines 104-1, 3, 5, and 7. Therefore, the signals on the timing control signal lines 104-2, 4, 6, and 8 sequentially rise after the flip-flop circuit 103-1 is set, and the timing control signal line 104 is reset before the flip-flop circuit 103-1 is reset. The signals -2, 4, 6, and 8 fall sequentially.

At this time, the second logical operation circuits 105-1 to 105-1
4 outputs the logical product of the positive logic output signal of the flip-flop circuit 103-1 and the signals of the timing control signal lines 104-2, 4, 6, and 8, so that the flip-flop circuit 103-1 is set. A pulse signal is output during a period in which the signals of the timing control signal lines 104-2, 4, 6, and 8 are at the Hi level from the time the signal is reset to the time when the signal is reset. As a result, signals having the same pulse width and shifted in timing at fixed time intervals are output.

Similarly, flip-flop circuit 103-2
Are set and reset in synchronization with the fall of the signal on the glitch prevention pulse signal line 106-2.

On the other hand, as for the signal on the timing control signal line 104, the signals on the timing control signal lines 104-1, 3, 5, and 7 rise sequentially after the flip-flop circuit 103-2 is set, and the flip-flop circuit 103-2 Is reset before the timing control signal line 104-1,
Signals 3, 5, and 7 fall sequentially.

At this time, the second logical operation circuits 105-5 to 105-5
8 (the outputs of 105-7 and 8 are omitted in FIG. 6) is a positive logic output signal of the flip-flop circuit 103-2 and the timing control signal lines 104-1, 3, 5, and 7
In which the signals on the timing control signal lines 104-1, 3, 5, and 7 are at the Hi level from the time when the flip-flop circuit 103-2 is set until the time when the flip-flop circuit 103-2 is reset in order to output the logical product of the signals. To output a pulse signal. As a result, signals having the same pulse width and the timing shifted by a certain time interval are output.

The scanning circuit configured as described above outputs a signal with a constant pulse width and a timing shift at regular time intervals, and operates as a scanning circuit.

At this time, the number of signal lines input to the scanning circuit is 6 + 8 + 2 = 16, and the method of selecting and using three of the six scan control signal lines in this embodiment is shown in FIGS. It is halved compared to 8 × 4 = 32 lines when applied to 20 conventional methods. As a result, the circuit scale and the parasitic capacitance generated in the wiring can be made smaller than before.

In addition, similarly to the first and second embodiments, the total number of times that the signal of the scan control signal line 101 and the signal of the anti-glitch pulse signal line 106 are switched from Hi to Low or from Low to Hi in one second is equal to the conventional value. Power consumption can be reduced in parallel with the fact that the parasitic capacitance can be reduced.

Further, since the first logical operation circuit 102 does not generate a glitch, the flip-flop circuit 103 does not malfunction and a scanning signal can be output at a required timing.

Further, the timing of the signal output from the first logical operation circuit 102 is adjusted by a combination of the scan control signal line 101 for inputting a signal to the first logical operation circuit 102 and the glitch prevention pulse signal line 106. Therefore, the configuration of each first logical operation circuit 102 can be the same.

(Fourth Embodiment) FIG. 7 shows a scanning circuit according to a fourth embodiment of the present invention.

This scanning circuit is connected to the scan control signal line 10
1, first logical operation circuit 102, flip-flop circuit 1
03, a timing control signal line 104, a second logical operation circuit 105, and a glitch prevention pulse signal line 106. The first logical operation circuit 102 performs a logical operation on a signal input from two of the five scan control signal lines 101 and one of the two glitch prevention pulse signal lines 106, Circuit 1
03 is input to the set terminal or the reset terminal. At this time, for one flip-flop circuit 103, the signal of the first logical operation circuit 102 that is two stages later than the first logical operation circuit 102 that inputs a signal to the set terminal is input to the reset terminal. The flip-flop circuit 103
A signal is input to each of the four second logical operation circuits 105, and the second logical operation circuit 105
03 and the timing control signal line 104
And performs a logical operation on the signal and outputs the operation result.

FIG. 8 is a timing chart of this scanning circuit.
Shown in Regarding each signal of the scan control signal line 101, when operating the scanning circuit, two of the five signal lines are always at the low level and the remaining three are at the high level, and the combination of the signal lines at the low level is constant. In the cycle T. On the other hand, the signal on the anti-glitch pulse signal line 106 is
Anti-glitch pulse signal line 1 of second and third embodiments
06 signal.

To each of the first logical operation circuits 102, only two of the scan control signal lines 101-1 to 101-5 and one of the glitch prevention pulse signal lines 106-1 and 106-2 are input. Different for each first logical operation circuit 102. The first logical operation circuit 102-1 includes the scan control signal lines 101-1 and 101-2 and the glitch prevention pulse signal line 106.
And a pulse signal is output when all of them are low. First logical operation circuit 102-2
Receives the scan control signal lines 101-1 and 101-2 and the signal of the glitch prevention pulse signal line 106-2, and outputs a pulse signal when all of them are low. The first logical operation circuit 102-3 includes a scan control signal line 101-1;
3 and the signal of the anti-glitch pulse signal line 106-1 are input, and when all of them are low, a pulse signal is output. Therefore, the odd-numbered first logical operation circuit 102 synchronizes with the fall of the signal on the glitch prevention pulse signal line 106-1 while the even-numbered first logical operation circuit 10
2 outputs a signal whose pulse width is 3T / 8 and whose phase is shifted by T / 2 in the adjacent first logical operation circuit 102 in synchronization with the fall of the signal on the glitch prevention pulse signal line 106-2. I do. At this time, the signal on the glitch prevention pulse signal line 106 falls after the signal on the scan control signal line 101 switches, and the signal on the scan control signal line 101
Rises before the signal of the scan control signal line 101 is switched, so that each first logical operation circuit 102 does not output a signal at the timing of switching of the signal of the scan control signal line 101. Can be prevented from occurring.

Here, the flip-flop circuit 103-1
Is set in synchronization with the rise of the output of the first logical operation circuit 102-1 and reset in synchronization with the rise of the output of the first logical operation circuit 102-3. For this reason,
The flip-flop circuit 103-1 is set and reset in synchronization with the fall of the signal on the glitch prevention pulse signal line 106-1.

On the other hand, the signal on the timing control signal line 104-1 is delayed by T / 16 with respect to the period T of the signal on the scan control signal line 101-1 from the fall of the glitch prevention pulse signal line 106-1. This is a falling signal having a period T and a duty ratio of 50%. The signals on the timing control signal lines 104-3, 5, and 7 are
4-1 and 3 and 5 are T / 8 delayed signals,
The signals on the timing control signal lines 104-2, 4, 6, and 8 are signals obtained by inverting the polarities of the signals on the timing control signal lines 104-1, 3, 5, and 7. Therefore, the signals on the timing control signal lines 104-2, 4, 6, and 8 sequentially rise after the flip-flop circuit 103-1 is set, and the timing control signal line 104 is reset before the flip-flop circuit 103-1 is reset. The signals -2, 4, 6, and 8 fall sequentially.

At this time, the second logical operation circuits 105-1 to 105-1
4 outputs the logical product of the positive logic output signal of the flip-flop circuit 103-1 and the signals of the timing control signal lines 104-2, 4, 6, and 8, so that the flip-flop circuit 103-1 is set. A pulse signal is output during a period in which the signals of the timing control signal lines 104-2, 4, 6, and 8 are at the Hi level during a period from reset to reset. As a result, signals having the same pulse width and shifted in timing at fixed time intervals are output.

Similarly, flip-flop circuit 103-2
Are set and reset in synchronization with the fall of the signal on the glitch prevention pulse signal line 106-2.

On the other hand, the signals on the timing control signal lines 104 are sequentially raised after the flip-flop circuit 103-2 is set, and the signals on the timing control signal lines 104-1, 3, 5, and 7 rise sequentially. 2 is reset before the timing control signal line 104-1,
Signals 3, 5, and 7 fall sequentially.

At this time, the second logical operation circuits 105-5 to 105-5
8 (outputs of 105-7 and 8 in FIG. 8 are omitted) is a positive logic output signal of the flip-flop circuit 103-2 and the timing control signal lines 104-1, 3, 5, and 7
The signals on the timing control signal lines 104-1, 3, 5, and 7 during the period from when the flip-flop circuit 103-2 is set to when it is reset are at the Hi level. A pulse signal is output during the period. As a result, signals having the same pulse width and shifted in timing at fixed time intervals are output.

The scanning circuit configured as described above outputs a signal having a constant pulse width and a timing shift at regular time intervals, and operates as a scanning circuit.

At this time, the number of signal lines input to the scanning circuit is 5 + 8 + 2 = 15, and the method of selecting and using two of the five scan control signal lines performed in this embodiment is shown in FIGS. This is 3/4 compared to 5 × 4 = 20 lines when applied to 20 conventional methods. As a result, the circuit scale and the parasitic capacitance generated in the wiring can be made smaller than before.

In addition, as in the first to third embodiments, 1
The signal of the scan control signal line 101 and the glitch prevention pulse signal line 106 changes from Hi to Low or Lo
Since the total number of times of switching from w to Hi is smaller than in the related art, power consumption can be reduced in parallel with the reduction in parasitic capacitance.

Further, since the first logical operation circuit 102 does not generate a glitch, the flip-flop circuit 103 does not malfunction and a scan signal can be output at a required timing.

Further, since the first logical operation circuit 102 does not generate a glitch, the flip-flop circuit 103 does not malfunction and a scanning signal can be output at a required timing.

Further, the timing of the signal output from the first logical operation circuit 102 is adjusted by a combination of the scan control signal line 101 for inputting a signal to the first logical operation circuit 102 and the glitch prevention pulse signal line 106. Therefore, the configuration of each first logical operation circuit 102 can be the same.

(Fifth Embodiment) FIG. 9 shows a scanning circuit according to a fifth embodiment of the present invention.

The scanning circuit includes a scan control signal line 10
1, first logical operation circuit 102, flip-flop circuit 1
03, a timing control signal line 104, a second logical operation circuit 105, and a glitch prevention pulse signal line 106. The first logical operation circuit 102 performs a logical operation on signals input from three of the six scan control signal lines 101 and two of the four anti-glitch pulse signal lines 106, and outputs the result of the flip-flop circuit 103 is input to the set terminal or the reset terminal. At this time,
For one flip-flop circuit 103, the signal of the first logical operation circuit 102, which is two stages later than the first logical operation circuit 102 that inputs a signal to the set terminal, is input to the reset terminal. The flip-flop circuit 103 inputs a signal to each of the four second logical operation circuits 105, and the second logical operation circuit 105 performs a logical operation on a signal input from the flip-flop circuit 103 and a signal on the timing control signal line 104. And outputs the operation result.

FIG. 1 is a timing chart of this scanning circuit.
0 is shown. The signals on the scan control signal lines 101-1 to 10-6 are the same as the scan control signal lines 101-1 to 10-6 of the third embodiment.
Signal. On the other hand, the signal of the anti-glitch pulse signal line 106-1 is connected to the scan control signal line 101-1.
, The cycle is T, the duty ratio is 50%, and the scan control signal line 10
It is a signal that falls T / 16 earlier than the rise and fall of 1-1. The signal on the anti-glitch pulse signal line 106-3 is
The signal of the anti-glitch pulse signal lines 106-2 and 106-4 is a signal obtained by inverting the polarity of the signal of the anti-glitch pulse signal lines 106-1 and 106-3. .

One of the scan control signal lines 101-5 and 6 is connected to the terminal A of each first logical operation circuit 102, and one of the scan control signal lines 101-3 and 101 is connected to the terminal B. One of the scan control signal lines 101-1 and 2 is connected to C, and the anti-glitch pulse signal line 10 is connected to the terminal D.
Either one of 6-1 and 2-1 is input to the terminal E, and one of the glitch prevention pulse signal lines 106-3 and 106 is input to the terminal E, and the combination is different for each first logical operation circuit 102. The first logical operation circuit 102-1 receives the signals of the scan control signal lines 101-1, 3, 5 and the anti-glitch pulse signal lines 106-1 and 10-3.
Outputs a pulse signal when ow. First logical operation circuit 1
02-2 receives the signals of the scan control signal lines 101-1, 3, 5 and the glitch prevention pulse signal lines 106-2 and 106-4, and outputs a pulse signal when all of them are low. The first logical operation circuit 102-3 includes the scan control signal lines 101-2, 3, 5 and the glitch prevention pulse signal line 1.
06-1, 3 are input and they are all Lo.
A pulse signal is output at the time of w. For this reason, the first logic operation circuit 102 of the odd-numbered stage is connected to the glitch prevention pulse signal line 1
In synchronization with the falling edge of the signal 06-3, the even-numbered first logical operation circuit 102 has a pulse width of 3T / 8 in synchronization with the falling edge of the signal on the glitch prevention pulse signal line 106-4. And the adjacent first logical operation circuit 10
2, a signal whose phase is shifted by T / 2 is output. At this time, the signal on the glitch prevention pulse signal line 106-3 falls after the signal on the scan control signal line 101 switches, and the signal on the glitch prevention pulse signal line 106-4 switches on the scan control signal line 101. Since the first logical operation circuit 102 rises before, the first logical operation circuit 102 does not output a signal at the timing when the signal of the scan control signal line 101 switches, and therefore, it is possible to prevent the occurrence of a glitch due to the timing shift of the scan control signal line 101. .

Here, the flip-flop circuit 103-1
Is set in synchronization with the rise of the output of the first logical operation circuit 102-1 and reset in synchronization with the rise of the output of the first logical operation circuit 102-3. For this reason,
The flip-flop circuit 103-1 is set and reset in synchronization with the fall of the signal on the glitch prevention pulse signal line 106-3.

On the other hand, the signal on the timing control signal line 104-1 is the signal on the glitch prevention pulse signal line 106-3 as T.
/ 8 delayed signal, and the timing control signal line 10
The signal 4-3 is a signal obtained by delaying the signal on the timing control signal line 104-1 by T / 8. The signals on the timing control signal lines 104-2 and 44-2 are
These are signals obtained by inverting the polarities of the signals 1 and 3. Therefore, after the flip-flop circuit 103-1 is set, the signals on the timing control signal lines 104-2 and 104-2 and the anti-glitch pulse signal lines 106-1 and 10-3 sequentially rise, and the flip-flop circuit 103-1 is reset. Before or almost simultaneously, the signals on the timing control signal lines 104-2 and 4-4 and the glitch prevention pulse signal lines 106-1 and 3 fall sequentially.

At this time, the second logical operation circuits 105-1 to 105-1
4 outputs a logical product of a positive logic output signal of the flip-flop circuit 103-1 and signals of the timing control signal lines 104-2 and 44-2 and the glitch prevention pulse signal lines 106-1 and 36-1. A pulse signal is output during a period in which the signals on the timing control signal lines 104-2 and 104-2 and the anti-glitch pulse signal lines 106-1 and 106-3 during the period from when the circuit 103-1 is set to when it is reset are high. . As a result, signals having the same pulse width and shifted in timing at fixed time intervals are output.

Similarly, flip-flop circuit 103-2
Are reset in synchronization with the fall of the signal on the glitch prevention pulse signal line 106-4.

On the other hand, the signal on the timing control signal line 104 is the signal on the timing control signal lines 104-1 and 104-1 and the signal on the glitch prevention pulse signal lines 106-2 and 106-2 and 4 after the flip-flop circuit 103-2 is set. The signals on the timing control signal lines 104-1 and 104-1 and the glitch prevention pulse signal lines 106-2 and 106-4 fall sequentially or almost simultaneously before the flip-flop circuit 103-2 is reset.

At this time, the second logical operation circuits 105-5 to 105-5
8 (outputs of 105-7 and 8 in FIG. 10 are omitted) is a positive logic output signal of the flip-flop circuit 103-2, the timing control signal lines 104-1, 3 and the glitch prevention pulse signal line 106. -2, 4 and a flip-flop circuit 103-2
The pulse signal is output during a period in which the signals on the timing control signal lines 104-1 and 34-1 and the glitch prevention pulse signal lines 106-2 and 106-2 and 4 are at Hi level from when the signal is set to when it is reset. As a result, signals having the same pulse width and shifted in timing at fixed time intervals are output.

The scanning circuit configured as described above outputs a signal having a constant pulse width and a timing shift at regular time intervals, and operates as a scanning circuit.

Here, the number of signal lines input to the scanning circuit is 6 + 4 + 4 = 14, and the method of selecting and using three of the six scan control signal lines performed in the present embodiment is shown in FIGS. This is less than half compared to 8 × 4 = 32 lines when applied to 20 conventional methods. As a result, the circuit scale and the parasitic capacitance generated in the wiring can be made smaller than before.

In addition, as in the first to fourth embodiments, 1
The signal of the scan control signal line 101 and the glitch prevention pulse signal line 106 changes from Hi to Low or Lo
Since the total number of times of switching from w to Hi is smaller than in the related art, power consumption can be reduced in parallel with the reduction in parasitic capacitance.

Since the first logical operation circuit 102 does not generate a glitch, the flip-flop circuit 103 does not malfunction and the scanning signal can be output at a required timing.

Further, the timing of the signal output from the first logical operation circuit 102 is adjusted by the combination of the scan control signal line 101 for inputting a signal to the first logical operation circuit 102 and the glitch prevention pulse signal line 106. ,
The configuration of each first logical operation circuit 102 can be the same.

(Sixth Embodiment) FIG. 11 shows a scanning circuit according to a sixth embodiment of the present invention.

This scanning circuit is connected to the scan control signal line 10
1, first logical operation circuit 102, flip-flop circuit 1
03, a timing control signal line 104, a second logical operation circuit 105, and a glitch prevention pulse signal line 106. The first logical operation circuit 102 performs logical operation on three of the six scan control signal lines 101 and a signal input from one of the glitch prevention pulse signal lines 106. The first logical operation circuit 102 in the odd-numbered stage inputs the operation result to four second logical operation circuits 105, and the first logical operation circuit 102 in the even-numbered stage inputs the set terminal or the reset terminal of the flip-flop circuit 103. At this time, for one flip-flop circuit 103, the signal of the first logical operation circuit 102 that is two stages later than the first logical operation circuit 102 that inputs a signal to the set terminal is input to the reset terminal. The flip-flop circuit 103 inputs a signal to each of the four second logical operation circuits 105 similarly to the first logical operation circuit 102 of the odd-numbered stage, and the second logical operation circuit 1
05 performs a logical operation on a signal input from the odd-numbered first logical operation circuit 102 or flip-flop circuit 103 and a signal on the timing control signal line 104, and outputs an operation result.

FIG. 1 is a timing chart of this scanning circuit.
It is shown in FIG. The signals on the scan control signal lines 101-1 to 101-6 are the scan control signal lines 101 of the third and fifth embodiments.
-1 to -6. On the other hand, the signal on the glitch prevention pulse signal line 106 is
Is 3T / 8, and the period during which the signal level is Low is 3T / 8, and is delayed by T / 2 from the rise and fall of the scan control signal line 101-1. It is a signal that falls.

One of the scan control signal lines 101-5 and 6 is connected to the terminal A of each first logical operation circuit 102, and one of the scan control signal lines 101-3 and 101 is connected to the terminal B. One of the scan control signal lines 101-1 and 101-2 is input to C, and the glitch prevention pulse signal line 106 is input to a terminal D that exists only in the even-numbered first logical operation circuit 102. The combination of signals input to C differs for each first logical operation circuit 102. The first logical operation circuit 102-1 includes a scan control signal line 101-
Signals 1, 3, and 5 are input, and when all of them are low, a pulse signal is output. First logical operation circuit 102-
Signals 2 are input to the scan control signal lines 101-1, 3, 5 and the glitch prevention pulse signal line 106, and output a pulse signal when all of them are low. The first logical operation circuit 102-3 is connected to the scan control signal line 101-
Signals 2, 3, and 5 are input, and when all of them are low, a pulse signal is output. Therefore, the odd-numbered first stage
The logical operation circuit 102 synchronizes with the rise and fall of the control signal line 101-1, while the first logical operation circuit 102 of the even-numbered stage synchronizes with the fall of the signal of the glitch prevention pulse signal line 106 and respectively. The pulse width is T /
2 and 3T / 8, and the adjacent first logical operation circuit 102
Output a signal whose rising timing is shifted by T / 2. At this time, the signal on the glitch prevention pulse signal line 106 falls after the signal on the scan control signal line 101 switches, and rises before the signal on the scan control signal line 101 switches.
No. 2 does not output a signal at the timing when the signal of the scan control signal line 101 switches, and therefore, it is possible to prevent the occurrence of a glitch due to a timing shift of the scan control signal line 101.

Here, the timing control signal line 104-1
Signal has a period T of the signal of the scan control signal line 101-1 rather than the fall of the scan control signal line 101-1.
Is a signal having a period T and a duty ratio of 50%, which falls with a delay of T / 16. Timing control signal line 10
4-3, 5 and 7 are the timing control signal lines 104-
The signals on the timing control signal lines 104-2, 4, 6, and 8 are the signals obtained by delaying the signals on the timing control signal lines 104-2, 4, 6, and 7 by T / 8. This is a signal obtained by inverting the polarity of the signal. Therefore, after the output signal of the first logical operation circuit 102-1 rises, the signals of the timing control signal lines 104-2, 4, 6, and 8 sequentially rise, and the output signal of the first logical operation circuit 102-1 rises. Before falling, the timing control signal lines 104-2, 4,
Signals 6 and 8 fall sequentially. At this time, the second logical operation circuits 105-1 to 104-1 are connected to the first logical operation circuit 102-1.
Output signals and timing control signal lines 104-2, 4,
In order to output a logical product of the signals 6 and 8, the output signal of the first logical operation circuit 102-1 and the timing control signal line 10
A pulse signal is output during a period when the signals 4-2, 4, 6, and 8 are at the Hi level. As a result, signals having the same pulse width and shifted in timing at fixed time intervals are output.

Next, the flip-flop circuit 103-1
Is set in synchronization with the rising edge of the output of the first logical operation circuit 102-2, and is reset in synchronization with the rising edge of the output of the first logical operation circuit 102-4. For this reason,
The flip-flop circuit 103-1 is set and reset in synchronization with the fall of the signal on the glitch prevention pulse signal line 106-1.

On the other hand, the signals on the timing control signal lines 104 are sequentially raised after the flip-flop circuit 103-1 is set, and the signals on the timing control signal lines 104-1, 3, 5, and 7 rise sequentially. 1 is reset before the timing control signal line 104-1,
Signals 3, 5, and 7 fall sequentially.

At this time, the second logical operation circuits 105-5 to 105-5
Reference numeral 8 (outputs of 105-7 and 8 in FIG. 12 are omitted) is a positive logic output signal of the flip-flop circuit 103-1 and the timing control signal lines 104-1, 3, 5, and 7.
The signals on the timing control signal lines 104-1, 3, 5, and 7 during the period from when the flip-flop circuit 103-1 is set to when it is reset are at the Hi level. A pulse signal is output during the period. As a result, signals having the same pulse width and shifted in timing at fixed time intervals are output.

The scanning circuit configured as described above outputs a signal having a constant pulse width and a timing shift at fixed time intervals, and operates as a scanning circuit.

At this time, the number of signal lines input to the scanning circuit is 6 + 8 + 1 = 15, and the method of selecting and using three of the six scan control signal lines performed in the present embodiment is shown in FIGS. This is less than half compared to 8 × 4 = 32 lines when applied to 20 conventional methods. As a result, the circuit scale and the parasitic capacitance generated in the wiring can be made smaller than before.

In addition, as in the first to fifth embodiments, 1
The signal of the scan control signal line 101 and the glitch prevention pulse signal line 106 changes from Hi to Low or Lo
Since the total number of times of switching from w to Hi is smaller than in the related art, power consumption can be reduced in parallel with the reduction in parasitic capacitance.

The first logical operation circuit 102 of the odd-numbered stage
Does not output a signal when the first logical operation circuit 102 generates a glitch, and the first logical operation circuit 102 in an even-numbered stage does not generate a glitch, so the flip-flop circuit 103 Does not malfunction, the scanning signal can be output at the required timing.

Further, the timing of the signal output from the first logical operation circuit 102 is adjusted by the combination of the scan control signal line 101 for inputting a signal to the first logical operation circuit 102 and the glitch prevention pulse signal line 106. Therefore, the configuration of each first logical operation circuit 102 in the odd-numbered stage or each first logical operation circuit 102 in the even-numbered stage can be the same.

Further, since one flip-flop circuit 103 can be provided in two stages, the circuit configuration can be simplified.

(Seventh Embodiment) FIG. 13 shows a scanning circuit according to a seventh embodiment of the present invention.

This scanning circuit is connected to the scan control signal line 10
1, first logical operation circuit 102, flip-flop circuit 1
03, a timing control signal line 104, a second logical operation circuit 105, and a glitch prevention pulse signal line 106. The first logical operation circuit 102 is a logical operation of three signals out of the six scan control signal lines 101 and a signal input from one of the two glitch prevention pulse signal lines 106. Are input to set terminals or reset terminals of different flip-flop circuits 103, respectively.

At this time, one flip-flop circuit 1
03, the first logical operation circuit 10 which is one stage later than the first logical operation circuit 102 which inputs a signal to the set terminal.
One of the two output signals is input to the reset terminal. The flip-flop circuit 103 inputs signals to the four second logical operation circuits 105, respectively,
Reference numeral 5 performs a logical operation on a signal input from the flip-flop circuit 103 and a signal on the timing control signal line 104, and outputs an operation result.

FIG. 1 is a timing chart of this scanning circuit.
It is shown in FIG. The signals on the scan control signal lines 101-1 to 10-6 correspond to the signals on the scan control signal lines 101-1 to 10-6 of the third, fifth, and sixth embodiments. On the other hand, the signals on the anti-glitch pulse signal line 106 are the second and third signals,
This corresponds to a signal obtained by inverting the polarity of the signal on the anti-glitch pulse signal line 106 of the fourth embodiment.

One of the scan control signal lines 101-5 and 6 is connected to the terminal A of each first logical operation circuit 102, and one of the scan control signal lines 101-3 and 101 is connected to the terminal B. One of the scan control signal lines 101-1 and 2 is connected to C, and the anti-glitch pulse signal line 10 is connected to the terminal D.
6-1. The terminal E has a glitch prevention pulse signal line 106.
The combination of signals input to the terminals A to C is different for each first logical operation circuit 102.
The signals of the scan control signal lines 101-1 to 101-3 are input to the terminals A to C of the first logical operation circuit 102-1. The first logical operation circuit 102-1 is configured such that they are all Low.
And when the anti-glitch pulse signal line 106-1 is Hi, a pulse signal is output to the output X of the first logical operation circuit 102-1. On the other hand, all of them are Low and the anti-glitch pulse signal line 106-2 Is Hi, a pulse signal is output to the output Y of the first logical operation circuit 102-1. Similarly, signals of the scan control signal lines 101-2, 3 and 5 are input to terminals A to C of the first logical operation circuit 102-2. The first logical operation circuits 102-2 are all L
ow, when the signal of the anti-glitch pulse signal line 106-1 is Hi, a pulse signal is output to the output X of the first logic operation circuit 102-2, while the signal of the anti-glitch pulse signal line 106-2 is When all are Low, a pulse signal is output to the output Y of the first logical operation circuit 102-2. Therefore, the output X of the first logical operation circuit 102 is synchronized with the rise of the signal on the glitch prevention pulse signal line 106-1, while the output Y of the first logical operation circuit 102 is the glitch prevention pulse signal line 106-2. In synchronization with the rise of the signal, a signal having a pulse width of 3T / 8 and a phase shifted by T / 2 in the adjacent first logical operation circuit 102 is output. At this time, since the signal on the glitch prevention pulse signal line 106 rises after the signal on the scan control signal line 101 switches and falls before the signal on the scan control signal line 101 switches, each first logical operation circuit 102 No signal is output at the timing at which the signal on the scan control signal line 101 switches, so that the occurrence of a glitch due to a shift in the timing of the scan control signal line 101 can be prevented.

Here, the flip-flop circuit 103-1
Is set in synchronization with the rise of the output X of the first logical operation circuit 102-1 and reset in synchronization with the rise of the output X of the first logical operation circuit 102-2. Therefore, the flip-flop circuit 103-1 is set and reset in synchronization with the rise of the signal on the glitch prevention pulse signal line 106-1.

On the other hand, the signal on the timing control signal line 104-1 rises T / 16 later than the cycle T of the signal on the scan control signal line 101-1 than the rise of the glitch prevention pulse signal line 106-1. This is a signal with a period T and a duty ratio of 50% that goes down. The signals on the timing control signal lines 104-3, 5, and 7 are
4-1 and 3 and 5 are T / 8 delayed signals,
The signals on the timing control signal lines 104-2, 4, 6, and 8 are signals obtained by inverting the polarities of the signals on the timing control signal lines 104-1, 3, 5, and 7. Therefore, the signals on the timing control signal lines 104-2, 4, 6, and 8 sequentially rise after the flip-flop circuit 103-1 is set, and the timing control signal line 104 is reset before the flip-flop circuit 103-1 is reset. The signals -2, 4, 6, and 8 fall sequentially.

At this time, the second logical operation circuits 105-1 to 105-1
4 outputs the logical product of the positive logic output signal of the flip-flop circuit 103-1 and the signals of the timing control signal lines 104-2, 4, 6, and 8, so that the flip-flop circuit 103-1 is set. A pulse signal is output during a period in which the signals of the timing control signal lines 104-2, 4, 6, and 8 are at the Hi level from the time the signal is reset to the time when the signal is reset. As a result, signals having the same pulse width and shifted in timing at fixed time intervals are output.

Similarly, flip-flop circuit 103-2
Are set and reset in synchronization with the rise of the signal on the glitch prevention pulse signal line 106-2.

On the other hand, as for the signal on the timing control signal line 104, the signals on the timing control signal lines 104-1, 3, 5, and 7 sequentially rise after the flip-flop circuit 103-2 is set, and the flip-flop circuit 103-2 Is reset before the timing control signal line 104-1,
Signals 3, 5, and 7 fall sequentially.

At this time, the second logical operation circuits 105-5 to 105-5
Reference numeral 8 (outputs of 105-7 and 8 in FIG. 14 are omitted) is a positive logic output signal of the flip-flop circuit 103-2 and the timing control signal lines 104-1, 3, 5, and 7.
In which the signals on the timing control signal lines 104-1, 3, 5, and 7 are at the Hi level from the time when the flip-flop circuit 103-2 is set until the time when the flip-flop circuit 103-2 is reset in order to output the logical product of the signals. To output a pulse signal. As a result, signals having the same pulse width and shifted in timing at fixed time intervals are output.

The scanning circuit configured as described above outputs a signal having a constant pulse width and a timing shift at regular time intervals, and operates as a scanning circuit.

At this time, the number of signal lines input to the scanning circuit is 6 + 8 + 2 = 16, and the method of selecting and using three of the six scan control signal lines in this embodiment is shown in FIGS. It is halved compared to 8 × 4 = 32 lines when applied to 20 conventional methods. As a result, the circuit scale and the parasitic capacitance generated in the wiring can be made smaller than before.

In addition, as in the first to sixth embodiments, 1
The signal of the scan control signal line 101 and the glitch prevention pulse signal line 106 changes from Hi to Low or Lo
Since the total number of times of switching from w to Hi is smaller than in the related art, power consumption can be reduced in parallel with the reduction in parasitic capacitance.

Further, since the first logical operation circuit 102 does not generate a glitch, the flip-flop circuit 103 does not malfunction and the scanning signal can be output at a required timing.

Further, the first logical operation circuit 1 is formed by a combination of a scan control signal line 101 for inputting a signal to the first logical operation circuit 102 and a glitch prevention pulse signal line 106.
Since the timing of the signal output from the second logical operation circuit 102 is adjusted, the configuration of each first logical operation circuit 102 can be made the same.

Further, since two flip-flop circuits 103 can be driven by one first logical operation circuit 102, the circuit configuration can be simplified.

The various scanning circuits described in the above-described first to seventh embodiments are provided in one or both of a data signal line driving circuit and a scanning signal line driving circuit which are added to a matrix type image display device. You may do so.
Further, in a matrix type image display device, it may be provided in one or both of a data signal line driving circuit and a scanning signal line driving circuit provided on the same substrate as an integrated substrate type. In such a matrix type image display device including the scanning circuit of the present invention, it is possible to suppress the occurrence of glitch in the output of the scanning circuit, so that a good output result can be obtained on the display screen.

[0136]

According to the present invention, the number of signals required by the scanning circuit constituting at least one of the data signal line driving circuit and the scanning signal line driving circuit for driving the matrix type image display device is relatively small. This can be reduced with a simple circuit configuration, and the circuit scale and power consumption can be reduced. In addition, by providing such a scanning circuit in at least one of the data signal line driving circuit and the scanning signal line driving circuit, it is possible to suppress the occurrence of glitch in the output of the scanning circuit, and to obtain a favorable output result on a display image. Can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a scanning circuit according to a first embodiment.

FIG. 2 is a timing chart of the scanning circuit of FIG.

FIG. 3 is a circuit diagram illustrating a scanning circuit according to a second embodiment.

FIG. 4 is a timing chart of the scanning circuit of FIG. 3;

FIG. 5 is a circuit diagram showing a scanning circuit according to a third embodiment.

FIG. 6 is a timing chart of the scanning circuit of FIG.

FIG. 7 is a circuit diagram illustrating a scanning circuit according to a fourth embodiment.

FIG. 8 is a timing chart of the scanning circuit of FIG. 7;

FIG. 9 is a circuit diagram showing a scanning circuit according to a fifth embodiment.

FIG. 10 is a timing chart of the scanning circuit of FIG. 9;

FIG. 11 is a circuit diagram showing a scanning circuit according to a sixth embodiment.

FIG. 12 is a timing chart of the scanning circuit of FIG. 11;

FIG. 13 is a circuit diagram illustrating a scanning circuit according to a seventh embodiment.

FIG. 14 is a timing chart of the scanning circuit of FIG.

FIG. 15 is a schematic diagram illustrating a configuration of a matrix type image display device.

FIG. 16 is a schematic diagram showing a configuration of a data signal line driving circuit used in a matrix type image display device.

FIG. 17 is a circuit diagram showing an example of a scanning circuit forming a data signal line driving circuit or a scanning signal line driving circuit used in a matrix type image display device.

FIG. 18 is a timing chart of the scanning circuit of FIG.

FIG. 19 illustrates another example of a scanning circuit included in a data signal line driving circuit or a scanning signal line driving circuit used in a matrix type image display device.

20 is a timing chart of the scanning circuit of FIG.

[Explanation of symbols]

 Reference Signs List 101 scan control signal line 102 first logical operation circuit 103 flip-flop circuit 104 timing control signal line 105 second logical operation circuit 106 anti-glitch pulse signal line 201 data signal line 202 scanning signal line 203 data signal line driving circuit 204 scanning signal line Driving circuit 205 Scanning circuit 206 Sample / hold circuit 301 Scan control signal line 302 Logical operation circuit

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Jun Koyama 398 Hase, Atsugi-shi, Kanagawa Prefecture Semiconductor Energy Research Institute, Inc. (72) Inventor Hidehiko Chimura 398 Hase, Atsugi-shi, Kanagawa Semiconductor Energy Research Institute, Inc. (56) References JP-A-3-287291 (JP, A) JP-A-7-191636 (JP, A) JP-A-9-6278 (JP, A) JP-A-3-107994 (JP, A) (58) Survey Fields (Int.Cl. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133 505-580

Claims (8)

(57) [Claims] 1. A plurality of L scan control signal lines used for setting a scanning direction and an order, and a plurality of pulse signals respectively output by a logical operation of signals of all the L scan control signal lines. , Each of which is set by a pulse signal output from one of the different first logical operation circuits, and each of which is set to a different one of the different first logical operation circuits disposed after the first logical operation circuit. A plurality of flip-flop circuits reset by a pulse signal output from one logical operation circuit, N timing control signal lines for setting the timing of a scan signal to be finally output, and N timing control signal lines and the pulse signal, the full
Output from different ones in the flip-flop circuit
A plurality of second logical operation circuits each outputting a scan signal by a logical operation with a pulse signal to be performed . 2. Glitch prevention for sending L scan control signal lines used to set the direction and order of scanning, and sending a glitch prevention pulse for setting the direction and order of scanning and preventing glitches from occurring. and the pulse signal line, a logic operation between the signal and the glitch prevented pulses in the M scan control signal line of the L book SCS lines, a plurality of output pulse signals each of the first
A logical operation circuit, each of which is set by a pulse signal output from one of the first logical operation circuits different from each other, and each of which has one different first logical operation arranged at a stage subsequent to the first logical operation circuit. A plurality of flip-flop circuits reset by a pulse signal output from the circuit; N timing control signal lines for setting the timing of the finally output scanning signal; and K among the N timing control signal lines (K ≦ N) pulse signals of timing control signal lines and the flip signal
Scanning circuit and a plurality of second logic circuit which outputs a scanning signal by a logical operation between <br/> pulse signal output from a different one from each other in the flop. 3. The relationship of L = M × 2 is established between the total number L of the scan control signal lines and the number M of the scan control signal lines used by each of the first logical operation circuits, and , The L scan control signal lines are constituted by M sets of two scan control signal lines having phases opposite to each other, and each of the first logical operation circuits is configured by a respective one of the M sets of scan control signal lines. 3. The scanning circuit according to claim 2, wherein one of two scan control signal lines constituting each set is used. 4. The method according to claim 1, wherein M of the L scan control signal lines is M.
The combination of the M scan control signal lines in which the signals on the scan control signal lines and the signals on the remaining scan control signal lines have opposite phases and have the same phase are switched at a constant cycle. 3. The scanning circuit according to 2. 5. Glitch prevention for sending L scan control signal lines used for setting the direction and order of scanning, and sending a glitch prevention pulse for setting the direction and order of scanning and preventing glitches from occurring. A plurality of first pulse signals each of which outputs a pulse signal by a logical operation of a pulse signal line, a signal on M scan control signal lines out of the L scan control signal lines, and the glitch prevention pulse;
A logical operation circuit, each of which is set by a pulse signal output from one of the first logical operation circuits different from each other, and each of which has one different first logical operation arranged at a stage subsequent to the first logical operation circuit. A plurality of flip-flop circuits reset by a pulse signal output from the circuit; N timing control signal lines for setting the timing of the finally output scanning signal; and K among the N timing control signal lines (K ≦ N) and the pulse signal in the pulse signal or the glitch prevented pulse signal line of the timing control signal line, before Symbol flip
Output from different ones of the flip-flop circuit
Scanning circuit and a plurality of second logic circuit which outputs a scanning signal by a logical operation of a pulse signal that. 6. An L-scan control signal line used for setting a scanning direction and an order, and a glitch prevention for sending a glitch prevention pulse for setting a scanning direction and an order and preventing a glitch from occurring. A pulse signal line, a first logical operation circuit A that outputs a pulse signal by a logical operation of signals on the M scan control signal lines of the L scan control signal lines, and the L scan control signal lines A plurality of first logical operation circuits B each of which outputs a pulse signal by a logical operation of the signals on the M scan control signal lines and the glitch prevention pulse; B is set by the pulse signal output by B,
A plurality of flip-flop circuits reset by a pulse signal output from the first logical operation circuit B disposed at a stage subsequent to the first logical operation circuit B; and N flip-flop circuits for setting timing of a scan signal finally output , A pulse signal of K (K ≦ N) timing control signal lines of the N timing control signal lines, and a pulse signal output from the first logical operation circuit A different from each other. a plurality of second logic circuit C which outputs a scanning signal by logic operation, the output of K (K ≦ N) this timing control signal lines among the N number of timing control signal lines, the flip
A plurality of second logical operation circuits D each of which outputs a scan signal by a logical operation with a pulse signal output from one of different ones in the pump circuit. 7. Glitch prevention for sending L scan control signal lines used for setting the direction and order of scanning, and sending a glitch prevention pulse for setting the direction and order of scanning and preventing the generation of glitches. A pulse signal line, and a pulse signal selectively output from one of a pair of output terminals by a logical operation of a signal on the M scan control signal lines of the L scan control signal lines and the glitch prevention pulse. And a plurality of first logical operation circuits, each of which is set by a pulse signal output from one of the output terminals of one of the first logical operation circuits different from each other, and each of which is set by the first logical operation circuit Reset by a pulse signal output from one of the output terminals of one different first logical operation circuit arranged at a later stage than A plurality of flip-flop circuits, N timing control signal lines for setting timing of a scanning signal to be finally output, and K (K ≦ N) timings of the N timing control signal lines The pulse signal of the control signal line and the flip-flop
And a second logical operation circuit that outputs a scan signal by a logical operation with a pulse signal output from one of the different ones in the drop circuit . 8. A matrix-type image display device including a data signal line driving circuit and a scanning signal line driving circuit, wherein at least one of the data signal line driving circuit and the scanning signal line driving circuit is provided. A matrix-type image display device, comprising the scanning circuit according to any one of Items 1 to 7.