JP3283418B2 - Redundant output switching circuit and exchange - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant output switching circuit used in an exchange accommodating terminals in, for example, a 1: N communication mode , and such a redundant output switching circuit.
Pertaining to an exchange accommodating the .

[0002]

2. Description of the Related Art In general, a switching system is provided with a redundant output switching circuit so that even if a failure or the like occurs, the switching operation can be continued without interruption.

FIG. 2 shows an example of a conventional redundant output switching circuit. The redundant output switching circuit 1 shown in FIG. 2 includes a redundant configuration circuit 2 and a single configuration circuit 3.

Here, the duplex configuration circuit 2 has a double structure of an A-system circuit 2A and a B-system circuit 2B having the same circuit configuration, one of which always operates as an act system and the other operates as a standby system. I have. That is, when a failure or the like occurs, the circuit of the system that has been operating as the standby system until that time starts operating as the act system. However, the phases of signals output from the two systems often do not exactly coincide with each other due to differences in wiring length and the like, and there is usually a slight difference in phase.

In order to absorb this phase difference, a PLO (Phase Locked Oscillator) is provided in the single circuit 3 so that the operation clock converges to the phase of the input signal immediately after switching. ing.

The detailed configuration and operation of the redundant output switching circuit 1 are as shown in FIGS. 3 and 4. FIG. 3 is a block diagram showing a detailed circuit configuration of the redundant output switching circuit 1, and FIG. 4 is a timing chart showing the operation timing.

That is, the redundant output switching circuit 1 comprises N terminals (telephone terminals in this case) 51, 5
A signal having a destination of 2 to 5N is supplied to A through the switch 4.
It is input to each of the system circuits 2A and 2B. The contents of the signals input to each system are the same.

From the A-system circuit 2A and the B-system circuit 2B, such signals are transmitted as serial data DATAA (FIG. 4 (B)) and DATAB (FIG. 4 (E)) to the A-system reception circuit 3A and the B-system reception circuit 3B. Entered for each.

A system receiving circuit 3A1 and B system receiving circuit 3B
1 is the input serial data DATAA and DAT
AB is the frame synchronization signal SYNCA (FIG. 4A), S
Processing is performed based on the YNCB (FIG. 4D) and the clock signals CLKA (FIG. 4C) and CLKB (FIG. 4F), and the serial / parallel conversion circuits 3A2 and 3B2 convert the data into parallel data. The processing up to this stage is parallel processing, and the data rate is reduced by this serial / parallel conversion operation.

Note that these two parallel data DATs
AA (FIG. 4 (G)) and DATAB (FIG. 4 (H))
As a result of the selection by the selector 3C, only one of them is output to the subsequent data output circuit 3E. Here, switching of the selector 3C is performed by a switching signal given from the system selection circuit 3D. Incidentally, this switching signal is transmitted from each of the A-system circuit 2A and the B-system circuit 2B to the state signal ACT.
A (FIG. 4 (J)) and ACTB (FIG. 4 (K)) are input, and a system selection circuit 3 for specifying a system operating as an act system
Given from D.

The switching signal is also supplied to a selector 3D1 for selecting the clock signals CLKA and CLKB input to the PLO 3D2, and the phase of the clock signal CLKC output from the PLO 3D2 is synchronized with the phase of the act system clock signal. It has been made like that.

With this configuration, even if a failure or the like occurs in the act-related circuit, the processing target is immediately switched to the output from the standby-related circuit, and data is transmitted from the data output circuit 3E to the N terminals 51 to 5N. It can be transferred without interruption.

[0013]

However, commercially available PLOs cannot always satisfy all the conditions of the redundant output switching circuit 1 in terms of the operation CLK and the following speed, and the circuit design is not satisfactory. There was a possibility that it would be a constraint.

In order to save power, the power supply voltage is expected to further decrease (for example, 3.3 [V]).
There are still few types of PLO products corresponding to such a power supply voltage.

Therefore, it is possible that there is no PLO that satisfies the desired conditions. In such a case, it is necessary to newly develop a PLO prior to commercializing the redundant output switching circuit 1. However, such a situation is not preferable today, in which a reduction in the development period is desired.

In the conventional configuration circuit, PLO3
Even if the circuit parts other than D2 can be integrated, the PLO3D2 must be externally mounted on the LSI, so that the circuit scale and the mounting space cannot be avoided.

The present invention has been made in view of the above points, and it is an object of the present invention to propose a redundant output switching circuit having higher expandability and a smaller circuit size than conventional ones. Another object is to propose an exchange using such a redundant output switching circuit.

[0018]

According to the present invention, in order to solve the above-mentioned problem, when a failure occurs, a circuit system which has been operating as an active device until immediately before is replaced with a circuit system which has been operated as a standby device until immediately before. In a redundant output switching circuit that switches processing targets to continue processing operations without an instantaneous interruption, the following is characterized.

[0019] That is, when the circuit system of the circuit system and the protection device of the active device that switched even until processing of the current frame Ru Ah in process at the time the switch occurs is completed, just before switching Using a clock signal input from a circuit system operating as an active device as an internal clock to continue processing data input from the circuit system,
When the input of the next frame is started from the circuit system which newly operates as the active device after the processing of the data, the internal clock is switched to the clock signal input from the circuit system operating as the active device. Along with
The data to be processed, characterized in that a timing signal generating means for switching the data input from the circuit system.

As described above, since the clock signal paired with the data to be processed is used as it is as the internal clock, the processing can be continued without having a follow-up period of the internal clock for switching the circuit system.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the exchange according to the present invention will be described below with reference to the drawings.

(1) Configuration of Exchange (1-1) Overall Configuration FIG. 1 is a block diagram showing a functional configuration of the exchange of the embodiment. The exchange 11 is actually composed of various interfaces and switches, and other control devices and maintenance devices, and the like. FIG. 1 shows a block diagram of a circuit portion provided with a redundant output switching circuit. It becomes street.

The exchange 11 is characterized in that data sequentially input from the act-related circuit is written into a memory as an internal clock with the clock signal input from the act-related circuit together with the data. The point is that a redundant output switching circuit 12 having a function of preparing two memories for writing input data and replacing the memory for writing data in frame units is used.

Note that, even if a failure or the like occurs, the redundant system output switching circuit 12 converts the data of the frame at the time of the failure from the data and clock signal of the circuit that had been operating as the act circuit until then. The PLO is eliminated by a method of receiving the supply, continuing writing to the memory, and continuing the processing by receiving the supply of data and a clock signal from the circuit switched from the standby circuit to the act circuit from the next frame.

Hereinafter, the configuration of each part of the exchange 11 will be described in order.

(1-2) Configuration of Each Unit The switch 4 is provided in each of the telephone terminals 51 to 51 accommodated in the exchange 11.
This is a circuit for time division multiplexing communication data destined for 5N. By the way, this switch 4 is usually composed of two systems SW1 and SW2, and when one switch (for example, SW1) is in a standby state, the other switch (SW2) operates in an active state, and the switch (SW2) operates from the switch (SW2). The multiplexed data is split into two systems. The data branched in this manner is supplied to the redundant configuration circuit 13 of the redundant output switching circuit 12.

The duplex configuration circuit 13 has the same circuit configuration as A
This is a circuit composed of a system circuit 13A and a system B circuit 13B. When one of the A-system circuit 13A and the B-system circuit 13B operates as an act-related circuit, the other operates as its standby-related circuit, and even if a failure occurs in the act-related circuit, the standby-related circuit is immediately switched to perform communication. Can be continued.

The A-system circuit 13A and the B-system circuit 13B
Indicates that even if a failure or the like occurs while outputting the data DATAA and DATAB having the frame structure shown in FIGS. 5B and 5E, the data of the frame currently being output at the time when the failure occurs Has a structure that can continue outputting data to the end.

In addition, the A-system circuit 13A and the B-system circuit 13
B is the frame synchronization signal S shown in FIGS. 5A and 5D.
YNCA and SYNCB, clock signals CLKA and CLKB shown in FIGS. 5C and 5F, and status signals ACTA and ACTB shown in FIGS. 5G and 5H.

Next, the internal configuration of the simplex configuration circuit 14 will be described. The single-layer configuration circuit 14 uses either the clock signal CLKA or CLKB supplied from the act-related circuit as the operation clock supplied to the internal circuit.

The circuit provided for this purpose is the selector 14A. The selector 14A is provided with an A-system clock CL.
This circuit inputs KA and B-system clocks CLKB to input terminals, and alternatively selects an ACT-system clock signal specified by a system selection signal ACTD.

As a similar circuit, there is another selector 14B. However, in the case of the selector 14B, the output data DATAA of the A-system circuit 13A and the output data DATAB of the B-system circuit 13B are to be switched, and the data of the system specified by the system selection signal ACTD is selected. It has become.

Next, a circuit for generating the system selection signal ACTD will be described. Such circuits include a system selection circuit 14C, a selector 14D, and a D-flip-flop (D-flip-flop).
FF) circuit 14E.

The system selection circuit 14C includes the A system circuit 1
Status signals ACTA and AC from the 3A and B system circuits 13B
This is a circuit for inputting a TB to determine the current act-related circuit. The system switching signal ACT has a signal level corresponding to the determination result.
C is output.

For example, when the A-system circuit 13A is an act system, the system selection circuit 14C outputs an "H" level system switching signal ACTC, and when the B-system circuit 13B is an act system, it outputs an "L" level. And outputs the system switching signal ACTC. Note that the level change in the system switching signal ACTC is caused by the occurrence of a failure or the like.
Appears as soon as changes appear in CTA and ACTB.

The selector 14D receives the system switching signal ACT
C, the frame synchronization signals SYNCA and SYN
This circuit selects which frame synchronization signal of the CB is used in the subsequent processing, and outputs a selection result as a frame synchronization signal SYNCC. With this selector 14D, the head of the frame immediately after the act system has been switched can be found.

The D-FF circuit 14E is a flip-flop circuit that operates with the frame synchronization signal SYNCC output from the selector 14D as a trigger. Even if a level change occurs in the system switching signal ACTC input to the data input terminal, the D-FF circuit 14E performs the following operation. Until the frame starts, the system selection signal AC
This is a circuit that keeps the value captured at the time of the previous trigger input so that the state of TD does not change.

The presence of the D-FF circuit 14E makes it possible to switch the clock signal CLKC and data DATAC selected by the selectors 14A and 14B on a frame basis. Therefore, when the switching of the act system occurs, the phases of the data DATAC and the clock signal CLKC can be instantaneously switched from the beginning of the next frame.

Subsequently, the data DATAC and the clock signal CLK selected by the selectors 14A and 14B
The circuit for processing C will be described. These circuits include a counter 14F, a serial / parallel conversion circuit 14G, a memory selector 14H, first and second RAs.
M (hereinafter referred to as RAM1 and RAM2) and the data output circuit 14I.

Among them, the counter 14F operates based on the clock signal CLKC to output the internal clock signal CLKD and R
AM1 and an address signal ADDRS for the RAM2. For example, the counter 14F divides the frequency of the clock signal CLKC according to the bus width of the RAM, and generates the internal clock signal CLKD.

The counter 14F resets the count value based on the input timing of the frame synchronization signal SYNCC, and outputs the reset count value to the RAM1 and the RAM2 as a write address and a read address.

The serial / parallel conversion circuit 14G is a circuit that performs serial / parallel conversion of the data DATAC so as to match the bus width of the RAM1 or RAM2 operating based on the read address and the write address, and is provided from the counter 14F. It operates based on the clock CLKC.

The memory selector 14H outputs the parallel data DAT converted by the serial / parallel conversion circuit 14G.
This is a circuit for selecting a memory in which an AP is to be written. Each time the frame synchronization signal SYNCC is input to the memory selector 14H, a selection signal CS instructing a switch of a memory into which parallel data is written is output to the RAM1 and the RAM2.

The parallel data DATA is stored in the RAM 1.
When P is written, data already written in the previous frame period is read from one RAM 2, and conversely, when parallel data DATAP is written in RAM 2, data is already written from one RAM 1 in the previous frame period. The read data is read. FIG. 5J shows this state.

The data output circuit 14I converts the data read from either the RAM1 or the RAM2 based on the internal clock signal CLKD, and
N to N as output data DATAO.

(2) Example of Operation When Failure Occurs In the above configuration, the state of the switching operation when a failure occurs by the redundant output switching circuit will be described. Here, as a precondition, it is assumed that data D1 to DN having destinations of N telephone terminals 51 to 5N are time-division multiplexed within one frame period. It is assumed that a blanking period BLK is provided. Incidentally, in this example, the length of the blanking period BLK is the same as the length obtained by equally dividing one frame period into N + 1.

Under these preconditions, it is assumed that the A-system circuit 13A continuously operates as an act-system circuit and the B-system circuit 13B operates as an SBY-system circuit until the start of the first frame.

At this time, the operation up to the start of the first frame is as follows.

The system selecting circuit 14C determines from the status signals ACTA and ACTB that the A-system circuit 13A is the act system, and selects the system-switching signal ACTC for selecting the A-system circuit 13A.
Is output.

Thus, each of the selectors 14A, 14B,
14D , the data D of the A-system circuit 13A
ATAA, the clock signal CLKA and the frame synchronization signal SYNCA are selected, and the data DATAA is
The TAC is supplied to the serial / parallel conversion circuit 14G, the clock signal CLKA is supplied to the counter 14F as the clock signal CLKC, and the frame synchronization signal SYNCA is supplied to the D-FF circuit 14E, the counter 14F, and the memory selector 14H as the frame synchronization signal SYNCC.

Therefore, the serial / parallel conversion circuit 14
The G and data output circuit 14I operates by the clock signal CLKA of the A-system circuit 13A provided via the counter 14F.

Each time the counter 14F is reset by the frame synchronization signal SYNCC, it should count up the count value based on the clock signal CLKC and write the data D1 to DN converted by the serial / parallel conversion circuit 14G. Generate an address.

The memories to which the data D1 to DN are to be written are alternately switched by a selection signal CS input from the memory selector 14H at each head of the frame. Then, the reading of the data written in the previous frame from the memory in which the data has been written is started, and the data is transferred to each of the telephone terminals 51 to 5N via the data output circuit 14I.

[0054] In this state, if a failure in the middle of the first frame is generated, as shown in FIG. 5 (G) and (H), from the A-system circuit 13A and B-system circuit 13B, respectively it
Status signals ACTA and ACTB interchanged and A transfected system circuit and a standby system circuit is outputted. This gives 1
The state of the frame switching signal ACTC is inverted in the middle of one frame.

FIGS. 6 and 7 show this. FIG. 6 shows the A-system circuit 1 due to the influence of the state of the transmission path and the like.
FIG. 7 is a timing chart when the phase of data DATAA or the like output from 3A is advanced compared to the phase of data DATAB or the like output from the B-system circuit 13B.
Is the data DA output from the B-system circuit 13B.
The data D output from the A-system circuit 13A by TAB or the like
This is a case where it is advanced compared to ATAA or the like.

In any case, the state changes so that the system switching signal ACTC switches the frame synchronization signal SYNCA to SYNCB (FIGS. 6E and 7).
(E)), the output of the selector 14D switches from the frame synchronization signal SYNCA of the A-system circuit 13A to the frame synchronization signal SYNCB of the B-system circuit 13B.

However, since the two frame synchronization signals are in the "H" state except for the start position of the frame (that is, a period other than the start of the frame is represented), as shown in FIGS. 6 (F) and 7 (F). In addition, from the frame synchronization signal SYNCC, it is apparent that system switching cannot be identified. Note that the state change of the system switching signal ACTC is based on the frame synchronization signal SYN.
CA and SYNCB are prohibited in the upper circuit side so as not to occur during the period of the "L" state.

Therefore, during the first frame, rewriting of the latch data by the D-FF circuit 14E is not performed, and
-The system specified by the system selection signal ACTD output from the FF circuit 14E remains the A-system circuit 13A. For this reason,
During a period from the occurrence of the change of the system switching signal ACTC to the end of the first frame, the data DATAA output from the A-system circuit 13A is written to either the RAM1 or the RAM2 based on the clock signal CLKA. Become.

When the transfer of the second frame is started after the end of the first frame, the latch data of the D-FF circuit 14E is rewritten by the frame synchronization signal SYNCB at the head of the first frame, and the selectors 14A and 14B are rewritten. The data and clock signal to be selected are switched.

Thus, at the start of the second frame,
The data DATAB and the clock signal CLKB synchronized with the frame synchronization signal SYNCB of the B-system circuit 13B are supplied to the serial / parallel conversion circuit 14G and the counter 14F, and the data to be processed and the operation timing are switched.

Since this switching is performed based on the operation timing of the B-system circuit 13B, there is a possibility that the data of the A-system circuit 13A may be destroyed at the time of the switching. Since a tail is provided with a blanking period irrelevant to the original data transfer, FIG.
As shown in FIG. 7H, the operation can be continued by absorbing the phase difference between the two systems only by increasing or decreasing the blanking period. That is, system switching cannot be determined from the telephone terminals 51 to 5N.

Then, after the third frame, the B-system circuit 1
The operation synchronized with the clock signal SYNCB output from 3B is continued. Thus, an uninterrupted operation is guaranteed.

[0063] Thus, failure or the like is two even by using the data and clock signals until having been output from the circuit that is operating as the acting circuit until it next frame period is started for generating The writing and reading operations to the memories (that is, RAM1 and RAM2) are continued, and from the next frame period, the data writing operation to the two memories is performed using the clock data and the data on the circuit side switched from the standby system to the act system. By continuing the read operation and the read operation, it is possible to realize a redundant output switching circuit that operates without using a PLO and an exchange incorporating the same.

In addition, the redundant output switching circuit 12
Since the clock signal used for the internal operation is used as it is by switching the clock signal input from the two systems, it is not necessary to consider the follow-up period at the time of system switching as compared with the case where the PLO is used as in the past, and the data It can easily cope with a case where the transfer rate is increased.

As shown in FIG. 8, the redundant output switching circuit starts with memories (RAM1 and RAM2).
The circuits such as the selectors 14A, 14B, 14D
Since it can be manufactured in I, the circuit scale and the mounting area can be further reduced as compared with the related art.

(2) Other Usage Modes In the redundant output switching circuit in the above-described embodiment, the case where two memories are used for writing and reading data has been described. However, the same applies when only one memory is used. , A redundant output switching circuit that operates in the same manner can be realized. In this case, data may be transmitted every other frame as shown in FIG. 9, instead of transmitting data using all frames. Incidentally, the circuit configuration only needs to remove one memory from FIG.

Further, a redundant output switching circuit that operates in the same manner can be realized without using any memory. An example is shown in FIG. However, in FIG. 10, parts corresponding to those in FIG. 1 are denoted by the same reference numerals. The difference between FIG. 10 and FIG. 1 is that the frame synchronization signal SYN
CC is used as a reset signal of the data output circuit 14I. It should be noted that the data transfer rate and the speed of the clock signals CLKA and CLKB in this example are set to be twice those in the case where one memory is used. Thus, data for one frame can be transmitted only in the first half of one frame period.

FIG. 11 shows an operation example of the redundant output switching circuit 11 '. In this example, a failure occurs in the middle of the second frame, and the system is switched between the act system and the standby system. In this case, too, the frame synchronization signal SY indicating the start of the third frame in the B system circuit 13B.
Until NCB is input, the data D of the A-system circuit 13A
ATAA continues to be transmitted to data output circuit 14I. Accordingly, in the case of this example, the transmission of the head data [8] of the third frame has been started.

However, as shown in FIG. 11 (L), immediately after that, the frame synchronization signal SY indicating the start of the third frame
Since the NCB is input to the data output circuit 14I as a reset signal, the data [8] of the A-system circuit 13A becomes invalid, and the data [8 '], [9'], [1] of the B-system circuit 13B.
0 '] becomes valid. Hereinafter, the same operation is repeated. If the processing of the data [8 '], [9'], and [10 '] is completed by the next frame as shown in FIG. 11M, the redundant output switching circuit operates without any problem. I do.

Further, in the above-described embodiment, a telephone terminal has been described as an example of a terminal, but the present invention is not limited to this.
It can also be applied to data terminals such as computers. That is, the switching system is an ISDN which is an integrated service digital network, whether it is a telephone network switching system, a digital data circuit switching network switching system, a digital data packet switching network switching system.
(Integrated Services Digital Network) exchanges. Also, the present invention can be applied to a case where a dedicated line is connected.

Further, in the above-described embodiment, as the blanking period provided at the end position of one frame period, the same time as the time required for transmitting data to one terminal is used. The length may be longer or shorter. If this period is long,
Although the data transfer rate decreases, the phase difference between the act system and the standby system that can be absorbed can be widened accordingly.

In the above-described embodiment, the redundant output switching circuit of the duplex system has been described. However, the present invention can be applied to a redundant output switching circuit of the n + 1 system.

Furthermore, in the above embodiment, the case where the redundant system output switching circuit is used in the exchange has been described. However, any circuit or system having a redundant system can be applied.

[0074]

As described above, according to the present invention, even if a failure occurs and the circuit system of the active device and the spare device is switched, the device operates as the active device until immediately before the processing of the current frame is completed. that the clock signal circuit system continues to process data using as the internal clock, when the input is to be the start of the next frame from the switching circuit based on the newly active apparatus, a clock signal used as an internal clock Is switched to a clock signal of a circuit system newly operating as an active device to perform data processing, whereby a redundant system output switching circuit can be configured without using a PLO. As a result, the number of circuits and the mounting space can be reduced as compared with the conventional circuit. Further, by using such a redundant output switching circuit, the exchange can be further reduced in size.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an entire configuration of an exchange according to an embodiment (excluding a processor, a control unit, and the like).

FIG. 2 is a block diagram showing a schematic configuration of a conventionally used redundant output switching circuit.

FIG. 3 is a block diagram showing an entire configuration of a conventionally used switching system (excluding a processor, a control unit, and the like).

FIG. 4 is a timing chart for explaining a switching operation of a conventionally used redundant output switching circuit.

FIG. 5 is a timing chart for explaining a switching operation of the redundant output switching circuit according to the embodiment;

FIG. 6 is a timing chart showing switching timing when the operation phase of the A-system circuit is advanced compared to the operation phase of the B-system circuit.

FIG. 7 is a timing chart showing switching timing when the operation phase of the B-system circuit is advanced compared to the operation phase of the A-system circuit.

FIG. 8 is a block diagram illustrating a schematic configuration of an exchange according to the embodiment.

FIG. 9 is a timing chart showing a transmission method used in a redundant output switching circuit of a system using only one memory according to another usage mode.

FIG. 10 is a block diagram showing a redundant output switching circuit of a system without using a memory according to another usage mode.

FIG. 11 is a timing chart showing a transmission method of a redundant output switching circuit using no memory.

[Explanation of symbols]

1, 12 redundant output switching circuit, 2, 13 redundant configuration circuit, 2A, 13A A system circuit, 2B, 13B
.. .B system circuit, 3, 14...
.. System receiving circuit, 3B... B system receiving circuit, 3A2, 3B2.
... Serial / parallel conversion circuit, 3C, 3D1, 14
A, 14B, 14D ... selector, 3D ... system selection circuit, 3D2 ... PLO, 3E ... data output circuit, 4 ...
... Switches, 51, 52 to 5N terminals, 11 exchanges, 14C system selection circuits, 14E D-flip-flop (D-FF) circuits, 14F counters, 14G
... Serial / parallel conversion circuit, 14H ... Memory selector, 14I ... Data output circuit, RAM1, RAM
2. Memory.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04M 3/22 H04Q 11/04

Claims (3)

(57) [Claims] 1. A redundant system output switch that switches a processing target from a circuit system that has been operating as the active device until immediately before to a circuit system that has been synchronously operated as the standby device until immediately before, so that the processing operation can be continued without an instantaneous interruption. In the circuit, the circuit system of the active device and the circuit system of the standby device are switched.
In case that, Oh in process at the time the switch occurs
That until the processing of the current frame is finished, and continues the process of data input from the circuit system using a clock signal inputted from the circuit system has been operating as a working unit immediately before switching as the internal clock, the When the input of the next frame is started from the circuit system newly operating as the active device after the data processing, the internal clock is switched to the clock signal input from the circuit system operating as the active device, and the data to be processed includes a timing signal generating means for switching the data input from the circuit system, the end of the frame, the transmission of significant data, respectively
A redundant output switching circuit, wherein a blank period not used is provided . 2. A circuit which has been operating as a working device until immediately before.
The circuit that was running synchronously as a backup device until just before
By switching the processing target to the road system, the processing operation
In the redundant output switching circuit that continues without interruption, the circuit system of the working device and the circuit system of the standby device are switched.
Is being processed at the time when the switching occurs.
Until processing of the current frame is completed,
Input from the circuit system that was operating as the
Using the lock signal as an internal clock,
Continue processing the input data, and finish processing the data.
Circuit system that will be newly operated as a working device after
When the input of the next frame starts from
Input from the circuit system operating as the active device
Switch to the clock signal and set the data to be processed.
To switch data to the data input from the circuit system.
Comprising a a timing signal generating means, said timing signal generating means, one of said two circuit system operates in either normal as a current device
Detection means for detecting the time and the detection result of the detection means,
Of the frame synchronization signal input from the
A first selector for selecting and outputting a frame synchronization signal; and a first selector for selecting and outputting a frame synchronization signal input from the first selection unit.
Until the head of the next frame is detected.
Latch means for holding a detection result of a stage; and a clock signal input from the two circuit systems.
Input from a circuit system specified by the output of the latch means
Selector for selecting and outputting a clock signal to be output
When, among the data inputted from the two circuit systems, the La
Output from the circuit system specified by the output of the switch means
This and a third selector for selecting and outputting data
And a redundant output switching circuit. 3. An interface connected to a wide area network or a dedicated line, a switch for exchanging data input / output through the interface, and two switches operating by inputting the same data from the switch. It has a circuit system, a circuit system which has been operating as a working unit immediately before, even in the case that switching to the circuit system which has been synchronized operation as a reserve unit until just before, Oh in process at the time the switch occurs that until the processing of the current frame is finished, and continues the process of data input from the circuit system using a clock signal inputted from the circuit system has been operating as a working unit immediately before switching as the internal clock, the After the data processing is completed, when the input of the next frame is started from the circuit system newly operating as the active device, the internal clock is changed to the current clock. With switching on the clock signal input from the circuit system that operates as a device, exchange of data to be processed, characterized in that a timing signal generating means for switching the data input from the circuit system.