JP3284978B2 - Method for manufacturing capacitor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a capacitor .
Manufacturing method for capacitors used in semiconductor devices .
Construction method .

[0002]

2. Description of the Related Art In a capacitor according to the present invention, realizing a high capacitance value with a low leakage current is one of the important factors.

In order to achieve this object, Ta2O5, SrTiO3, (Ba, Sr) T
A structure in which a high dielectric constant film such as iO3 is used for a capacitor has been studied.

FIG. 15 is a sectional view of an example of a conventional capacitor structure. The conventional capacitor is a columnar-structured capacitive film 10 including a substrate 100, a lower electrode 101 laminated on the substrate 100, and a grain 103 and a grain boundary 104 laminated on the lower electrode 101.
2 and an upper electrode 1 laminated on the capacitor film 102.
05.

[0005] Here, the grains 103 refer to clusters of individual crystals constituting a capacitance film. The capacitance film has a polycrystalline structure. The polycrystalline structure means that a large number of crystals of a small capacitance film are gathered to form one film.

For example, as shown in FIG. 15, the capacitance film has a structure in which crystals (ie, grains 103) like columns are bundled.

On the other hand, the grain boundary 104 is a boundary between the grains 103.

[0008] Grain 103, grain boundary 10
4 are names indicating structures in the crystal.

[0009]

However, this method has a problem in that a large leak current easily flows through the grain boundary 104 because a capacitor film having a polycrystalline columnar structure is used.

[0010] As a method of improving the leak current, for example, Japanese Journal of Applied Physics (Japanese Journal of Applied Physics) is used.
Applied physics) 35 (1996)
On page 4880, a technique for improving the surface flatness of a capacitor film using multi-step film formation is described.
Pp. 2530 describes a technique for optimizing the partial pressure of oxygen gas during film formation. The magazine, Vol. 33 (1994) 5129.
Although the page describes a technique for optimizing the (Ba + Sr) / Ti ratio of (Ba, Sr) TiO3, these prior arts cannot essentially avoid the grain boundary problem which is a leakage current path.

For this reason, Japanese Patent Application No. 9-17 / 1997 proposes to fill the grain boundary with an amorphous material having a small leak current.
No. 949 (unpublished at the time of filing the present invention), but it is not sufficient to take measures against the grain boundary, for example, there is a concern that leakage current may increase when the grain boundary is crystallized by heat treatment or the like. .

Further, a technique of epitaxially growing a capacitance film on strontium oxide ruthenium (SrRuO3) and essentially eliminating the grain boundary has been applied to the Applied Physics Letter (Applied ph.
ysics Letter) 70 (11) vol. (1997)
Year) page 17.

However, this epitaxial growth has a problem that the lower electrode structure is complicated and productivity is poor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a capacitor structure capable of avoiding a leak current path relating to grain boundary with a relatively simple configuration, and a method of manufacturing the same.

[0015]

[0016]

Means for Solving the Problems] To solve the above problems
The method for manufacturing a capacitor according to the present invention, the lower electrode,
A method of manufacturing a capacitor comprising: a capacitor film having a columnar structure formed of grains and a grain boundary stacked on an upper portion of the lower electrode; and an upper electrode stacked on the capacitor film. A first step of forming an electrode, a second step of stacking the capacitor film on the lower electrode after the first step, and the grain boundary forming the capacitor film after the second step A third step of etching an upper portion of the capacitor film, a fourth step of depositing an upper electrode on the upper portion of the capacitor film using a processing method having poor coverage, and a subsequent step of depositing the upper electrode on the upper portion of the capacitor film. And a fifth step of etching the electrode.

Furthermore, instead of the fourth and fifth step,
Following the third step, a sixth step of depositing an upper electrode on the capacitor film using a processing method with good coverage, a seventh step of heat-treating the upper electrode after the sixth step, An eighth step of processing the upper electrode is provided after the seventh step.

According to the present invention , a structure is obtained in which the upper electrode stacked on the capacitor film does not directly make electrical contact with the grain boundary, so that the leakage current path relating to the grain boundary can be reduced with a relatively simple configuration. It is possible to avoid.

Incidentally, JP-A-5-343254, JP-A-8-17939, and JP-A-8-319.
No. 51 discloses a technique for reducing leakage current, but none of the publications discloses a capacitor having a columnar-structured capacitance film composed of grains and grain boundaries as in the present invention.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A feature of the present invention is to realize a capacitor structure characterized in that a grain boundary existing between grains constituting a capacitance film and an upper electrode are not in direct contact with each other.
The manufacturing method includes an etching method, an upper electrode deposition method, and an annealing method after forming the upper electrode.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. First, the first embodiment will be described. The first embodiment relates to a capacitor structure.

FIG. 1 shows a first example of a capacitor structure according to the present invention.
It is sectional drawing which shows embodiment. The conventional example (FIG. 1)
The same components as in 5) are denoted by the same reference numerals, and description thereof will be omitted.

Referring to FIG. 1, a capacitor is connected to a substrate 100.
And a lower electrode 101 laminated on the substrate 100
And a capacitor film 3 having a columnar structure, which is laminated on the lower electrode 101 and includes a grain 1 and a grain boundary 2.
And an upper electrode 4 stacked on the capacitor film 3.

The grain boundary 2 ′ on the upper surface of the capacitance film 3 is etched, so that the upper electrode 4 formed on the capacitance film 3 does not directly contact the grain boundary 2.

Next, a second embodiment will be described. The second embodiment relates to a first method for manufacturing a capacitor. 2 to 4 are cross-sectional views illustrating respective manufacturing steps of the capacitor according to the second embodiment, and FIG. 13 is a flowchart illustrating the respective manufacturing steps. 2 to 4, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

First, the lower electrode 101 is formed on the substrate 100 (S1 in FIG. 13), and then the columnar capacitor film 3 composed of the grains 1 and the grain boundary 2 is formed on the lower electrode 101. (Fig of S2), then gray capacitive film 3 top by wet etching and dry etching
Selectively etch only in- bandry 2 ' (S
3).

Next, the upper electrode 4 is formed by a film formation method having poor coverage (S4), and a region where the grain boundary 2 does not contact the upper electrode 4 is formed. Then, finally, the upper electrode 4 is processed (S5).

The features of this manufacturing method are that only the grain boundary 2 is etched by etching and that the method of forming the upper electrode 4 having poor coverage is used in combination.

Next, a third embodiment will be described. The third embodiment relates to a second method for manufacturing a capacitor. 6 to 8 are cross-sectional views illustrating respective manufacturing steps of the capacitor according to the third embodiment. FIG.
8 to FIG. 8, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. The flowchart is shown in FIG.
Use 3.

In the third embodiment, a method of etching both the grain 1 and the grain boundary 2 is used (S3 in FIG. 13). The etching conditions at this time are such that the etching rate of the grain 1 is lower than the etching rate of the grain boundary 2.

Using the difference between the two etching rates,
Apparently, the shape is such that the grain boundary 2 'on the surface of the capacitance film 3 does not exist. Further, the upper electrode 4 is formed by a film formation method having poor coverage (S4 in the same figure).

Next, a fourth embodiment will be described. The fourth embodiment relates to a third method for manufacturing a capacitor. 9 to 12 are cross-sectional views illustrating respective manufacturing steps of the capacitor according to the fourth embodiment, and FIG. 14 is a flowchart illustrating the respective manufacturing steps. 9 to 1
2, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In the fourth embodiment, the second or third
After processing the capacitance film 3 by the etching method of the embodiment (S3 in FIG. 14), the upper electrode 4 is formed.

At this time, the method of forming the upper electrode 4 is not limited to a method having poor coverage. After forming the upper electrode 4 (S
14) Then, heat treatment of the capacitor is performed (S15 in the same figure), and the upper electrode 4 is recrystallized.

As a result of the volume condensation accompanying the recrystallization, the material of the upper electrode 4 buried in the grain boundary 2 does not come into electrical contact with the grain boundary 2, and the structure of the present invention can be realized.

The main leak current path in the capacitance film 3 is the grain boundary 2. Thus, by using the present invention, electrical contact between the leakage current path and the upper electrode 4 can be avoided, and a capacitor having a low leakage current can be provided.

Next, examples of the second to fourth embodiments will be described.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment will be described. The first example is a first example of the second embodiment. The first embodiment will be described with reference to FIGS.

First, a ruthenium (Ru) lower electrode 101 is formed on the substrate 100 by sputtering (S1 in FIG. 13). Next, an electron cyclotron resonance (Electron) is provided above the lower electrode 101.
Strontium titanate (SrTiO3 (hereinafter referred to as ST)) by a Cyclotron Resonance (hereinafter referred to as ECR) chemical vapor deposition (CVD) method.
Is formed (see FIG. 2 and FIG. 2).

The ST film forming conditions at this time are as follows.
The film forming temperature was 500 ° C., the film forming chamber pressure was 7 mTorr, the plasma power was 750 W, and Sr (DPM) was used as a raw material.
2 (Die Balloy Metanate Strontum (DP
M), the official name is bis-dipivaloymeth
anate), titanium isoprooxide (hereinafter referred to as Ti (O
-I-Pr) 4), and argon Ar
Is transported to a film formation chamber as a carrier gas, and mixed with oxygen gas in the film formation chamber to form a film.

As shown in FIG. 2, S formed under these conditions
T3 has a columnar structure composed of the grain 1 and the grain boundary 2 existing between the grain 1 and the grain 1.

After the ST film 3 is formed, the substrate 100 with the ST film 3 is immersed in an etching solution composed of hydrofluoric acid (HF) and pure water to selectively etch the grain boundary 2 (see S3 in FIG. 13 and FIG. 3). ).

At this time, the mixing ratio of the etching solution was hydrofluoric acid:
Using pure water = 1: 10000, and setting the temperature of the etching solution to 2
5 ° C. and an etching time of 10 seconds were used. Under this etching condition, the grain boundary 2 ′ on the upper surface of the capacitor film was etched by 2 nm.

After the etching, the substrate was immersed in a water bath in which pure water was circulated for 10 minutes so that the etching did not proceed, so that the etching of the grain boundary 2 'on the surface of the capacitance film 3 did not proceed.

After the etching, the substrate 100 with the capacitive film 3 was dried, and gold (hereinafter, Au) as the upper electrode 4 was deposited to a thickness of 100 nm by sputtering (see S4 in FIG. 13 and FIG. 4).

The deposition conditions at this time are as follows. Au as target, Ar as sputter gas, plasma power 2 kW, DC applied voltage 500 V, film forming chamber pressure 3 mT
orr, substrate heating is 100 ° C.

Since the sputtering method has poor coverage, the etched grain boundary portion 2 on the surface of the capacitance film 3 is formed.
′ Cannot be covered and the grain boundary 2 and the Au upper electrode 4 do not come into contact with each other (see FIG. 4).

Further, the Au upper electrode 4 is etched to an appropriate size to form the upper electrode 4 (see S5 in FIG. 13 and FIG. 4).

FIG. 5 shows a comparison between the capacitor formed using this embodiment and the conventional capacitor obtained by forming the Au upper electrode 105 after forming the capacitance film 102 as shown in FIG. It was done.

Referring to FIG. 5, the leak current is reduced by using the present invention, and a leak current of 10 to 8 A / cm ² or less can be obtained with an applied voltage of 1 V.

This leak current is a level of the leak current which sufficiently satisfies the specifications for application of the device.

Next, a second embodiment will be described. Second
The example is a second example of the second embodiment. Second
FIGS. 2 to 4 and 13 are also used to describe the embodiment.

The processes up to the formation of the capacitance film 3 (S2 in FIG. 13) are the same as those in the first embodiment.

After the ST film 3 is formed, ECR is performed using HF gas.
The gas pressure is set to 2 mTorr by the plasma etching method.
The substrate was etched at room temperature for 30 seconds (S in FIG. 13).
3).

At this time, only the grain boundary 2 is etched, and the grain boundary 2 ′ on the surface of the capacitor film 3 is etched.

Steps S4 and S5 are the same as in the first embodiment.

In this step, HF gas is used. However, if a gas capable of selectively etching only the grain boundary 2 is used, a similar effect can be obtained.

Next, a third embodiment will be described. Third
The example is an example of the third embodiment. The third embodiment will be described with reference to FIGS.

The processes up to the formation of the capacitance film 3 (S2 in FIG. 13) are the same as in the first and second embodiments.

After forming the ST film 3, oxygen (O2), chlorine (C
I2) and the grain 1 and the grain boundary 2 are etched by an ECR plasma etching method using a mixed gas of SF6 (sulfur hexafluoride) (S in FIG. 13).
3).

At this time, since the etching speed of the grain boundary 2 is higher than that of the grain 1, a portion 2 'where the grain boundary 2 does not exist is formed on the surface of the capacitor film 3 (see FIG. 7).

The following steps S4 and S5 correspond to the first and second steps.
This is the same as the embodiment.

Next, a fourth embodiment will be described. 4th
The example is an example of the fourth embodiment. The fourth embodiment will be described with reference to FIGS.

The processes up to the formation of the capacitance film 3 (S2 in FIG. 14) are the same as those in the first to third embodiments.

After forming the ST film 3, the grain boundary portion 2 'on the surface of the capacitor film 3 was removed by using any of the first to third embodiments (see S3 in FIG. 14 and FIG. 10).

After that, Pt 107 is applied as the upper electrode 4 to E.
Deposited 100 nm by CRCVD (S1 in FIG. 14).
4 and FIG. 11).

The deposition conditions at this time are as follows. Pt (DPM) 2 was used as a raw material, the film forming temperature was set to 250 ° C., the film forming chamber pressure was set to 7 mTorr, the plasma power was set to 750 W, and the organometallic raw material was transported to the film forming chamber using argon Ar as a carrier gas.

A portion 2 where no grain boundary 2 is removed by using the CVD method having good coverage.
'Also deposits Pt (see FIG. 11).

Thereafter, the sample is heat-treated at 600 ° C. in nitrogen for 30 minutes (see S15 in FIG. 14 and FIG. 12). At this time, Pt in the portion of the grain boundary surface portion 2 ′ does not come into contact with the grain boundary 2 due to the deposition and condensation of Pt 107 due to recrystallization.

Thereafter, the upper electrode 4 is processed to form a capacitor (see S16 in FIG. 14 and FIG. 12).

Although Pt is used as the upper electrode 4 in the fourth embodiment, the same effect can be obtained with silicide of W or Ti.

Although Ru is used as the lower electrode 101 in the first to fourth embodiments and Au is used as the upper electrode 4 in the first to third embodiments, platinum (Pt) is used for these electrodes 101 and 4. Hereinafter, Pt), iridium (Ir), palladium (Pd), tungsten (W), Ti (titanium) and their oxides and nitrides, and oxides such as strontium ruthenium oxide (hereinafter SrRuO3) are used. Has the same effect.

Further, in the above embodiment, ST was used as the capacitance film 3, but it is represented by ABO3, where A is Ba, S
at least one of r, Pb, Ca, La, Li, or K, and B is Zr, Ti, Ta, Nb, Mg, F
e, Zn, or at least one element of W, or a chemical formula of (Bi2O2) (Xm-
1YmO3m + 1) (m is a positive integer), X is at least one of Ba, Sr, Pb, Ca, K, or Bi, and Y is Nb, Ta, Ti, or W Or one or more elements of the formula
The same effect can be obtained with the capacitance film 3 made of a2O5 or BaMgF4.

[0074]

[0075]

According to the method of manufacturing a capacitor according to the present invention,
Accordingly, a method for manufacturing a capacitor includes a lower electrode, a capacitor film having a columnar structure formed of grains and grain boundaries stacked on the lower electrode, and an upper electrode stacked on the capacitor film. The method includes a first step of forming the lower electrode, a second step of stacking the capacitor film on the lower electrode after the first step, and a step of forming the capacitor film after the second step. A third step of etching the upper part of the grain boundary constituting the above, a fourth step of depositing an upper electrode on the upper part of the capacitor film using a processing method having poor coverage after the third step, Since the method includes a fifth step of etching the upper electrode after the fourth step, a relatively simple configuration is used for the grain boundary.
Leakage current path can be avoided.

Further, instead of the fourth and fifth steps,
Following the third step, a sixth step of depositing an upper electrode on the capacitor film using a processing method with good coverage, a seventh step of heat-treating the upper electrode after the sixth step, Since the method includes the eighth step of processing the upper electrode following the seventh step, the same effects as above can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of a capacitor structure according to the present invention.

FIG. 2 is a cross-sectional view illustrating each manufacturing process of a capacitor according to a second embodiment.

FIG. 3 is a cross-sectional view showing each manufacturing step of the capacitor according to the second embodiment.

FIG. 4 is a cross-sectional view showing each manufacturing step of the capacitor according to the second embodiment.

FIG. 5 is a characteristic diagram of leakage current density versus applied voltage.

FIG. 6 is a cross-sectional view showing each manufacturing step of the capacitor according to the third embodiment.

FIG. 7 is a cross-sectional view showing each manufacturing step of the capacitor according to the third embodiment.

FIG. 8 is a cross-sectional view showing each manufacturing step of the capacitor according to the third embodiment.

FIG. 9 is a cross-sectional view showing each manufacturing step of the capacitor according to the fourth embodiment.

FIG. 10 is a sectional view showing each manufacturing step of the capacitor according to the fourth embodiment.

FIG. 11 is a cross-sectional view showing each manufacturing step of the capacitor according to the fourth embodiment.

FIG. 12 is a cross-sectional view showing each manufacturing step of the capacitor according to the fourth embodiment.

FIG. 13 is a flowchart showing each manufacturing process of the capacitor according to the second embodiment.

FIG. 14 is a flowchart showing each manufacturing process of the capacitor according to the fourth embodiment.

FIG. 15 is a sectional view of an example of a conventional capacitor structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Grain 2, 2 'grain boundary 3 Capacity film 4 Upper electrode 100 Substrate 101 Lower electrode

Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/822 H01L 21/8242 H01L 27/04 H01L 27/108

Claims (6)

(57) [Claims] 1. A method of manufacturing a capacitor, comprising: a lower electrode; a capacitor film having a columnar structure laminated on the lower electrode and composed of grains and grain boundaries; and an upper electrode laminated on the capacitor film. A first step of forming the lower electrode, a second step of stacking the capacitor film on the lower electrode after the first step, and a step of forming the capacitor film after the second step. A third step of etching the upper part of the grain boundary to be constituted;
Following the third step, a fourth step of depositing an upper electrode on the capacitor film using a processing method having poor coverage, and a fifth step of etching the upper electrode after the fourth step.
And a method for producing a capacitor. 2. A sixth step of, instead of the fourth and fifth steps, depositing an upper electrode on the upper part of the capacitor film using a processing method having good coverage next to the third step;
A seventh step of annealing the upper electrode next to the step, the manufacturing method according to claim 1, wherein the capacitor, characterized in that it comprises an eighth step of processing the upper electrode to the next seventh step. 3. The method of claim 3, wherein the third step selectively etches only the grain boundary.
2. A method for manufacturing the capacitor according to 1 . 4. Production of the third step of claim 1, wherein etches both the grain and the grain boundary, wherein said that the direction of the etching rate of the grain boundary is higher than the grain capacitor Method. 5. The method of claim 3, wherein the third step is to immerse the capacitor film in an etchant comprising hydrofluoric acid and pure water to selectively etch the grain boundary.
4. The method for manufacturing a capacitor according to 3 . 6. The method according to claim 1, wherein the third step is performed using hydrofluoric acid gas.
4. The method according to claim 3, wherein the capacitor film is etched by an R plasma etching method.