JP3285147B2 - Method of forming fine contact and via hole - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a method for forming a fine contact and a via hole for a gate electrode or a metal wiring located thereunder in an interlayer insulating film such as iO ₂ .

[0002]

2. Description of the Related Art Conventionally, as methods for forming fine contacts and via holes, for example, JP-A-03-166720, JP-A-05-102107 and JP-A-09-0.
A method described in Japanese Patent No. 82664 is known.
These conventional methods will be briefly described with reference to FIG. 3 and include the following steps.

[0003] In FIG. 3 (a), a wiring 3 formed on a first interlayer film 1 is replaced with a second interlayer film 2 in the next step.
(FIG. 3B). Interlayer film 2 of the second, after the polishing by CMP, resist film 4 having a predetermined hole pattern is provided, the hole 6 is formed by lithography in accordance with the hole pattern, and then be subjected to hole etching ring As a result, a fine contact and a via hole 7 'are formed.

[0004]

However, in the above-mentioned conventional method, since a via hole is formed after polishing of an interlayer film by CMP, there is a limit to miniaturization.

[0005]

According to the present invention, there is provided a method for forming fine contacts and via holes, comprising the steps of: forming an interlayer insulating film on a semiconductor substrate on which a gate electrode or a metal wiring is formed ; Resist on the interlayer insulating film
A step of forming a film and the resist by lithography
Forming a hole pattern to preparative membranes, taper etching down to form a via hole of forward tapered shape the interlayer insulating film by dry etching with a taper etching
And grayed step, a step of removing the resist film, polishing the interlayer insulating film by CMP, a more composed step
It is characterized by passing in order .

[0006] The present invention also relates to fine contacts and vias.
In the method of forming a hole, a gate electrode or a
Forming an interlayer insulating film on the semiconductor substrate on which the wiring is formed
Forming a resist film on the interlayer insulating film.
The resist film by lithography.
Process to form a metal pattern and dry etching
Forward taper type by taper etching the interlayer insulating film
Taper etching step to form a via hole in the shape of
Removing the resist film; and the taper etch.
Via hole formed in a forward tapering step
Providing an organic film so as to fill the gap;
Etching back to a certain thickness and before CMP
Polishing the interlayer insulating film and removing the organic film
And the steps consisting of:
You.

Further, the present invention forms a via hole.
Forming an interlayer insulating film on a semiconductor substrate
Forming a resist film on the interlayer insulating film
Patterning the resist film;
The interlayer insulation is performed using the turned resist film as a mask.
Etch the edge film to form a forward tapered via hole
Forming, and removing the resist film;
The interlayer insulating film having a forward tapered via hole
Steps of polishing by CMP and steps consisting of
It is characterized by doing.

The present invention also relates to a method for forming a via hole.
Forming an interlayer insulating film on a semiconductor substrate
Forming a resist film on the interlayer insulating film;
Patterning the resist film;
The interlayer insulating film using the patterned resist film as a mask.
To form a forward tapered via hole
Removing the resist film; and removing the resist film.
The forward tapered shape formed in the per etching process
Providing an organic film so as to fill the via hole;
A step of etching back the organic film to a predetermined thickness;
Polishing the interlayer insulating film with P;
And the steps consisting of
Features.

As a result, finer contacts and via holes can be formed as compared with the conventional method in which hole etching is performed after CMP polishing.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1A shows a state in which a wiring 3 is formed on a first interlayer film 1 such as SiO ₂ on a semiconductor substrate on which a gate electrode or a metal wiring is formed. A second interlayer film 2 is provided so as to cover the wiring 3. The second interlayer film 2 is formed to a thickness of, for example, 1000 nm and global planarization is performed. A resist film 4 having holes 6 in a predetermined pattern is provided (FIG. 1B).

Next, the second interlayer film 2 exposed by the hole 6 is tapered by dry etching to form a forward tapered via hole 7 having a taper angle θ degrees. Thereafter, the resist film 4 is removed by, for example, ashing using oxygen plasma and a wet stripping process (FIG. 1C). After that, the surface of the second interlayer film 2 is polished by CMP so that
Reduce to about 0 nm. As a result, a contact and a via hole 7 having an opening diameter (300 to 1000 / tan θ) mm are finally formed (FIG. 1D).

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention. In this example, the surface of a first interlayer insulating film 1 on a semiconductor substrate on which a gate electrode or a metal wiring 3 is formed is globally flattened, and a resist film having a hole 6 having a diameter of, for example, 0.3 μm is formed thereon by lithography. After forming the via hole 7 having a forward tapered shape with a taper angle θ degrees by etching the interlayer insulating film 2 by dry etching, the process until the resist film 4 is removed (FIG. 2)
(A) to FIG. 2 (c)) are the same as the steps shown in FIG. 1 (a) to FIG. 1 (c) in the first embodiment.

In the second embodiment, after the resist film 4 is removed, an organic film is applied on the semiconductor substrate, and the via holes 7 are filled with the organic film 8 (FIG. 2D). Then, the remaining organic film 8 is removed by etching back by dry etching, leaving only the bottom of the via hole 7 (FIG. 2E). Next, the second interlayer film 2 is formed by CMP.
Is polished to reduce, for example, the interlayer film thickness to about 500 nm (FIG. 2F).

Finally, the organic film remaining at the bottom of the hole is removed by wet peeling or dry peeling. As a result, finally the diameter of the opening (300-1000 / tan θ)
nm contacts and via holes are formed (FIG. 2).
(G)).

The advantage of the second embodiment is that the CM
By protecting the polishing material and polishing liquid from reaching the bottom of the contact or via hole in the interlayer film polishing step by P, the effect of preventing damage to the underlying wiring material or the Si substrate can be obtained.

[0016]

According to the present invention as described above,
A via hole is formed by a taper etching at a stage where an interlayer film is formed thick, therefore the upper polishing by CMP, it is possible to form a fine contact and via holes than the pattern formed by lithography.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a step of forming fine contacts and via holes according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a step of forming fine contacts and via holes according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a step of forming fine contacts and via holes in a conventional method.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 first interlayer film 2 second interlayer film 3 wiring 4 resist 6 hole 7 forward tapered via hole / via hole 7 ′ via hole 8 organic film

Claims (8)

(57) [Claims] 1. A fine contact and method for forming a via hole, forming an interlayer insulating film on a semiconductor substrate having a gate electrode or the metal wiring is formed, prior to
Forming a step of forming a resist film on a serial interlayer insulating film, forming a hole pattern on the resist film by lithography, a via hole of forward tapered shape and taper etching the interlayer insulating film by dry etching and the taper etching process, the resist and removing the film <br/>, step a, fine contact and method for forming a via hole, characterized in that the expiration of steps more made in order to polish the interlayer insulating film by CMP. 2. A method for forming fine contacts and via holes.
Gate electrode or metal wiring
Forming an interlayer insulating film on the formed semiconductor substrate;
Forming a resist film on the interlayer insulating film;
A hole pattern in the resist film by lithography
Forming the interlayer insulating film by dry etching
By taper etching to form a forward tapered via hole
Forming a taper etching step, and the resist film
Formed in the step of removing and the taper etching step
To fill the via hole of the formed forward taper shape
Providing an organic film, and etching the organic film to a predetermined thickness.
And backing the interlayer insulating film by CMP.
Polishing, and removing the organic film.
Contact characterized by passing through the steps sequentially
And a method of forming a via hole. 3. A method for forming a via hole, comprising:
Forming an interlayer insulating film on the conductive substrate;
Forming a resist film on the edge film, and the resist film
Patterning the patterned layer,
Etching the interlayer insulating film using a dist film as a mask
Forming a forward tapered via hole by using
Removing the resist film;
Polishing the interlayer insulating film having the holes by CMP.
And steps consisting of the following steps:
Via hole formation method. 4. A method for forming a via hole, comprising:
Forming an interlayer insulating film on the conductive substrate;
Forming a resist film on the edge film, and the resist film
Patterning the patterned layer,
Etching the interlayer insulating film using a dist film as a mask
Forming a forward tapered via hole by using
Removing the resist film and the taper etching
Fill the forward tapered via hole formed in the process
Providing an organic film so that
Etching back to a thickness, and said layer by CMP
Polishing the inter-insulation film and removing the organic film
And a via that sequentially goes through a process consisting of
How to form holes. 5. A gate electrode or a gate electrode on the semiconductor substrate.
Forming a metal wiring;
4 reaches the gate electrode or the metal wiring.
Or the method of forming a via hole according to 4. 6. The method according to claim 5, wherein the polishing is performed after the step of polishing.
The film thickness is the interlayer insulating film formed on the semiconductor substrate.
5. The film according to claim 3, wherein the film thickness is about one half of the film thickness.
A hole formation method. 7. The etching is a dry etching.
The method for forming a hole according to claim 3, wherein 8. The process for etching back the organic film.
From the top of the forward tapered via hole depending on the process.
Removed, only at the bottom of the forward tapered via hole
The method for forming a via hole according to claim 7, which is left.