JP3285443B2 - Charge pump - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump, and more particularly, to a charge pump used, for example, in a semiconductor memory device.

[0002]

2. Description of the Related Art FIG. 12 is a circuit diagram of a charge pump generally used in a semiconductor memory device, and FIG.
FIG. 3 is a diagram showing a structure of an NMOS transistor of No. 2;

Referring to FIGS. 12 and 13, charge pump 131 includes NMOS transistors 133, 13
4,135,136,137,138,139.
The power supply voltage (Vcc) 132 is input to the gate and the source of the NMOS transistor 133. NM
The output from the drain of the NMOS transistor 133 is input to the source and the gate of the OS transistor 134 via the connection point A. NMOS transistor 1
35 are connected to the source and gate of NM via a connection point B.
An output from the drain of the OS transistor 134 is input. An output is input to the source and the drain of the NMOS transistor 136 from the drain of the NMOS transistor 135 via the connection point C. NMOS
The output from the drain of the NMOS transistor 136 is input to the source and the gate of the transistor 137 via the connection point D. NMOS transistor 138
Are connected to the source and gate of the
An output from the drain of the transistor 137 is input. The source and the gate of the NMOS transistor 139 are connected to the NMOS transistor 138 via the connection point F.
The output from the drain is input.

[0004] A capacitor 140 is connected to the connection point A, and a signal PH is input to the capacitor 140. A capacitor 141 is connected to the connection point B, and a signal / PH which is a signal complementary to the signal PH is input to the capacitor 141. Connection point C
Is connected to a capacitor 142 to which a signal PH is input. A capacitor 143 is connected to the connection point D, and a signal / PH is input to the capacitor 143. A capacitor 144 is connected to the connection point E, and the signal PH is input to the capacitor 144. A capacitor 145 is connected to the connection point F, and a signal / PH is input to the capacitor 145. Finally, a high voltage (HV) obtained by boosting the power supply voltage (Vcc) is obtained from the drain of the NMOS transistor 139.

From the NMOS transistor 133 to the NMOS
The structure of the transistor 139 is described. For example, FIG.
As shown in FIG. 3, the NMOS transistor 134 has p-
n ₊ source 147 formed in well 146 and p
N ₊ drain 148 formed in well 146
And a gate 149. The source 147 is connected to the gate 149, and is connected to the NMOS transistor 1
The output from drain 148, which is also the source of 35, is NM
The signal is input to the gate of the OS transistor 135.

FIG. 14 is an equivalent circuit diagram of the charge pump shown in FIG. 12, and FIG. 15 is a diagram for explaining the operation of the charge pump shown in FIG.
FIG. 15A is a diagram showing an example of the signal / PH, and FIG. 15B is a time chart showing an example of the signal / PH. FIG.

The NMOS transistor 13 shown in FIG.
3,134,135,136,137,138,139
Are the diodes 150, 151, and 15 shown in FIG.
2,153,154,155,156.

The operation will be described with reference to FIGS. The signal PH and the signal / PH are complementary pulse signals of the Vcc level as shown in FIG. 15, and the signal PH is input to the capacitors 140, 142, 144.
The signal / PH is input to capacitors 141, 143, and 145. Then, in synchronization with the signal PH and the signal / PH, the potentials at the connection points A, B, C, D, E, and F rise and fall due to coupling. For example, when the potentials at the connection points A, C, and E rise, the potentials at the connection points B, D, and F tend to fall. However, from the characteristics of the diode, the connection point A →
A current flows through B, C → D, E → F, and the connection points B,
The potentials of D and F do not drop significantly. At the next timing, when the potentials at the connection points B, D, and F rise, the potentials at the connection points A, C, and E tend to fall. However, also in this case, due to the characteristics of the diode, current flows through the connection points B → C and D → E, and the potentials at the connection points A, C, and E do not decrease significantly. By such repetition, a high potential (HV) sufficiently higher than the potential (Vcc) of the power supply voltage 132 is output. That is, the charge pump outputs a potential whose absolute value is larger than the applied initial potential.

[0009]

However, in the charge pump shown in FIG. 12, since only one output is taken from the last end, when a plurality of high voltages are required, for example,
Multiple charge pumps are required. As the plurality of high voltages, three patterns of different positive potential levels, different negative potential levels, and positive and negative potential levels can be considered. Therefore, for example, in order to obtain two outputs, two charge pumps are required for each of the above three patterns.

Generally, a charge pump is a circuit occupying a very large area, so mounting a plurality of charge pumps leads to an increase in chip area.

On the other hand, the diode of the charge pump shown in FIG. 14 is constituted by connecting the source and the gate of the NMOS transistor.
Approximately, (amplitude of signal given as pulse-MOS
It is expressed by (the threshold value of the transistor) × the number of stages. As can be seen from this relationship, the physical quantity that has the most influence on boosting is the threshold voltage Vth of the MOS transistor, which is expressed as in equation (1).

[0012] Vth = VTO + γ {(| 2φ F -VBS |) 1/2 - (| 2φ F |) 1/2} ... (1) where VTO is the back gate, the potential difference between the source 0
Is the threshold voltage at V, γ is the substrate threshold coefficient, and 2φ _F is strong-inver.
VBS is the potential difference between the back gate and the source (Vbb-Vss, taking a negative value).

As described above, the MOS represented by the formula (1)
If the threshold voltage of the transistor becomes a constant value or becomes smaller as the number of stages increases, the boosting should be performed sufficiently. However, although the back gate is common,
Since the source potential of the MOS transistor increases as the charge pump rises, the back gate takes a large negative potential with respect to the source as the charge pump rises. Therefore, the threshold value Vth of the MOS transistor expressed by the expression (1) increases, and the amplitude (V
cc). The boosting performed by one stage of the charge pump is
(Amplitude of signal given as pulse−threshold of MOS transistor), this term decreases as the threshold of the MOS transistor increases, that is, as the charge pump becomes higher.
As a result, even if the number of charge pump stages is increased, sufficient boosting cannot be performed after a certain number of stages.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems and to provide a charge pump capable of sufficiently boosting the voltage by eliminating the back gate effect and independently obtaining outputs of different potential levels. It is.

[0015]

According to a first aspect of the present invention, there is provided a charge pump, comprising: a plurality of first semiconductor regions formed on an insulating film provided on a substrate and having a first conductivity; A plurality of second semiconductor regions formed on the insulating film and having a second conductivity different from the first conductivity in contact with each of the first semiconductor regions; using a second semiconductor region as a diode, and a respective diode connected in series, one end of a charge pump outputs a positive or negative voltage gives a signal to each of the diodes, the series connected diodes Side , a predetermined first voltage is supplied by first supply means.
The positive voltage from the other end of the diode connected in series.
Output to the other end of the diode connected in series .
2 is supplied by the second supply means and connected in series.
A negative voltage is output from one end of the diode.

According to a second aspect, the first semiconductor region of the first aspect includes a p-type semiconductor region.
Including an n-type semiconductor region.

According to the third aspect, the first voltage is higher than the second voltage.
High.

According to a fourth aspect, the first supply means of the third aspect is provided.
Includes a first P-channel transistor and a second supplier
The stage includes a first N-channel transistor.

According to a fifth aspect, the second supply means of the fourth aspect is provided.
Is further connected in series with the first N-channel transistor.
A second diode connected in series with one end of the
Includes N-channel transistors.

According to a sixth aspect, the first supply means of the fourth or fifth aspect further comprises a second P-channel transistor connected in series between the first P-channel transistor and the other end of the diode connected in series. Including channel transistors. In claim 7, the first supply means of claim 6 further includes a third N-channel transistor connected in parallel with the first P-channel transistor.

[0021]

The charge pump according to the first aspect of the present invention has a first
Supply means operates and the other end of the diode connected in series
From possible outputs a positive high voltage, the second supply means is operated
A negative high voltage can be output from one end of the diodes connected in series .

A charge pump according to a second aspect of the present invention comprises:
The first semiconductor region is a p-type semiconductor region, and the second semiconductor region is an n-type semiconductor region. For example, a positive or positive voltage which is sufficiently boosted without causing a physical phenomenon such as a back gate effect that prevents boosting. Can output negative high voltage.

The charge pump according to the third aspect of the present invention
The first voltage is set higher than the second voltage.

According to a fourth aspect of the present invention, there is provided a charge pump comprising:
A first P-channel transistor as a first supply means
And a first N-channel transistor as a second supply means.
A positive or negative high voltage can be output using a star.

According to a fifth aspect of the present invention, there is provided a charge pump comprising:
As a second supply output, a second N-channel transformer
The reliability of the operation of the second supply means can be improved by using a resistor.
Wear.

The charge pump according to the invention of claim 6 is:
By using a second P-channel transistor as the first supply unit, the reliability of the operation as the first supply unit can be improved. The charge pump according to the invention of claim 7 is:
The reliability of the operation of the first supply means can be further improved by using a third N-channel transistor as the first supply means.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a description will be given of a case where positive high voltages having different potential levels can be output by one charge pump.

FIG. 1 is a circuit diagram of a charge pump capable of outputting voltages of different positive potential levels and a block diagram of a drive circuit thereof. FIG. 2 is a circuit diagram of the drive circuit and a block diagram of an oscillator of FIG. FIG. 3 is a time chart showing signals PH and / PH output from the drive circuit of FIG. Hereinafter, only portions different from the conventional example shown in FIG. 12 will be described.

This charge pump 1 includes an NMOS transistor 1 in addition to the charge pump 131 shown in FIG.
39, 3, 5, 7, 9, and 11 are provided. That is,
The output from the drain of the NMOS transistor 139 is
The signal is input to the gate and source of the NMOS transistor 3 via the connection point H. The output from the drain of the NMOS transistor 3 is input to the gate and the source of the NMOS transistor 5 via the connection point I. The output from the drain of the NMOS transistor 5 is input to the gate and the source of the NMOS transistor 7 via the connection point J. The output from the drain of the NMOS transistor 7 is input to the source and the gate of the NMOS transistor 9 via the connection point K. Accordingly, the capacitor 13 is connected to the connection point H, the capacitor 15 is connected to the connection point I, the capacitor 17 is connected to the connection J, and the capacitor 19 is connected to the connection point K.

The connection point F shown in FIG.
The capacitor 145 is connected to the connection point F shown in FIG. 1, and further connected to the gate and the source of the NMOS transistor 11. Capacitor 14
0, 141, 142, 143, 144 are connected to the first drive circuit 21 and the capacitors 145, 13, 15, 15, 1
7 and 19 are connected to the second drive circuit 23.

The capacitors 140, 142, 144 include
The signal PH1 which is an output from the first drive circuit 21 is input, and the capacitors 141 and 143 are supplied to the first drive circuit 21
And the signal / P which is a complementary signal of the signal PH1
H1 has been input. Capacitors 145, 15, 19
, A signal PH2 which is an output of the second drive circuit 23 is inputted to the capacitors 13 and 17, and a signal / PH which is an output of the second drive circuit 23 and is a complementary signal of the signal PH2 is provided to the capacitors 13 and 17.
2 has been entered.

As shown in FIG. 2, the internal configuration of the first drive circuit 21 includes an inverter 27 to which the pulse signal CLK output from the oscillator 25 is input, and inverters 29 and 37 to which the output of the inverter 27 is input. , Inverter 29,
Inverters 31 and 3 to which respective outputs of 37 are inputted
9, inverters 33 and 41 to which the respective outputs of the inverters 31 and 39 are input, and an inverter 35 to which the output of the inverter 33 is input. The output of inverter 35 is signal / PH1, and the output of inverter 41 is signal PH1.

The second drive circuit 23 receives the pulse signal CLK output from the oscillator 25 on one side and the signal P on the other side.
NAND 43 to which a signal MODE for controlling H2 and signal / PH2 is input, inverters 45 and 53 to which the output of NAND 43 is input, inverters 47 and 55 to which respective outputs of inverters 45 and 53 are input, and inverter 47 , And 55, and an inverter 51 to which the output of the inverter 49 is input. The output of inverter 51 is signal PH2, and the output of inverter 57 is signal / PH2.

With respect to the charge pump having such a circuit configuration, the first drive circuit 21 and the second drive circuit 23 are arranged as shown in FIG.
When a signal as shown in FIG.
VPP1 which is the output of the transistor 11 is boosted to a high voltage, and VPP2 which is the output of the NMOS transistor 19
Is not boosted. On the other hand, when the first drive circuit 21 and the second drive circuit 23 output signals as shown in FIG. 3B, VPP1 and VPP2 are boosted at different positive potential levels.

This will be described in detail. FIG.
In order to output a signal as shown in (a), the signal MODE input to the NAND 43 of the second drive circuit 23 is output.
Are at the L level. The output of the NAND 43 is H
Level, and the signal PH2 goes to the H level via the inverters 45, 47, 49, and 51.
The signal / PH2 goes low through 55 and 57.
On the other hand, the signal / PH1, which is the output of the first drive circuit 21, is
It becomes a signal complementary to the pulse signal CLK output from the oscillator 25 via the inverters 27, 29, 31, 33, 35, and the signal PH1 is output as a pulse signal equivalent to the output of the pulse signal CLK.

Thus, the capacitor 14 shown in FIG.
Since the pulse signals PH1 and / PH1 from the first drive circuit 21 are input to 0, 141, 142, 143 and 144, VPP1 which is the output of the NMOS transistor 11 is output.
Is boosted to a high voltage. On the other hand, the second drive circuit 2
The signals PH2 and / PH2, which are the outputs of the NMOS transistor 9, are not pulse signals.
2 is not boosted.

Next, when the signal MODE input to the NAND 43 of the second drive circuit 23 is at the H level, the signal PH
2, / PH2 becomes a pulse signal as shown in FIG. 3B and is input to the capacitors 145, 13, 15, 17, 19. Therefore, the NMOS transistor 139,
The boosting is also performed at 3, 5, 7, and 9, and VPP2 becomes VP
The voltage is further increased than P1. That is, the charge pump 1 can output different positive potential level boosted voltages VPP1 and VPP2 when the signal MODE input to the NAND 43 of the second drive circuit 23 is at the H level, and the signal M
When ODE is at the L level, a positive high voltage VPP1 that is boosted by the number of stages corresponding to the first drive circuit 21 can be output.

FIG. 4 is a circuit diagram of a charge pump capable of outputting high voltages having different negative potential levels and a block diagram of a drive circuit thereof. Hereinafter, only the portions different from the charge pump shown in FIG. 1 will be described.

PMOS instead of NMOS transistor
High voltages of different negative potential levels are output using the transistors. That is, the NMOS transistor 13
3,134,135,136,137,138,13
Instead of 9, 3, 5, 7, 9, 11, PMOS transistors 61, 63, 65, 67, 69, 71, 73, 7
5, 77, 79, 81, 83 are provided. And P
MOS transistor 61 has its gate and source connected to ground potential 59. Thereby, the second drive circuit 23
, Which is the output of the PMOS transistor 83, when the signal MODE input to the NAND
VP which is the output of P1 and PMOS transistor 81
P2 is a high voltage at a different negative potential level and the signal M
When ODE is at L level, only VPP1 is output as a negative high voltage.

Note that the number of stages for the first drive circuit 21 and the second drive circuit 23 is not determined, and the number of stages for the first drive circuit 21 is N, and
May be a general number of steps such that the number of steps for M is M steps.

The charge pumps shown in FIGS. 1 and 4 output positive high voltages of different potential levels or negative high voltages of different potential levels.
The present invention is not limited to the case where two outputs are obtained, and the same concept can be applied to the case where three or more outputs are obtained.

Next, even with the charge pumps shown in FIGS. 1 and 4, in order to obtain a positive or negative high voltage,
Again, since two charge pumps are required, the chip area increases in such a case. for that reason,
In the following, the present invention will be described first to obtain a positive or negative high voltage which is sufficiently boosted without the back gate effect, and thereafter, is sufficiently boosted by one charge pump, and if necessary, A charge pump capable of obtaining a positive or negative high voltage will be described.

FIG. 5 is a diagram showing the structure of a charge pump required in the present invention. FIG. 6 is a diagram showing a charge pump capable of obtaining a positive high voltage using the diode according to the structure of FIG. It is the equivalent circuit diagram shown.

In recent years, various types of SOI substrates have been proposed, and SOI substrates have been manufactured by various manufacturing methods. For example, an SOI substrate 99 as shown in FIG. 5 is manufactured. In the SOI substrate 99, p-type regions 85a, 85b, 85c are formed at predetermined intervals in an insulating film 97 on a Si substrate 95, and an n-type region 87a is formed on the insulating film 97 so as to be in contact with the p-type region 85a. , N-type region 87b is p
Formed on the insulating film 97 so as to be in contact with the mold region 85b;
N-type region 87c is formed on insulating film 97 so as to be in contact with p-type region 85c. Power supply voltage (Vcc) 89 is connected to p-type region 85a, n-type region 87a and p-type region 85b are connected, and n-type region 87b and p-type region 85c are connected.
Are connected, and the n-type region 87c is connected to the adjacent p-type region.

The n-type region 87a and the p-type region 85b are further connected to a capacitor 91, and the n-type region 87b and the p-type region 85c are connected to a capacitor 93. The signal PH is input to the capacitor 91, and the signal / PH is input to the capacitor 93. Various methods for fabricating an SOI substrate have been proposed, and any of the fabrication methods may be used. However, as shown in FIG.
The charge pump when used as two diodes is
It is represented by an equivalent circuit as shown in FIG.

In this case, the charge pump 10 shown in FIG.
0 is equivalent to the charge pump 131 shown in FIG.
1,102,103,104,105,106,107
Uses a junction diode shown in FIG. Therefore, there is no back gate effect, the threshold voltage Vth in the equation (1) does not increase, and as the number of stages of the charge pump increases, the positive high voltage (POSITI
VE HIGH VOLTAGE).

FIG. 7 is an equivalent circuit diagram showing a charge pump capable of obtaining a negative high voltage using the diode having the structure of FIG. Only parts different from FIG. 6 will be described.

Diodes 101, 102, 103, 10
Instead of 4,105,106,107, diode 1
08, 109, 110, 111, 112, 113, 11
4 is used. The diodes 108 to 114 are different from the alternatives only in the structural difference shown in FIG. A ground voltage (GND) 115 is connected to the n-type region of diode 108. As a result, the ground voltage 115 does not leak from the diode 108 to the well and the substrate in the diode 114, so that the negative high voltage (NEGATIVE HIGH VOLT
AGE) and output.

FIG. 8 is a circuit diagram of the charge pump according to the first embodiment of the present invention. Hereinafter, only portions different from FIG. 6 will be described.

A power supply voltage (Vcc) 89 and a first PMOS transistor (P
1) 116 is provided. The other source / drain is connected to the diode 101 via the connection point L. A signal for controlling the first PMOS transistor 116 is provided at the gate.
POSITIVE IN is input. Further, a first NMOS transistor (N1) 117 having one of the source and the drain connected to the diode 107 via the connection point M is provided. The other source / drain has a ground potential (GND) of 1
15 and a gate, a signal NEGA which is a control signal.
TIVE IN is input.

Next, the operation will be described. In order to generate a positive high voltage (POSITIVE HIGH VOLTAGE), an L level 0V signal POSITIVE IN is input to the gate of the first PMOS transistor 116, and the first NMO
0V which is L level is applied to the gate of the S transistor 117.
Signal NEGATIVE IN is input, the first P
The MOS transistor 117 is turned on, and the first N
MOS transistor 117 is turned off. Thereby, this charge pump has a circuit configuration equivalent to that of the charge pump shown in FIG.
As the complementary signal (Vcc level)
To 145, the positive high voltage (POSITIVE HIG
H VOLTAGE) is output.

On the other hand, in order to obtain a negative high voltage, the signal POSITIVE IN of the power supply voltage (Vcc) at the H level is input to the gate of the first PMOS transistor 116, and the first NMOS transistor 117 is turned on. At the gate,
H level power supply voltage (Vcc) signal NEGATIVE IN
Is input, the first PMOS transistor 116 is turned off, and the first NMOS transistor 117 is turned on. As a result, this charge pump is
And a signal having a negative high voltage (NEGATIVE HIGH VOLTAGE) is obtained. As described above, the first P which is an example of the first switching means is
By controlling the MOS transistor 116 and the NMOS transistor 117 which is an example of the second switching means,
The power supply voltage (Vc) is connected to one end of the diode connected in series.
When c) is applied, a positive high voltage is output, and the ground voltage (GND) is applied to the other of the series-connected transistors.
, A negative high voltage is output. Therefore, it is not necessary to separately prepare the positive charge pump and the negative charge pump, and the chip area can be reduced.

By the way, in the embodiment shown in FIG.
Assuming that the positive high voltage is 8-10V, the first NMO
Since a voltage of 0 V is applied to the gate of the S transistor 117 at that time, a stress of 8 to 10 V is applied. On the other hand, if the negative high voltage is a voltage of -8 to -10 V, the first PMOS transistor 11
6 has a power supply voltage (Vcc) of 3
Since a voltage of about 5 V is applied, a stress of about 13 V is applied to the first PMOS transistor 116.
Therefore, in order to obtain reliability, first the first P
It is necessary to reduce the stress on the MOS transistor 116.

FIG. 9 is a circuit diagram of a charge pump according to a second embodiment of the present invention. Hereinafter, only portions different from FIG. 8 will be described.

One of the source / drain is a first PMOS.
A second PMOS transistor (P2) 118 connected to the transistor 116 and having the other source / drain connected to the diode 101 via the connection point L is provided. Its gate is connected to the ground voltage (GND) 119. Since the operation is the same, the description is omitted.

The role of the second PMOS transistor 118 is to alleviate the stress on the first PMOS transistor 116 and to improve the reliability. In particular, the effect is exhibited when a negative high voltage is output. Also in this charge pump, a positive high voltage or a negative high voltage is obtained according to the purpose, and it is not necessary to separately prepare a positive charge pump and a negative charge pump, and the chip area can be reduced.

FIG. 10 is a circuit diagram of a charge pump according to a third embodiment of the present invention. Only parts different from FIG. 9 will be described.

In the embodiment shown in FIG. 9, in order to reduce the stress on the first PMOS transistor 116, the second PMOS transistor 116 is used.
Although the MOS transistor 118 is provided, in this embodiment, a second NMOS transistor (N2) 120 is provided to reduce the stress on the first NMOS transistor 117. That is, one of the source and the drain is connected to the first NMOS transistor 117.
And a second NMOS transistor 120 whose other source and drain are connected to the diode 107 via the connection point M. A power supply voltage (Vcc) 121 is input to the gate. The operation in this embodiment is omitted for simplicity.

The role of the second NMOS transistor 120 is to alleviate stress on the first NMOS transistor 117 and improve reliability. In particular, the effect is exhibited when a positive high voltage is output. Also in the charge pump having such a configuration, a positive high voltage or a negative high voltage is output according to the purpose, so that it is not necessary to separately prepare a positive charge pump and a negative charge pump, and the chip area is reduced. Is suppressed.

FIG. 11 is a circuit diagram of a charge pump according to a fourth embodiment of the present invention. Hereinafter, only portions different from FIG. 10 will be described.

In the embodiment shown in FIG. 10, the first P
A second PMOS transistor 118 is provided to alleviate stress on the MOS transistor 116, and a first N
Although the second NMOS transistor 120 is provided to alleviate the stress on the MOS transistor 117, the stress on the first PMOS transistor 116 is increased. This is as described in the first embodiment shown in FIG.

Therefore, a third NMOS transistor (N3) is further provided in parallel with the first PMOS transistor 116.
Are connected to form an inverter 124. Inverter 1
24, the first PMOS transistor 1
/ POSITIVEIN which is an inverted signal of the signal POSITIVE IN,
Is entered.

The operation will be described. In order to generate a positive high voltage, the 0V signal / POSITIVE IN is input to the inverter 124, and the 0V signal NEGATIVE IN is input to the gate of the first NMOS transistor 117. The power supply voltage (Vcc) 89 is applied to the first PMOS transistor 116,
The voltage is transmitted through the second PMOS transistor 118, boosted by the diodes 101 to 107 connected in series, and output as a positive high voltage (POSITIVE HIGH VOLTAGE). On the other hand, in order to obtain a negative high voltage, the signal / POSITIVE IN input to the inverter 124 is input as Vcc at H level, and the signal NEGATIVE at V level at H level is input to the gate of the first NMOS transistor 117. IN
Is entered. The ground voltage 115 is applied to the diodes 107 to 101 connected in series via the first NMOS transistor 117 and the second NMOS transistor 120.
Is boosted sufficiently and a negative high voltage (NEGATIVE HIGH VOLTAG
E).

The feature of this embodiment is that the provision of the third NMOS transistor 123
The floating state of the node between the OS transistors 116 and 118 is avoided, and the reliability of the device is further improved. Also in this embodiment, since a positive high voltage or a negative high voltage is generated by one charge pump depending on the purpose, it is not necessary to separately prepare a positive charge pump and a negative charge pump, and the chip area is reduced. Is suppressed.

In a situation where a positive or negative high voltage is required, for example, a negative high voltage is required when rewriting information in a memory cell in units of word lines. High voltage is required. Further, a negative high voltage is required for a DIMOR type flash memory which has been developed in recent years.

[0066]

As described above, according to the present invention, there is provided a charge pump capable of sufficiently boosting the voltage every time the number of stages is increased and obtaining a positive or negative high voltage. it can.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a charge pump capable of outputting a high voltage having a different positive potential level and a block diagram of a drive circuit thereof.

FIG. 2 is a circuit diagram of a drive circuit and a block diagram of an oscillator of FIG. 1;

FIG. 3 is a time chart showing a signal PH and a signal / PH output from the drive circuit of FIG. 2;

FIG. 4 is a circuit diagram of a charge pump capable of outputting high voltages of different negative potential levels and a block diagram of a drive circuit thereof.

FIG. 5 is a diagram showing a structure of a charge pump required in the present invention.

FIG. 6 is an equivalent circuit diagram showing a charge pump capable of obtaining a positive high voltage using the diode having the structure of FIG. 5;

FIG. 7 is an equivalent circuit diagram showing a charge pump that can obtain a high negative voltage using the diode having the structure of FIG. 6;

FIG. 8 is a circuit diagram of a charge pump according to the first embodiment of the present invention.

FIG. 9 is a circuit of a charge pump according to a second embodiment of the present invention.

FIG. 10 is a circuit diagram of a charge pump according to a third embodiment of the present invention.

FIG. 11 is a circuit diagram of a charge pump according to a fourth embodiment of the present invention.

FIG. 12 is a circuit diagram of a charge pump generally used in a semiconductor memory device.

FIG. 13 is a diagram showing a structure of the NMOS transistor of FIG.

FIG. 14 is an equivalent circuit diagram of the charge pump shown in FIG.

FIG. 15 is a diagram for explaining the operation of the charge pump shown in FIG. 14, and is a time chart showing an example of a signal PH and a signal / PH.

[Explanation of symbols]

85a, 85b, 85c p-type region 87a, 87b, 87c n-type region 101, 102, 103, 104, 105, 106, 1
07 Diode 116 First PMOS transistor 117 First NMOS transistor 118 Second PMOS transistor 120 Second NMOS transistor 122 Third NMOS transistor

Continuing from the front page (72) Inventor Shinichi Kobayashi 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Co., Ltd. USL Development Development Laboratory (72) Inventor Motoharu Ishii 4-1-1 Mizuhara, Itami-shi, Hyogo Address Mitsubishi Electric Corp. USL Development Laboratory (56) References JP-A-1-164264 (JP, A) JP-A-2-276467 (JP, A) JP-A-2-65269 ( JP, A) JP-A-4-117164 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H02M 3/07

Claims (7)

(57) [Claims] A plurality of first semiconductor regions formed on an insulating film provided on a substrate and having a first conductivity; and a plurality of first semiconductor regions formed on the insulating film and each of the first semiconductor regions. A plurality of second semiconductor regions having a second conductivity different from the first conductivity in contact with the region, wherein the first semiconductor region and the second semiconductor region in contact with each other are used as diodes. And a diode connected in series with each other, providing a signal to each diode and outputting a positive or negative voltage, wherein a predetermined first voltage is applied to one end of the series-connected diode. And a positive voltage is output from the other end of the series-connected diode, and a second supply of a predetermined second voltage to the other end of the series-connected diode is performed. Supplied by means Te, a charge pump for outputting a negative voltage from said one end of the series connected diodes. 2. The charge pump according to claim 1, wherein said first semiconductor region includes a p-type semiconductor region, and said second semiconductor region includes an n-type semiconductor region. 3. The charge pump according to claim 2, wherein the first voltage is higher than the second voltage. 4. The charge pump according to claim 3, wherein said first supply means includes a first P-channel transistor, and said second supply means includes a first N-channel transistor. 5. The apparatus according to claim 1, wherein said second supply means further comprises said first supply means.
5. The charge pump according to claim 4, further comprising a second N-channel transistor connected in series between the N-channel transistor and the other end of the series-connected diode. 6. The first supply means further comprises: the first supply means.
A second P-channel transistor connected in series between the P-channel transistor of
The charge pump according to claim 4, further comprising a channel transistor. 7. The first supply means further comprises:
N connected in parallel to the P-channel transistor
7. The charge pump according to claim 6, comprising a channel transistor.