JP3286161B2 - Power converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power conversion device suitable for a case where a power conversion unit and its control unit are installed separately.

[0002]

2. Description of the Related Art Generally, a power conversion device is an alternating current (direct current).
A power conversion unit that converts the power of the DC power into DC (AC) power;
And a control unit for controlling the power conversion unit. FIG. 10 shows an example of a thyristor leonard device for driving a DC motor as this type of power converter. This device converts an AC voltage supplied from an AC power supply 2 into a desired DC voltage by a power converter 3 and drives the DC motor 1 at a variable speed. The power converter 3 is a main part of a power conversion unit and includes a plurality of thyristor elements 10, and a pulse amplifier circuit 11 that outputs a gate pulse for firing each thyristor element in response to a gate signal from a control unit. It has.

The control unit includes a speed setting device 4 for setting a speed (voltage) reference, an acceleration / deceleration rate limiting circuit 5 for limiting the maximum rate of change of the speed (voltage) reference, and an output from the acceleration / deceleration rate limiting circuit 5. A voltage control circuit 7 for comparing the detected voltage reference with a DC voltage detection value detected via the voltage detector 6 and outputting a current reference; and a current detected via the current reference and the current detector 8. A current control circuit 9 for comparing the detected value with a phase control signal and outputting a phase control signal; a phase control circuit 12 for outputting a gate signal based on the phase control signal; and controlling the operations of the current control circuit 9 and the phase control circuit 12 Driving to
An operation circuit 13 for providing a stop signal is provided, and the DC motor 1 is controlled to a desired speed by changing the DC voltage output from the power converter 3 by setting the voltage reference to a desired value.

In the case of a power converter for driving an electric motor, a gate signal for controlling a thyristor element is generally employed in a double pulse system, and as shown in FIG. ° width gate signal Su
, Sz, Sv, Sx, Sw, Sy are output and input to the pulse amplifier circuit 11 via an external cable. Pulse amplification circuit 11 Double pulses Sug, Szg, S for firing thyristor element 10 based on this gate signal.
vg, Sxg, Swg, and Syg are output, and each thyristor element Su, Sz, Sv, Sx, Sw, and Sy of the power converter 3 is converted to 60.
It is sequentially fired with a phase difference of °, and each is made conductive only for a period of 120 °. The ignition timing is α-controlled by the phase control signal, and the power converter 3 outputs a DC voltage corresponding to the voltage reference.

[0005]

As described above, in the conventional device, when the power conversion unit and the control unit are installed separately from each other, the signal line for transmitting the gate signal becomes long, and is susceptible to noise. A signal line is required for each element, and there is a problem that the number of signal lines increases as the number of switch elements increases.

[0006] The present invention has been made in view of the above problems, and has as its object to convert a gate signal output from a control unit into a gate signal.
An object of the present invention is to provide a power conversion device that separates a selection signal designating a specific switch element and a signal giving the control timing thereof and sends them out with a small number of signal lines, and reproduces and controls the gate signal on the power conversion unit side. .

[0007]

A power converter according to the present invention includes a power converter having a plurality of switch elements, and a controller for outputting a plurality of gate signals for controlling the plurality of switch elements, respectively . the power converter, a selection signal designating a specific switching element based on the plurality of gate signals with encoding and transmitting said Sui
Means for synthesizing all the timings for turning on the switching elements and transmitting the combined signals as one timing signal, and regenerating a plurality of gate signals from the selection signal and the timing signal. Control. (Claim 1) Further, the means generates a pulse at each of the rising timings of the plurality of gate signals, adds these pulses and outputs a single timing signal, and based on the plurality of gate signals. Gate signal transmitting means for generating a plurality of second gate signals having a phase leading from that, and outputting a selection signal designating a specific switch element based on the plurality of second gate signals; Gate pulse reproducing means for selecting a specific pulse from the pulse train of the timing signal, generating a gate signal for the specific switch element at the timing of the selected pulse, and reproducing a plurality of gate signals.
(Claim 2) Further, the gate signal transmitting means is provided in the control unit, and the gate pulse regenerating means is provided in the power conversion unit, and the power conversion unit and the control unit are installed separately. (Claim 3) Further, the gate signal transmitting means outputs the selection signal as digital data and transmits the digital data serially, and the gate pulse reproducing means outputs the selection signal based on the serially transmitted digital data. Select a specific pulse from the pulse train. (Claim 4) Further, the gate pulse reproducing means selects two specific pulses from the pulse train based on a selection signal of the digital data, and controls a specific switch element at a timing of the selected two pulses. Generate a double pulse gate signal. (Claim 5) Further, the gate pulse reproducing means selects two specific pulses from the pulse train based on the selection signal of the digital data, and outputs a predetermined signal to a specific switch element at the timing of the selected two pulses. A gate signal having a pulse width of (Claim 6) Further, the power conversion unit includes a plurality of switch elements.
Three thyristors are used to form a three-phase full-wave rectifier circuit.
(Claim 7) Further, the power conversion unit is a GT instead of a thyristor.
A self-extinguishing switch element such as O, IGBT, or GTR is used. (Claim 8)

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of a power converter according to the first to fifth and seventh aspects of the present invention. This embodiment is an example of a case where a power converter using six thyristor elements for performing three-phase full-wave rectification is controlled by a double-pulse gate signal.

In FIG. 1, a phase control circuit 12 outputs six gate signals G1 for six thyristor elements in the same manner as in the prior art, and outputs all the pulses generated at the rising points of the six gate signals G1. A timing signal G2 of the added one pulse train is output. The phase correction circuit 14 outputs six gate signals G1a having advanced phases with respect to the six gate signals G1 in order to compensate for processing time due to transmission. The encoding circuit 15 encodes a selection signal for designating a specific thyristor element every time the state of the six leading phase gate signals G1a changes, and outputs it as a digital signal G1b. The pulse output circuit 16 outputs a timing signal G2a obtained by shaping the timing signal G2 into a predetermined pulse width. The decoding circuit 17 receives the digital signal G1b and outputs a selection signal G1c for specifying the thyristor element to be fired. The pulse input circuit 18 outputs a timing signal G2b having a pulse width actually given to the thyristor element based on the timing given by the timing signal G2a. The gate pulse reproducing circuit 19 reproduces and outputs six gate signals G3 for the six thyristor elements 10 based on the selection signal G1c and the timing signal G2b. Note that the decoding circuit 17, the pulse input circuit 18, and the gate pulse regeneration circuit 19 are provided on the power conversion unit side. The other components are the same as those of the related art (FIG. 8), and are denoted by the same reference numerals.

In the above configuration, as shown in FIG. 2, the gate signals G1 (SU, SZ, SV) are supplied from the phase control circuit 12.
, SX, SW, and SY) are output from the phase correction circuit 14 at a timing earlier than the gate signal G1 by the time t1, and the phase of the gate signal G1a (SU1, SZ) is corrected.
1, SV1, SX1, SW1, SY1) are output. The phase correction circuit 14 is composed of, for example, a circuit as shown in FIG. 3, and the gate signal SU for the U-phase thyristor element is shifted one timing earlier than that so as to secure a margin for compensating the processing time due to transmission. The gate signal SY for the output Y-phase thyristor element is delayed by a predetermined time Td by the timer 14a, and the rear end is cut off by the gate signal SV1 output one time later, to obtain the time t1.
A gate signal SU1 having a phase advance and a width of 120 ° is output. The same applies to the other phases, and the above-described gate signal G
1a is output.

When a change occurs in the state of the gate signal G1a, the encoding circuit 15 selects a selection signal G1c for specifying the states of the gate signals for the six thyristors immediately after the change.
Is output. That is, a change occurs in the state of the gate signal G1a, and the six switch elements SU, SZ, SV, SX, S
When a gate signal for one of the switch elements W, SY is output, the switch elements SU, SZ, SV,
As shown in FIG. 4, corresponding to SX, SW and SY, 3-bit digital data 001, 010, 011, 100, 10
1 and 110 are output and transmitted as a serial signal G1b. The value can be set to 000 when all the gate signals are off (block state), and set to 111 when all the gate signals are on (short-circuit protection state).

When the decoding circuit 17 receives the serial signal G1b and decodes the 3-bit digital data, as shown in FIG. 2, the decoding circuit 17 converts the gate signal G1a into a delay time T due to transmission processing.
The selection signal G1c (SU2, SZ2, SV2, SX2,
SW2, SY2).

On the other hand, when the timing signal G2a having a predetermined pulse width outputted from the pulse output circuit 16 is inputted, the pulse input circuit 18 receives the pulse width given to the thyristor element as shown in FIG. Timing signal G
2b (PU, PZ, PV, PX, PW, PY) are output. FIG. 5A shows a specific example of the pulse output circuit 16. When a timing signal G2a having a predetermined pulse width as shown in FIG.
8a is converted into a timing signal G2b having a narrow pulse width and output.

The gate pulse reproducing circuit 19 outputs a selection signal G
The timing signal G2b is distributed as shown in FIG. 2 based on 1c, and six gate signals G for each thyristor element are distributed.
3 (SU3, SZ3, SV3, SX3, SW3, SY3) are reproduced and output. PU and PZ of the timing signal G2b are assigned as the U-phase gate signal SU3, and the other phases are similarly given as double pulses. FIG. 6 shows a specific example of the gate pulse regeneration circuit 19 for the U phase. When the logical product of the U-phase selection signal SU2 and the timing signal G2b is established, a signal is output from the AND gate 19a.
The gate signal SU3 is output via the AND gate 19d. In this case, when a predetermined time has elapsed from the time when the first signal was output, the output of the timer 19b becomes zero, the AND gate 19c is closed, and the AND gate 19d is also closed. When the selection signal SV2 delayed by 120 ° is input, the AND gate 1 is connected via the inverter gate 19e.
9c is closed to remove unnecessary pulses.

The gate pulse reproducing circuit 19 outputs a selection signal G1c.
Since the timing signal G2b is distributed based on
As shown in (1), the U-phase selection signal SU2 must be output at an earlier timing than the target timing signal PU. Accordingly, the gate signal G1a (GU1) corresponding to the gate signal G1 (SU) output from the phase control circuit 12 is obtained.
Is set to be longer than the delay time Td2 of the selection signal G1c (SU2) transmitted through the encoding circuit 15 and the decoding circuit 17, and SU2 is earlier than PU by t2. Is output.

Next, as an embodiment of the power converter according to the first to fourth, sixth and eighth aspects of the present invention, the power converter
A case will be described in which six self-extinguishing switch elements performing phase full-wave rectification are used. In this case, as shown in FIG. 7, the gate pulse reproducing circuit 19 outputs the selection signal G
1c, the pulse train (PU, PU) of the timing signal G2b
Z, PV, PX, PW, and PY), and two wide-pulse gate signals G for each thyristor element at the timing of the selected two pulses.
3 (SU3, SZ3, SV3, SX3, SW3, SY3) are generated and output. The U-phase gate signal SU3 is a timing signal G2b.
, And output with a pulse width falling with the pulse PV of the timing signal G2b. Similarly, the other phases are also output as wide pulse gate signals.

FIGS. 8 and 9 show specific examples of the pulse input circuit 18 and the gate pulse reproducing circuit 19 used in this embodiment. As shown in FIG. 8 (a), when the timing signal G2a is input, the pulse input circuit 18 outputs a timing signal G2c whose logic value is inverted at each rising point of each pulse (binary) counter 18c. And the timing signal G
As shown in FIG. 8 (b), there is provided a one-shot circuit 18a for generating a pulse G2bP at each rising point of 2c and a one-shot circuit 18b for generating a pulse G2bN at each falling point of the timing signal G2c. The timing signals for the positive and negative self-extinguishing switch elements of the six self-extinguishing switch elements constituting the switch 3 are separated into pulses G2bP and G2bN and output. As shown in FIG. 9 (a), when the logical product of the U-phase selection signal SU2 and the timing signal G2bP is established, the gate pulse regeneration circuit 19 outputs the timing signal G via AND gates 19a and 19d.
2bP sets the flip-flop circuit 19f, and the gate signal SU3 rises and is output. When the timing signal G2bP having a phase delay of 120 ° is input while the flip-flop circuit 19f is set, the timing signal G2bP is supplied to the flip-flop circuit 1 via the AND gate 19g.
9f is reset, and the gate signal SU3 is wide (120 °).
It is output as a pulse gate signal. Of the six self-extinguishing switch elements, the gate signal for the positive-side self-extinguishing switch element (SU, SV, SW) is generated by a similar circuit, and the negative-side self-extinguishing switch element (SZ) is generated. , S
X, SY) is a timing signal G2b
It is generated by a similar circuit using G2bN instead of P.

In the above description, six gate signals are 60
Although the case of outputting at the phase interval of ° has been described, the phase interval fluctuates in the process of phase control because the phase interval becomes narrower or wider. It is necessary to ensure that the gate signal G3 having the minimum pulse width is ensured so that the signal does not disappear.

In the above description, the case where AC is converted to DC is described. However, the present invention can be applied to the case where DC is converted to AC, and can be applied to any power converter including a plurality of switch elements. Can be applied.

[0020]

According to the power converter of the present invention, it is possible to separate a selection signal designating a specific switch element from a plurality of switch elements and a signal giving its control timing and transmit a gate signal. It is possible to provide a gate signal from the control unit to the power conversion unit with a small number of signal lines, thereby providing a power conversion device with improved economic efficiency.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of a power converter according to claims 1 to 5 and 7 of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment.

FIG. 3 is a configuration diagram showing a specific example of a phase correction circuit 14 in FIG. 1;

FIG. 4 is a diagram showing the relationship between gate signals and data for explaining the operation of the encoding circuit 15 and the decoding circuit 17 of FIG. 1;

5A and 5B are diagrams showing a specific example of the pulse input circuit 18 of FIG. 1, wherein FIG. 5A is a configuration diagram, and FIG. 5B is a waveform diagram of input / output signals.

FIG. 6 is a configuration diagram showing a specific example of the gate pulse generation circuit 19 of FIG. 1;

FIG. 7 is a timing chart for explaining the operation of the embodiment of the power converter according to claims 1 to 4, 6, and 8 of the present invention.

8A and 8B are diagrams showing another specific example of the pulse input circuit 18 of FIG. 1, wherein FIG. 8A is a configuration diagram and FIG. 8B is a signal waveform diagram.

FIG. 9 is a configuration diagram showing another specific example of the gate pulse generation circuit 19 of FIG. 1;

FIG. 10 is a configuration diagram of a conventional power converter.

11A is a configuration diagram of a main part of a conventional power converter, FIG.
(B) is a timing chart for explaining the operation.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... DC motor 2 ... AC power supply 3 ... Power converter 4 ... Speed (voltage) reference setting device 5 ... Acceleration / deceleration rate limiting circuit 7 ... Voltage control circuit 8 ... Current detector 9 ... Current control circuit 10 ... Switch element 11 ... Pulse Amplifying circuit 12 ... Phase control circuit 13 ... Operation circuit 14 ... Phase correction circuit 15 ... Encoding circuit 16 ... Pulse output circuit 17 ... Decoding circuit 18 ... Pulse input circuit 19 ... Gate pulse reproduction circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H02M 7/155 H02M 1/08 H02M 7/48 H02P 7/292

Claims (8)

(57) [Claims] And 1. A power conversion unit having a plurality of switching elements, the power conversion device and a control unit for outputting a plurality of gate signals for controlling the plurality of switching elements, respectively
Oite, with a selection signal designating a specific said scan <br/> switch element transmits the encoding based on the plurality of gate signals, the total turning on the switching element, respectively
Means for synthesizing all the timings and transmitting as one timing signal, and regenerating a plurality of gate signals from the selection signal and the timing signal, and controlling the power conversion unit with the reproduced gate signals. Power converter. 2. The power converter according to claim 1,
The means generates a pulse at each of the rising timings of the plurality of gate signals, adds these pulses and outputs the added signal as one timing signal, and a plurality of leading phases based on the plurality of gate signals. A gate signal transmitting means for generating a second gate signal, and outputting a selection signal for designating a specific switch element based on the plurality of second gate signals; and determining the second signal from the pulse train of the timing signal based on the selection signal. And a gate pulse regenerating means for regenerating a plurality of gate signals by generating a gate signal for a specific switch element at the timing of the selected pulse. 3. The power converter according to claim 2, wherein
While providing the gate signal transmitting means in the control unit,
The power conversion device, wherein the gate pulse regeneration unit is provided in the power conversion unit, and the power conversion unit and the control unit are installed separately. 4. The power converter according to claim 2, wherein
The gate signal transmitting means outputs the selection signal as digital data and serially transmits the digital data, and the gate pulse reproducing means selects a specific pulse from the pulse train based on the serially transmitted digital data. A power converter characterized by the above-mentioned. 5. The power converter according to claim 2, wherein
The gate pulse reproducing means selects two specific pulses from the pulse train based on the selection signal, and generates a double pulse gate signal for a specific switch element at the timing of the selected two pulses. Power converter. 6. The power converter according to claim 2, wherein
The gate pulse generation means selects two specific pulses from the pulse train based on the selection signal, and generates a gate signal having a predetermined pulse width for a specific switch element at the timing of the selected two pulses. A power converter characterized by the above-mentioned. 7. The power converter according to claim 2, wherein
The power converter, wherein the power converter uses a six-phase thyristor as a plurality of switch elements to form a three-phase full-wave rectifier circuit. 8. The power converter according to claim 7,
The power converter includes a GTO, an ITO instead of a thyristor.
A power converter using a self-extinguishing switch element such as a GBT or GTR.