JP3287239B2 - Hierarchical cache memory and its state transition control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hierarchical cache memory which is connected to a bus capable of processing a pipeline of transactions and guarantees coherency of the cache memory.

[0002]

2. Description of the Related Art For example, a conventional hierarchical cache memory shown generally is a processor bus 101 as shown in FIG.
And a primary cache memory and a secondary cache memory having all the cache lines (columns of pairs of addresses of the main memory and cells holding the contents thereof). Layering is performed via the local bus 102. In FIG. 7B, when a transaction A for invalidating the valid cache line data of the secondary cache memory is issued to the system bus 103, the secondary cache memory hits and the primary cache memory also has valid cache line data. In order to invalidate the possibility, in response to an invalidation transaction A 'request on the local bus 102 by an invalidation transaction A request on the system bus 103, the local bus 10
A response of the invalidation transaction A on the system bus 103 is returned by the response of the invalidation transaction A ′ on 2.
Eventually, due to the invalidation transaction A issued to the system bus 103, the corresponding cache lines of the secondary cache memory and the primary cache memory all become invalid. When the secondary cache memory is connected to a non-pipelineable bus (non-pipelined bus), there is no other transaction on the path from the request to the response of transaction A, and coherency is guaranteed by the state transition. . In addition, local bus 1
02 in order to maintain the cache memory inclusion relationship when issuing a transaction to the transaction A ′
The state between T1 and T2 before the request is made valid.

[0003] The above-described conventional hierarchical cache memory has a state in which, in response to a non-pipeline transaction on the system bus where the lower cache memory does not hit, a transaction referring to the upper cache memory which does not hit from the inclusion relation is not issued to the local bus. A transition control method (state transition coherency control method for non-pipeline bus) is adopted.

[0004]

Since the conventional hierarchical cache memory as described above employs a state transition coherency control method for a non-pipeline bus, the lower-order cache memory is changed to a bus (pipeline bus) capable of pipeline processing. At the time of connection, there is another transaction on the bus between the request and the response of transaction A, and T1 and T1 from transaction A to A 'request.
The lower cache memory in the valid state between two hits,
There is a problem that the coherency of the cache memory in which transactions are linked between the upper and lower buses cannot be guaranteed.

[0005] The problem to be solved by the present invention is a transitional period in which the state of a cache memory connected to a pipeline bus in a hierarchical cache memory is updated so as to guarantee coherency. An object of the present invention is to provide a method for performing a state transition control so as to show a different state or not to access the cache memory only for an address being processed (state transition coherency control method for a pipeline bus).

[0006]

A hierarchical cache memory according to the present invention has a cache memory determination circuit, which receives a system bus side tag address signal and a local bus side tag address signal, According to an access direction selection signal indicating whether the access request is from the system bus or the local bus, one of the system bus side tag address signal and the local bus side tag address signal is selected as a tag address signal, Receives the bus-side index address signal and the local bus-side index address signal, and indexes one of the system bus-side index address signal and the local bus-side index address signal according to the access direction selection signal. Control signal to determine whether or not a cache hit has occurred based on the index address signal and the tag address signal, and to output a cache hit signal when a cache hit has occurred. At the timing of the invalidation transaction that invalidates the cache data line, the control that does not output the cache hit signal only for the access request generated on the system side corresponding to the cache data line ,
Local buffer in response to the invalidation transaction
When the invalidation transaction occurs in the
Even for requests access occurred in the local bus side corresponding to the cache line of data, and to perform the control that does not output the cache hit signal.

Further, the hierarchical cache memory according to the present invention has a cache memory determination circuit. The cache memory hit determination circuit receives a system bus side tag address signal and a local bus side tag address signal, and issues an access request. A first selector for outputting one of a system bus side tag address signal and a local bus side tag address signal as a tag address signal in accordance with an access direction selection signal indicating whether the signal is from the system bus or the local bus. Receiving the system bus side index address signal and the local bus side index address signal, and in accordance with the access direction selection signal, inverts either the system bus side index address signal or the local bus side index address signal. A second selector that outputs a dex address signal, a tag section having a cache state for the main memory, a reference tag address signal from the tag section according to the index address signal, a system bus side state signal and a local bus side state signal , A third selector that outputs one of a system bus side state signal and a local bus side state signal as a state signal in accordance with an access direction selection signal, and a tag address signal and a reference tag address signal. A comparator for judging whether they match or not, and outputting an address match signal if they match, and an OR gate for outputting a state valid signal only when the state signal indicates that a copy exists on the cache And address match signal and state valid According No., an AND gate for outputting a cache hit signal,
Further, the memory array may indicate that only the system bus side state signal corresponding to the cache line data is not copied on the cache at the timing when the invalidation transaction for invalidating the cache line data on the system bus occurs. And on the system bus
Row corresponding to the invalidation transaction
Time when an invalidation transaction on Calvas occurs
The local bus side state signal corresponding to the cache line data also indicates that the cache is not copied on the cache. Also, the hierarchical cache memory according to the present invention has a cache memory determination circuit, which receives a system bus side tag address signal and a local bus side tag address signal, and requests access to the system bus. A first selector for outputting one of a system bus side tag address signal and a local bus side tag address signal as a tag address signal in accordance with an access direction selection signal indicating from which side of the local bus; Receiving the side index address signal and the local bus side index address signal,
A second selector for outputting one of a system bus side index address signal and a local bus side index address signal as an index address signal in accordance with an access direction selection signal; and a cache state for the main memory and one bus side state for the other. The tag section having a flag to be corrected to the bus side state is held, a reference tag address signal is output from the tag section according to the index address signal, and the local bus side A memory array that outputs a state signal and a state correction flag signal, a state correction circuit that changes a local bus side state signal to a system bus side state signal when the state correction flag signal is ON, and an access direction selection signal ,system And a third selector that outputs one of the source-side state signal and the local bus-side state signal as a state signal, and determines whether or not the tag address signal and the reference tag address signal match. A comparator that outputs an address match signal, an OR gate that outputs a state valid signal only when the state signal indicates that a copy exists on the cache, and a cache hit signal according to the address match signal and the state valid signal. An output AND gate for outputting the state correction flag signal corresponding to the cache line data at a timing when an invalidation transaction for invalidating the cache line data occurs on the system bus. Then state
The signal should be a local bus side state signal.
Corresponds to invalidation transactions generated on the stem bus
Invalidation transaction on the local bus
At this time, the state correction flag signal corresponding to the cache line data is set to OFF, and the local bus side state signal indicates a state in which there is no copy on the cache.

The hierarchical cache memory according to the present invention has a cache memory judgment circuit, which receives a system bus side tag address signal and a local bus side tag address signal, and receives an access request from the system. A first selector for outputting either one of a system bus side tag address signal and a local bus side tag address signal as a tag address signal in accordance with an access direction selection signal indicating from which side of the bus or the local bus; The bus side index address signal and the local bus side index address signal are received, and either the system bus side index address signal or the local bus side index address signal is indexed according to the access direction selection signal. Second output as the scan address signal
A processing flag register for outputting a processing flag signal indicating that processing is being performed in the cache memory and a flag indicating that processing is being performed in the cache memory, and outputting ON as a processing flag signal when processing is being performed and OFF when processing is not being performed. An address register that holds the current address and outputs it as a processing address signal; a state register that holds the system bus side state corresponding to the address being processed and outputs it as a processing system bus side state signal; and a tag address signal And whether the index address signal matches the processing address signal, and if they match, the first comparator that outputs the processing address match signal, and the processing address match signal according to the access direction selection signal. Outputs a state register selection signal when it is present and the processing flag signal is ON. An AND gate, a memory array holding a tag unit representing a cache for the main memory, and outputting a reference tag address signal and a local bus side state signal from the tag unit according to an index address signal; a state register selection signal and a local bus side A third selector for outputting a state signal in accordance with the state signal and the system bus side state signal being processed; and determining whether or not the tag address signal and the reference tag address signal match. A comparator that outputs a signal, an OR gate that outputs a state valid signal only when the state signal indicates that a copy exists on the cache, and an AND gate that outputs a cache hit signal in accordance with the address match signal and the state valid signal And a system bus When an invalidation transaction that invalidates the cache line data occurs, the processing flag register turns on the processing flag signal corresponding to the cache line data, and stores the address corresponding to the cache line data in the address register. Is set in the state register so that only the state of the system bus corresponding to the cache line data is not copied on the cache, and the invalidation transaction generated on the system bus is set.
Invalidation transaction on local bus in response to transaction
At the timing of the occurrence of the cache line data , the memory array also causes the local bus side state signal corresponding to the cache line data to indicate that it is not copied on the cache, and the processing flag register corresponds to the cache line data. The processing flag signal is turned off. Also, the hierarchical cache memory according to the present invention has a cache memory determination circuit, wherein the cache memory hit determination circuit receives the system bus side tag address signal and the local bus side tag address signal, and the access request is issued to the system bus or the system bus. A first selector for outputting one of a system bus side tag address signal and a local bus side tag address signal as a tag address signal in accordance with an access direction selection signal indicating from which side of the local bus, and a system bus side An index address signal and a local bus index address signal are received, and one of the system bus index address signal and the local bus index address signal is indexed according to the access direction selection signal. Second output as signal
A flag indicating that processing is in progress in the cache memory, a flag indicating that processing is in progress, and outputting a flag indicating that processing is in progress. An address register that holds the address of the current address and outputs it as an address signal during processing, and has a system bus side state and a local bus side state corresponding to the address being processed, and outputs it as a system bus side state signal and a local bus side state signal A first register for determining whether the tag address signal and the index address signal match the processing address signal, and outputting a processing address match signal if they match; According to the selection signal, an address match signal is being processed, and processing is in progress. When the lag signal is ON, an AND gate that outputs a state register selection signal and a tag unit indicating a cache for the main memory are held, and a reference tag address signal and a local bus side state signal are transmitted from the tag unit according to the index address signal. A memory array to output, a third selector to output a state signal from a state register selection signal, an access direction selection signal, a processing local bus side signal, and a processing system bus side state signal; a tag address signal and a reference tag A comparator that determines whether or not the address signal matches, and outputs an address match signal if the address signal matches, and outputs a state valid signal only when the state signal indicates that a copy exists on the cache. An OR gate to output,
An AND gate that outputs a cache hit signal in accordance with the address match signal and the state valid signal;
When an invalidation transaction that invalidates cache line data occurs on the system bus, the processing flag register turns on the processing flag signal corresponding to the cache line data, and the address register corresponds to the cache line data. sets the address, the state register only the system bus side state corresponding to the cache line data, so as to represent a state that there is no duplicate on the cache, the system bus
Row in response to an invalidation transaction
Time when an invalidation transaction on Calvas occurs
In the memory array , the memory array causes the state signal indicating that the local bus side state signal corresponding to the cache line data is not copied on the cache, and the processing flag register turns off the processing flag signal corresponding to the cache line data. I tried to be.

The hierarchical cache memory according to the present invention has a cache memory determination circuit. The cache memory hit determination circuit receives a system bus side tag address signal and a local bus side tag address signal. A first selector for outputting either one of a system bus side tag address signal and a local bus side tag address signal as a tag address signal in accordance with an access direction selection signal indicating from which side of the bus or the local bus; The bus side index address signal and the local bus side index address signal are received, and either the system bus side index address signal or the local bus side index address signal is indexed according to the access direction selection signal. Second output as the scan address signal
, And a tag portion indicating the state of the cache with respect to the main memory. A reference tag address signal, a state signal, a system bus-side transaction retry flag signal, and a system bus-side tag access A memory array for outputting a retry flag signal, a local bus side transaction retry flag signal, a local bus side tag access retry flag signal, and a system bus side transaction retry flag signal and a local bus side transaction retry flag signal according to an access direction selection signal Is selected and output as the selected transaction retry flag signal, and the system bus side tag access retry flag signal and the local bus side tag access retry flag are output. And a third selector that selects one of the signals and outputs the selected tag access retry flag signal as to whether or not the tag address signal and the reference tag address signal match. A comparator that outputs a signal; an OR gate that outputs a state valid signal only when the state signal indicates that a copy exists on the cache; and a cache hit signal according to the address match signal and the state valid signal. A first AND gate that outputs a transaction retry flag signal for causing a local bus side to retry a transaction when the selected transaction retry flag signal indicates ON and an address match signal is output. AND gate and selected tag access retry flag signal ON, and a third AND gate for outputting a tag access retry flag signal for performing tag access retry when an address match signal is output. At the timing when the invalidation transaction to invalidate occurs, the memory array turns on the local bus side transaction retry flag signal corresponding to the cache line data, and sets the local bus side tag access retry flag signal corresponding to the cache line data to the ON state. Turn on,
For invalidation transactions that occur on the system bus,
Invalidation transaction on the local bus occurs in response
At this timing, the memory array turns off the local bus side transaction retry flag signal corresponding to the cache line data. Also, the hierarchical cache memory according to the present invention has a cache memory determination circuit, which receives a system bus side tag address signal and a local bus side tag address signal, and requests access to the system bus. A first selector for outputting one of a system bus side tag address signal and a local bus side tag address signal as a tag address signal in accordance with an access direction selection signal indicating from which side of the local bus; Receiving the local bus side index address signal and the local bus side index address signal, and indexing either the system bus side index address signal or the local bus side index address signal in accordance with the access direction selection signal. Processing selector, which has a second selector for outputting as a processing signal and a flag indicating that the cache memory is being processed, and outputs ON as a processing flag signal when processing is being performed and OFF when processing is not being performed. When,
An address register that holds the address of the cache memory being processed and outputs it as an address signal being processed, a system bus side transaction retry flag, a system bus side tag access retry flag, and a local bus side transaction retry corresponding to each address of the cache memory A state that has a flag and a local bus side tag access retry flag, and outputs a system bus side transaction retry flag signal, a system bus side tag access retry flag signal, a local bus side transaction retry flag signal, and a local bus side tag access retry flag signal Determines whether the register, tag address signal, and index address signal match the processing address signal, and outputs the processing address match signal if they match. A first comparator that outputs a state register selection signal in accordance with the address match signal during processing and the flag signal during processing; A memory array that outputs a reference tag address and a state signal from the tag section according to an address signal, and a transaction retry flag according to one of a system bus side transaction retry flag signal and a local bus side transaction retry flag signal according to an access direction selection signal. A third selector for outputting as a signal, outputting one of the system bus-side tag access retry flag signal and the local bus-side tag access retry flag signal as a tag access retry flag signal, and a state signal. An OR gate that outputs a state valid signal only when it indicates that a copy exists on the cache, a second AND gate that outputs a cache hit signal according to the address match signal and the state valid signal, and a selected transaction retry. When the flag signal indicates ON, the address match signal is output, and the state register selection signal is output, a third AND that outputs a transaction retry flag signal for retrying a transaction on the local bus side is output. When the gate and the selected tag access retry flag signal indicate ON, the address match signal is output, and the state register selection signal is output, the tag access retry flag signal for performing the tag access retry is output. AND gate Further, at a timing when an invalidation transaction for invalidating cache line data on the system bus occurs, the memory array may indicate that the state signal corresponding to the cache line data is not copied on the cache. The processing flag register turns on the processing flag signal corresponding to the cache line data, the address register sets the address corresponding to the cache line data, and the retry flag register stores the address of the address corresponding to the cache line data. the local bus side transaction retry flag to oN, the retry flag register is to be turned oN the local bus side transaction retry flag signal, invalidation transactions that have occurred on the system bus
Invalidation transaction on the local bus in response to the
At the timing of the occurrence of the action, the in- process flag register turns off the in-process flag signal corresponding to the cache line data.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A hierarchical cache memory according to an embodiment of the present invention has the same system configuration as that of FIG. 7A of the conventional example, as shown in FIG. 1A, as shown in FIG. 2
A next cache memory hit determination circuit is provided. The tag section of the cache memory has two upper and lower bus side states, so that the coherency of the hierarchical cache memory connected to the pipeline bus can be guaranteed. In the secondary cache memory hit determination circuit, as shown in FIG. 1B, when the selectors 1 and 2 are "1" / "0", the access direction by the access direction selection signal 15 for selecting the system bus side / local bus side is selected. , The system bus / local bus side tag address signal 11/12 and the index address signal 13/14 are selected and output as the tag address signal 16 and the index address signal 17. The memory array 3 has the same multiple copies ("S" state) as the state having different update data ("M" state) and the same multiple copies ("S" state) for the contents of the main memory. State) and a state having no copy (“I” state), and holds a tag portion of the cache memory according to the MESI protocol indicating the cache state in four states. According to the selection index address signal 17 by the selector 2, the tag address signal 18 referred to from the tag section and each of the states "M", "E", "S", and "I" are 2 bits "11".
And the system-side state signal 19 and the local bus-side state signal 20 represented by "10", "01" and "00". The comparator 4 determines whether the selected tag address signal 16 from the selector 1 matches the reference tag address signal 18 from the memory array 3, and outputs an address match signal 21 representing "1" when the tag address signal 16 matches. The selector 5 selects the system-side state signal 19 and the local bus-side state signal 20 by the memory array 3 according to the access direction by the access direction selection signal 15 and outputs it as a state signal 22. The OR gate 6 outputs a state valid signal 23 representing "1" only when the state signal 22 by the selector 5 is a valid state ("M", "E", and "S" states). When the address match signal 21 from the comparator 4 is “1” and the state valid signal 23 from the OR gate 6 is “1” (there is a cache line with the same address as the address to be accessed, and the state is valid). ), The cache hit signal 24 representing “1” is output.

The hierarchical cache memory of the above embodiment performs a state transition control so that the upper and lower buses show different states in a transition period when the state of the hierarchical cache memory connected to the pipeline bus is updated. (State transition coherency control method for pipeline bus).

In FIG. 1C, when a transaction for invalidating the cache line data in the "S" state in the secondary cache memory is issued to the system bus 103, the transaction is first performed in the memory array 3 of the secondary cache memory hit determination circuit. It is assumed that both the system and the local bus side state signals 19 and 20 are in the "S" state, and the state signal 19 is sent to the system bus side at the timing T1 when the invalidation transaction on the system bus 103 is issued. "State. At the timing T2 at which the invalidation transaction on the local bus 102 is issued, the state signal 20 is updated to the “I” state for the local bus. For the transaction of the same address issued to the system and the local bus side between timings T1 and T2, the transaction on the system bus side is the system bus side state signal 19 representing "00".
Causes a miss according to the cache hit signal 24 representing "0", and the transaction on the local bus side becomes "0".
The local bus state signal 20 representing "1" hits according to the cache hit signal 24 representing "1". At the end of the processing, both the system and the local bus side state signals 19 and 20 are in the "I" state.

In the embodiment of the present invention shown in FIG. 1A, the secondary cache memory hit judging circuit shown in FIG. 1B uses the system bus side state signal 19 by the memory array 3 as shown in FIG. In place of the above, the state correction for correcting the local bus side state to the system bus side state is configured as the memory array 3a that outputs the flag signal 25, and the state correction flag signal 25 means "ON" in the separately provided state correction circuit 8. When “1” is set to “00”, and when “0” meaning “OFF”, the local bus side state signal 20 by the memory array 3a is
A system bus side state signal 19 representing the same value as the above may be output. The tag portion of the cache memory has one bus side state and a flag for correcting the one bus side state to the other bus side state, so that the bit width of the tag portion can be reduced. In the case of FIG. 1C, it is assumed that the local bus side state signal 20 is first in the "S" state and the state correction flag signal 25 is "OFF" in the memory array 3a of the secondary cache memory hit determination circuit. Then, at the timing T1 at which the invalidation transaction on the system bus 103 is issued, the state correction flag signal 25 is turned "ON". At the timing T2 at which the invalidation transaction on the local bus 102 is issued, the local bus side state signal 20 is updated to the “I” state, and the state correction flag signal 25 is turned “OFF”.
Return to Before the timing T1, between the T1 and T2, and after the T2, the system and the local bus side state signal 1
9 and 20 have the same values as in FIG. At the end of the process, the local bus side state signal 20 is in the “I” state, and the state correction flag signal 25 is “OFF”.

In the embodiment of the invention shown in FIG. 1A, the secondary cache memory hit judging circuit shown in FIG. 1B uses the system bus side state signal 19 by the memory array 3 as shown in FIG. Memory array 3 that does not output
b, a processing flag register 111 for holding a flag indicating that the cache memory is being processed, an address register 112 for holding the processing address, and a state register 113 for holding the processing system bus side state are separately provided. , A comparator 9 provided separately and a selector 1
It is determined whether or not the tag to be accessed by the address register 2 and the index address signals 16 and 17 match the address signal 27 during processing by the address register 112, and outputs a processing address match signal 28 representing "1" when they match.
Further, in accordance with the access direction by the access direction selection signal 15 in the AND gate 10 provided separately, the in-process address coincidence signal 28 accessed from the system bus side by the comparator 9 is “1” and the in-process flag signal 26 by the in-process flag register 111 is A state register selection signal 29 representing "1" is output only when "1". Further, in accordance with the state register selection signal 29 by the AND gate 10 in the selector 5b, the system bus side state signal 30 being processed by the state register 113 and the memory array 3
b and the local bus side state signal 20 may be selected and output as the state signal 22. The tag section of the cache memory has one bus side state, and the tag external register has a processing address and the other bus side state, so that the bit width of the tag section can be further reduced. Further, it is only necessary to update the tag corresponding to one bus, and the number of times of updating the tag can be further reduced. Also, it is not necessary to refer to a tag for access from the bus side having a state in the register, and the number of times of reference to the tag can be reduced. Further, the address register 112 for holding the address being processed can be shared by the existing registers of the circuit. In the case of FIG. 1C, in the memory array 3b of the secondary cache memory hit determination circuit, first, the local bus side state signal 20 is in the "S" state, and the processing flag register 111 is "OFF". Next, the system bus 10
3. Timing T for issuing invalidation transaction on
In step 1, the processing flag register 115 is turned "ON", the transaction address is set in the address register 112, and the "I" state is set in the state register 113. At the timing T2 when an invalidation transaction on the local bus 102 is issued, the local bus side state signal 20 is updated to the “I” state, and the in-process flag register 111 is returned to “OFF”. Timing T1
Both before and after T1 and T2 and after T2, the system and local bus side state signals 19 and 20 become "00" and "01". At the end of the process, the local bus side state signal 20 is in the “I” state, and the in-process flag register 111 is “OFF”.

Also, in the embodiment of the invention shown in FIG. 1A, the secondary cache memory hit determination circuit shown in FIG. 3 receives the in-process system bus side state signal 30 by the state register 113 as shown in FIG. In addition, it is configured as a state register 113a which also outputs the local bus side state signal 31 during processing, the processing address match signal 28 accessed by the comparator 9 by the AND gate 10a is "1", and the processing flag by the processing flag register 111 A state register selection signal 29a representing "1" is output only when the signal 26 is "1". Further selector 5
In step c, the local bus side state signal 20 by the memory array 3b and the system being processed by the state register 113a and the local bus side state signals 30 and 31 according to the state register selection signal 29a by the AND gate 10a and the state direction by the access direction selection signal 15. May be selected and output as the state signal 22. The tag external register of the cache memory has the address being processed and the two upper and lower bus side states, and can respond to an access to the address being updated without waiting for the completion of the update processing (generally, a larger capacity than the register). It was necessary to store the update request in a queue until the completion of the physical update processing in the tag section of the memory array 3b using a low-speed memory, and wait for the tag reference during the update processing.
Also, in order to refer to a tag before the update processing is completed, it is necessary to perform an address comparison for confirming that a tag reference that is not being updated is not being updated. FIG. 1 (c) above
, The local bus side state signal 20 is first stored in the memory array 3b of the secondary cache memory hit determination circuit.
Is in the “S” state and the in-process flag register 111 is “OFF”.
3. Timing T for issuing invalidation transaction on
In step 1, the in-process flag register 115 is turned “ON”,
The transaction address is set in the address register 112, and the "I" and "S" states are set in the state register 113 on the system and local bus sides. At the timing T2 at which an invalidation transaction on the local bus 102 is issued,
To the “I” state, and the in-flight flag register 1
11 is returned to "OFF". Before timing T1, T1 and T
2 and after T2, and any tag access from the system bus side and the local bus side,
The state signal 22 has the same value as in FIG. At the end of the processing, the local bus side state signal 20 becomes “I”.
In the state, the in-process flag register 111 indicates “OF
F ".

In the embodiment of the invention shown in FIG. 1A, the secondary cache memory hit judging circuit shown in FIG. 1B uses the system bus of the memory array 3c in the memory array 3c as shown in FIG. State signal 22, system bus side transaction retry flag signal 32, system bus side tag access retry flag signal 33, local bus side transaction retry flag signal 34, local bus side tag instead of side state signal 19 and local bus state signal 20. An access retry flag signal 35 is output, the OR gate 6 uses the state signal 22 from the memory array 3c instead of the selector 5, and the selector 5d outputs a retry flag signal 32 from the memory array 3c according to the access direction by the access direction selection signal 15. 34 and 33 and 35 with respect to the selected output as the selected transaction retry flag signal 36 and the tag access retry flag signal 37. And AND
In the gate 7a, when the address match signal 21 by the comparator 4 is "1" and the selected transaction retry flag signal 36 by the selector 5d is "1" (there is a cache line having the same address as the address to be accessed, and it corresponds to the access direction). Only when the transaction retry flag is set), a transaction representing "1" and a retry flag signal 38 are output, and
In the D gate 7b, when the address match signal 21 from the comparator 4 is "1" and the selected tag access retry flag signal 37 by the selector 5d is "1" (there is a cache line having the same address as the address to be accessed, and The secondary cache memory hit / retry (retry) determination circuit may be configured to output the tag access retry flag signal 39 indicating “1” only when the corresponding tag access retry flag is set. Use transaction retry and tag access retry as necessary so that transaction retry is performed in cases where deadlock must be avoided, and tag access retry with a smaller performance penalty than transaction retry in other cases (Because depending on the usage, not all four flags are used, in that case, only the flags to be used need be provided.) Also, the existing circuit can share a necessary cache memory access control circuit for the same address as during a physical tag update process or during a splitting transaction of a bus having a split function.

In the hierarchical cache memory of the above-described embodiment, state transition is performed so as not to access the cache memory only for the address being processed in a transition period in which the state of the hierarchical cache memory connected to the pipeline bus is updated. A control method (pipeline bus state transition coherency method) is adopted.

In the case of FIG. 1C, the state signal 22 is first in the "S" state in the memory array 3c of the secondary cache memory hit / retry determination circuit, and the retry flag signals 32, 33, 34, and 35 are all present. "OF
F ", the state signal 22 is updated to the" I "state at the timing T1 when the invalidation transaction on the system bus 103 and the local bus 102 is issued, and the local bus side transaction retry flag signal 34 To “ON” and the timing T2
Returns the local bus side transaction retry flag signal 34 to "OFF". At the end of the process, the state signal 22 is in the "I" state, and the retry flag signals 32, 33, 34, and 35 are all "OFF".
For a transaction issued to the system bus at the same address as the transaction being processed between timings T1 and T2, a retry flag signal 38 representing "0" is generated by system bus side retry flag signals 32 and 33 representing "OFF". At 39, tag access results other than retry are made valid. At this time, the system bus side misses according to the cache hit signal 24 representing "0" in the "I" state. Further, “ON” is set for a transaction issued to the local bus having the same address as the transaction being processed between timings T1 and T2.
A transaction retry flag signal 38 representing "1" is retried for a local bus transaction by a local bus transaction retry flag signal 34 representing "1", and the tag access result other than the retry is invalidated. At this time, the transaction on the local bus side cannot access the effective cache memory due to the retry. At the timing T1, the system bus side tag access retry flag signal 32 of the memory array 3c is set to "O".
N ", the state signal 22 is updated to the" I "state at the timing T2, the system bus-side tag access retry flag signal 32 is returned to" OFF ", and the transaction on the system bus is performed between the timings T1 and T2. Control different from the above operation example may be performed so that a valid cache memory access is waited for in the access retry and a transaction on the local bus side hits.

In the embodiment of the invention shown in FIG. 1A, the secondary cache memory hit judging circuit shown in FIG. 4 uses the memory array 3d as shown in FIG.
b, a state signal 22 is output in place of the local bus side state signal 20, and the OR gate 6 uses the state signal 22 from the memory array 3d instead of the selector 5c. A system bus side transaction retry flag signal 32, a system bus side tag access retry flag signal 33, and a local bus side transaction retry flag signal 3 provided by a retry flag register 113b separately provided instead of the state register 113a.
4 and local bus side tag access retry flag signal 3
5, the selected transaction retry flag signal 36 and the selected tag access retry flag signal 37
Output as Further, only when the address match signal 21 of the comparator 4 is "1" in the AND gate 7c, the selected transaction retry flag signal 36 of the selector 5e is "1", and the retry flag valid signal 29b of the AND gate 10a is "1", "1" Is output as a transaction retry flag signal 38 representing AND
At the gate 7d, the address match signal 21 from the comparator 4 is "1", the selected transaction retry flag signal 36 from the selector 5e is "1", and the AND gate 10a.
May be configured as a secondary cache memory hit / retry determination circuit that outputs as a tag access retry flag signal 39 representing "1" only when the retry flag valid signal 29b is "1". The tag external register of the cache memory has a processing address, a transaction retry flag from the upper / lower bus side, and a tag access retry flag, and is different from the embodiment shown in FIG.
The bit width of the tag portion can be reduced, and the number of times of updating the tag can be reduced to one. Further, it is not necessary to refer to a tag for the address being processed, and the number of times of tag reference can be reduced. In the case of FIG. 1C, in the memory array 3d of the secondary cache memory hit / retry determination circuit, first, the state signal 22 is in the "S" state, and the processing flag register 111 is "OFF". The state signal 22 is updated to the “I” state at the timing T1 at which the invalidation transactions on the system bus 103 and the local bus 102 are issued, the in-process flag register 111 is turned “ON”, and the address register 1
12, the local bus side transaction retry flag signal 34 by the retry flag register 113b is set to “ON”, and the processing flag register 111 is set to “OF” at the timing T2.
F ”. At the end of the process, the state signal 22 is in the “I” state, and the in-process flag register 111 is “OFF”. The cache hit 24, the transaction retry flag signal 38, and the tag access retry flag signal 39 are the same as those in the embodiment shown in FIG. 5 regardless of the access from the system or the local bus before the timing T1, between T1 and T2, and after T2. Have the same value.

[0020]

According to the hierarchical cache memory of the present invention as described above, in the transition period for updating the state of the hierarchical cache memory connected to the pipeline bus, different states are shown in the upper and lower buses. Alternatively, since a method of performing state transition control so that the cache memory is not accessed only for the address being processed is adopted, the inclusion relationship is not applied to the non-pipeline transaction on the system bus in which the lower cache memory does not hit as in the related art. In comparison with the method of performing state transition control so as not to issue a transaction referring to the upper cache memory that does not hit from the local bus to the local bus, the tag section of the cache memory has two upper and lower bus side states and is connected to the pipeline bus. The hierarchical cache memory The effect of the following for each invention in addition can guarantee Renshi. (1) The tag portion of the cache memory has one bus side state and a flag for correcting the one bus side state to the other bus side state, so that the bit width of the tag portion can be reduced. (2) The tag section of the cache memory has one bus-side state, the address being processed and the other bus-side state in the tag external register, and the bit width of the tag section can be further reduced. Further, it is only necessary to update the tag corresponding to one bus, and the number of times of updating the tag can be further reduced. Further, it is not necessary to refer to a tag for access from a register having a state, and the number of times of reference to the tag can be further reduced. (3) The tag external register of the cache memory has a processing address and two upper and lower bus side states, and can respond to an access to the address being updated without waiting for the completion of the update processing. (4) Transaction retry is performed in cases where deadlock must be avoided, and in other cases, transaction retry and tag access retry are performed as necessary so that tag access retry with a smaller performance penalty than transaction retry is performed. (Because depending on how to use, not all four flags are used, in that case, only the flags to be used need be provided.) (5) The tag external register of the cache memory has a processing address and four subset flags, a transaction retry flag from the upper / lower bus side and a tag access retry flag as four subset flags, which is different from the embodiment corresponding to the above (4). The hit width of the tag part can be reduced,
The tag can be updated only once. Further, it is not necessary to refer to the tag for the address being processed, and the number of times of reference to the tag can be reduced.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of a hierarchical cache memory showing an embodiment of the present invention, a functional block diagram of a secondary cache memory hit determination circuit, and a timing diagram for explaining the operation of the secondary cache memory.

FIG. 2 is a functional block diagram of the secondary cache memory determination circuit showing another embodiment of the present invention.

FIG. 3 is a functional block diagram of the secondary cache memory determination circuit showing another embodiment of the present invention.

FIG. 4 is a functional block diagram of the secondary cache memory determination circuit showing another embodiment of the present invention.

FIG. 5 is a functional block diagram of the secondary cache memory hit / retry determination circuit showing another embodiment of the present invention.

FIG. 6 is a functional block diagram of the secondary cache memory hit / retry determination circuit showing another embodiment of the present invention.

FIG. 7 is a system configuration diagram of a hierarchical cache memory showing a conventional technique and a timing diagram for explaining the operation of the secondary cache memory.

[Explanation of symbols]

1 selector, 2 selector, 3, 3a, 3b, 3c,
3d memory array, 4 comparators, 5, 5a, 5b, 5
c, 5d, 5e selector, 6, 6a OR gate,
7, 7a, 7b, 7c, 7d, 7e AND gate, 8
State correction circuit, 9 comparator, 10, 10a AN
D gate, 11 System bus side tag address signal, 1
2 Local bus side tag address signal, 13 System bus side index address signal, 14 Local bus side index address signal, 15 Access direction selection signal, 16 Selected tag address signal, 17 Selected index address signal, 18 Reference tag address signal, 19
System bus side state signal, 20 local bus side state signal, 21 address match signal, 22 state signal, 23 state valid signal, 24 cache hit signal, 25 state modification flag signal, 26 processing flag signal, 27 processing address signal, 28 Address match signal during processing, 29, 29a State register selection signal, 29b Retry flag enable signal, 30 Processing system bus side state signal, 31 Processing local bus side state signal, 32 System bus side transaction retry flag signal, 33 System Bus-side tag access retry flag signal, 34 Local bus-side transaction retry flag signal, 35 Local bus-side tag access retry flag signal, 36 Selected transaction retry flag signal, 37 selected Tag access retry flag signal, 38 transaction retry flag signal, 39 tag access retry flag signal, 111 processing flag register, 112 address register, 113, 113a state register, 1
13b Retry flag register. In the drawings, the same reference numerals indicate the same or corresponding parts.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/08 G06F 15/16-15/177

Claims (7)

(57) [Claims] 1. An upper cache memory and a lower cache
Memory and the cache provided in the lower cache memory.
And a flash memory hit determination circuit.
Update the state of the lower cache memory
Different states for the upper and lower buses during the transition period
Hierarchical cache memory for state transition control
The cache memory determination circuit receives the system bus side tag address signal and the local bus side tag address signal, and according to an access direction selection signal indicating whether the access request is from the system bus or the local bus. Selecting one of the system bus side tag address signal and the local bus side tag address signal as a tag address signal, receiving the system bus side index address signal and the local bus side index address signal, and according to the access direction selection signal. One of the system bus-side index address signal and the local bus-side index address signal is selected as an index address signal, and is selected based on the index address signal and the tag address signal. And determines whether or not a cache hit has occurred, and in the event of a cache hit, controls to output a cache hit signal. Further, an invalidation transaction that invalidates a cache data line on the system bus has occurred. At the timing, only the access request generated on the system side corresponding to the cache data line is controlled not to output the cache hit signal, and the system bus is controlled.
The log corresponding to the invalidation transaction that occurred above
Local bus where the invalidation transaction occurred
In timing, even for requests of access that occurred in the local bus side corresponding to the cache line of data, the hierarchical cache memory and performing control not to output cache hit signal. 2. An upper cache memory and a lower cache.
Memory and the cache provided in the lower cache memory.
And a flash memory hit determination circuit.
Update the state of the lower cache memory
Different states for the upper and lower buses during the transition period
Hierarchical cache memory for state transition control
The cache memory hit determination circuit receives a system bus side tag address signal and a local bus side tag address signal, and an access direction selection signal indicating whether the access request is from the system bus or the local bus. Output one of the system bus side tag address signal and the local bus side tag address signal as a tag address signal according to
And a system bus side index address signal and a local bus side index address signal, and according to the access direction selection signal, either one of the system bus side index address signal and the local bus side index address signal is indexed. A second selector for outputting a signal, a tag section having a cache state for the main memory, and a reference tag address signal, a system bus side state signal and a local bus side state signal from the tag section according to the index address signal And a third cell that outputs one of the system bus side state signal and the local bus side state signal as a state signal in accordance with the access direction selection signal. A comparator that determines whether or not the tag address signal and the reference tag address signal match, and outputs an address match signal if the tag address signal and the reference tag address signal match; and a copy of the state signal exists on the cache. And an AND gate that outputs a cache hit signal in accordance with the address match signal and the state valid signal. The memory array further comprises: At the timing when the invalidation transaction for invalidating the cache line data on the system bus occurs, only the system bus side state signal corresponding to the cache line data,
A state is assumed that there is no copy on the cache, and the invalidation transaction generated on the system bus is represented.
Invalidation transaction on local bus corresponding to transaction
At a timing action occurs, the local bus side state signal corresponding to the cache line data
Also, the hierarchical cache memory, characterized in that to represent the state that there is no copy on the cache. 3. An upper cache memory and a lower cache.
Memory and the cache provided in the lower cache memory.
And a flash memory hit determination circuit.
Update the state of the lower cache memory
Different states for the upper and lower buses during the transition period
Hierarchical cache memory for state transition control
The cache memory hit determination circuit receives a system bus side tag address signal and a local bus side tag address signal, and an access direction selection signal indicating whether the access request is from the system bus or the local bus. Output one of the system bus side tag address signal and the local bus side tag address signal as a tag address signal according to
And a system bus side index address signal and a local bus side index address signal, and according to the access direction selection signal, either one of the system bus side index address signal and the local bus side index address signal is indexed. A second selector that outputs the signal as a signal, and a tag unit having a cache state for the main memory and a flag that corrects one bus side state to the other bus side state, and stores the tag unit according to the index address signal. A memory array that outputs a reference tag address signal, and outputs a local bus side state signal and a state correction flag signal by referring to a state of a cache included in the tag unit and the flag; Is ON, a state correction circuit for changing a local bus side state signal to a system bus side state signal; and one of the system bus side state signal and the local bus side state signal according to the access direction selection signal. A third selector that outputs whether or not the tag address signal and the reference tag address signal match, and outputs an address match signal if the tag address signal and the reference tag address signal match; An OR gate that outputs a state valid signal only when the signal indicates that a copy exists on the cache; and an AND gate that outputs a cache hit signal according to the address match signal and the state valid signal, Further, the memory array is provided with a cache line data on a system bus. At a timing invalidate transaction occurs to disable the data, the state signal state correction flag signal corresponding to the cache line data is set to be in the ON state the local bus side state signal
Signal on the system bus.
Nothing on the local bus in response to an invalidation transaction
At the time when the validation transaction occurs, the state correction flag signal corresponding to the cache line data is turned off, and the local bus side state signal indicates a state where there is no copy on the cache. A hierarchical cache memory. 4. An upper cache memory and a lower cache
Memory and the cache provided in the lower cache memory.
And a flash memory hit determination circuit.
Update the state of the lower cache memory
Different states for the upper and lower buses during the transition period
Hierarchical cache memory for state transition control
The cache memory hit determination circuit receives a system bus side tag address signal and a local bus side tag address signal, and an access direction selection signal indicating whether the access request is from the system bus or the local bus. Output one of the system bus side tag address signal and the local bus side tag address signal as a tag address signal according to
And a system bus side index address signal and a local bus side index address signal, and according to the access direction selection signal, either one of the system bus side index address signal and the local bus side index address signal is indexed. A second selector for outputting a signal as a signal and a flag indicating that the cache memory is being processed, and a processing flag register for outputting ON as a processing flag signal when processing is being performed and OFF when processing is not being performed; An address register that holds the address being processed of the cache memory and outputs it as an address signal being processed; and a system bus side state corresponding to the address being processed is output as a state signal on the system bus side being processed. To And Torejisuta, the tag address signal and the index address signal, to determine whether it matches to the processing in the address signal, the first outputs the processing in the address matching signal when a match
And the in-process address match signal is present in accordance with the access direction selection signal, and the in-process flag signal is turned on.
And outputs a state register selection signal in the case of
A gate, a memory array holding a tag unit representing a cache for a main memory, and outputting a reference tag address signal and a local bus side state signal from the tag unit according to the index address signal; A third selector for outputting a state signal in accordance with the bus side state signal and the processing system bus side state signal; determining whether the tag address signal and the reference tag address signal match; Is a comparator that outputs an address match signal; an OR gate that outputs a state valid signal only when the state signal indicates that a copy exists on the cache; AND gate that outputs a cache hit signal The processing flag register turns on a processing flag signal corresponding to the cache line data at a timing when an invalidation transaction for invalidating cache line data occurs on the system bus. The address register is set to an address corresponding to the cache line data, and the state register represents a state in which only the system bus side state corresponding to the cache line data is not copied on the cache. And the system
In response to the invalidation transaction that occurred on the
The source of the invalidation transaction on the local bus.
In timing, said memory array, said local bus side state signal corresponding to the cache line data
A cache flag indicating that there is no copy on the cache, and the processing flag register turns off a processing flag signal corresponding to the cache line data. 5. An upper cache memory and a lower cache
Memory and the cache provided in the lower cache memory.
And a flash memory hit determination circuit.
Update the state of the lower cache memory
Different states for the upper and lower buses during the transition period
Hierarchical cache memory for state transition control
The cache memory hit determination circuit receives a system bus side tag address signal and a local bus side tag address signal, and an access direction selection signal indicating whether the access request is from the system bus or the local bus. Output one of the system bus side tag address signal and the local bus side tag address signal as a tag address signal according to
And a system bus side index address signal and a local bus side index address signal, and according to the access direction selection signal, either one of the system bus side index address signal and the local bus side index address signal is indexed. A second selector that outputs a signal as a signal, and a processing flag register that has a flag indicating that the cache memory is being processed, outputs ON as a processing flag signal when processing is being performed, and outputs OFF when processing is not being performed. An address register for holding an address being processed in the cache memory and outputting it as an address signal being processed; a system bus side state and a local bus side state corresponding to the address being processed; A state register for outputting a signal and a local bus-side state signal; and determining whether the tag address signal and the index address signal match the processing address signal. A first comparator that outputs a state register selection signal when the processing-in-progress address signal is present and the processing-in-progress flag signal is ON according to an access direction selection signal; A memory array that holds a tag unit representing a cache for a memory and outputs a reference tag address signal and a local bus side state signal from the tag unit according to the index address signal; and the state register selection signal and the access direction selection signal. The processing local bus side state signal A third selector for outputting a state signal from the state signal on the system bus side during processing; determining whether the tag address signal matches the reference tag address signal; A comparator that outputs a state valid signal only when the state signal indicates that a copy exists on a cache; and a cache hit signal according to the address match signal and the state valid signal. And an AND gate for outputting, and when the invalidation transaction for invalidating the cache line data occurs on the system bus, the in-process flag register turns on the in-process flag signal corresponding to the cache line data. And the address register is the cache Set the address corresponding to the in-data, only the system bus side state corresponding to the cache line data to the state register, and to represent the state that there is no copy on the cache, occurring on the system bus The nullifying transaction
Invalidation transaction on the local bus in response to the
At the timing when the connection occurs, the memory array stores the local bus side state corresponding to the cache line data.
In this case, the in-flight flag register indicates a state in which the in-flight flag signal corresponding to the cache line data is set to O.
A hierarchical cache memory characterized in that the cache memory becomes an FF. 6. An upper cache memory and a lower cache
Memory and the cache provided in the lower cache memory.
And a flash memory hit determination circuit.
Update the state of the lower cache memory
Different states for the upper and lower buses during the transition period
Hierarchical cache memory for state transition control
The cache memory hit determination circuit receives a system bus side tag address signal and a local bus side tag address signal, and an access direction selection signal indicating whether the access request is from the system bus or the local bus. Output one of the system bus side tag address signal and the local bus side tag address signal as a tag address signal according to
And a system bus side index address signal and a local bus side index address signal, and according to the access direction selection signal, either one of the system bus side index address signal and the local bus side index address signal is indexed. A second selector that outputs the signal as a signal, and a tag unit that indicates a cache state for the main memory;
A reference tag address signal, a state signal, a system bus side transaction retry flag signal, a system bus side tag access retry flag signal, a local bus side transaction retry flag signal, a local bus side A memory array for outputting a tag access retry flag signal, and selecting one of the system bus side transaction retry flag signal and the local bus side transaction retry flag signal according to an access direction selection signal and outputting as a selected transaction retry flag signal Then, one of the system bus-side tag access retry flag signal and the local bus-side tag access retry flag signal is selected to perform the selected tag access retry. A third selector that outputs a flag signal, a comparator that determines whether the tag address signal matches the reference tag address signal, and outputs an address match signal if the tag address signal and the reference tag address signal match; An OR gate that outputs a state valid signal only when it indicates that a copy exists on the cache, and according to the address match signal and the state valid signal,
A first AND gate for outputting a cache hit signal; and a transaction retry flag for retrying a transaction on the local bus side when the selected transaction retry flag signal indicates ON and the address match signal is output. A second AND gate that outputs a signal, and when the selected tag access retry flag signal indicates ON and the address match signal is output,
A third AND gate for outputting a tag access retry flag signal for performing a tag access retry, and further comprising, at a timing when an invalidation transaction for invalidating cache line data on a system bus occurs, the memory array: The local bus-side transaction retry flag signal corresponding to the cache line data is turned on, and the local bus-side tag access retry flag signal corresponding to the cache line data is turned on.
On the local bus in response to the invalidation transaction
Wherein the memory array turns off a local bus-side transaction retry flag signal corresponding to the cache line data at the timing when the invalidation transaction occurs . 7. An upper cache memory and a lower cache
Memory and the cache provided in the lower cache memory.
And a flash memory hit determination circuit.
Update the state of the lower cache memory
Different states for the upper and lower buses during the transition period
Hierarchical cache memory for state transition control
The cache memory hit determination circuit receives a system bus side tag address signal and a local bus side tag address signal, and an access direction selection signal indicating whether the access request is from the system bus or the local bus. Output one of the system bus side tag address signal and the local bus side tag address signal as a tag address signal according to
And a system bus side index address signal and a local bus side index address signal, and according to the access direction selection signal, either one of the system bus side index address signal and the local bus side index address signal is indexed. A second selector that outputs a signal as a signal, and a processing flag register that has a flag indicating that the cache memory is being processed, outputs ON as a processing flag signal when processing is being performed, and outputs OFF when processing is not being performed. An address register that holds a processing address of the cache memory and outputs the address as a processing address signal; a system bus side transaction retry flag and a system bus side tag access corresponding to each address of the cache memory; It has a retry flag, a local bus-side transaction retry flag, and a local bus-side tag access retry flag. The system bus-side transaction retry flag signal, the system bus-side tag access retry flag signal, the local bus-side transaction retry flag signal, and the local bus side A state register that outputs a tag access retry flag signal, and a second register that determines whether the tag address signal and the index address signal match the processing address signal, and outputs a processing address match signal if they match. 1
And a first A that outputs a state register selection signal according to the in-process address match signal and the in-process flag signal.
An ND gate, a memory array for holding a tag unit indicating a cache state for a main memory, and outputting a reference tag address and a state signal from the tag unit according to the index address signal; One of the system bus side transaction retry flag signal and the local bus side transaction retry flag signal is output as a transaction retry flag signal, and either the system bus side tag access retry flag signal or the local bus side tag access retry flag signal is output. A third selector that outputs one of them as a tag access retry flag signal, and outputs a state valid signal only when the state signal indicates that a copy exists on the cache. And R gate, the address match signal in accordance with the state valid signal,
A second AND gate for outputting a cache hit signal; and when the selected transaction retry flag signal indicates ON, the address match signal is output, and the state register selection signal is output, Third A for outputting a transaction retry flag signal for causing a transaction to be retried
When the selected tag access retry flag signal indicates ON, the address match signal is output, and the state register selection signal is output, a tag access retry flag signal for performing tag access retry is output. A fourth AND gate for outputting, and at a timing when an invalidation transaction for invalidating cache line data occurs on the system bus, the memory array outputs a state signal corresponding to the cache line data. The cache flag indicates that there is no copy on the cache, the processing flag register turns on a processing flag signal corresponding to the cache line data, and the address register stores an address corresponding to the cache line data. And set The retry flag register turns on the local bus-side transaction retry flag of the address corresponding to the cache line data, the retry flag register turns on the local bus-side transaction retry flag signal, and the system bus.
In response to the invalidation transaction that occurred on the
The source of the invalidation transaction on the local bus.
2. The hierarchical cache memory according to claim 1 , wherein the in-process flag register turns off the in-process flag signal corresponding to the cache line data at the time of imaging .