JP3290141B2 - Video coding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

Although lower prices of the memory BACKGROUND OF THE INVENTION are rapidly, the ratio of the video data storage device that put the video encoding apparatus still greater. This is because the amount of video data is generally very large. The present invention relates to a technique for minimizing the storage capacity of a video data storage device in the video encoding device .

[0002]

2. Description of the Related Art With the spread of DVD, video communication, etc.,
Among video data processing apparatuses, economical use of video coding apparatuses is becoming more and more important. Here, a description will be given of a reduction in the storage capacity of the video data storage device in the video encoding device , which is effective for economy.

In the current mainstream video encoding algorithms such as MPEG1 and MPEG2, the encoding order in which the P period (M) of the motion prediction mode of the frame is BBIBPBPBP in the order of 3 is the mainstream. It has become.
Here, I represents a coded frame without motion prediction, P represents a coded frame for forward prediction, and B represents a coded frame for bidirectional prediction. In this encoding order algorithm,
Conventionally, storage areas for at least two local reproduction frames and four original frames have been required. The reasons for this are listed below.

(1) In encoding an original frame corresponding to B, it is necessary to refer to a local reproduction frame corresponding to the P encoded frame located before and after the original frame. The frame must be held in the encoding device.

(2) The encoding of the original frame corresponding to P must precede the encoding of the original frames corresponding to the two Bs located immediately before and another immediately before in the input order of the original frame. Therefore, at the time of encoding the original frame corresponding to P, it is necessary to hold the previous two original frames corresponding to B. Further, when an original frame corresponding to P is encoded, an original frame corresponding to B located next to the original frame in the order of input of the original frame comes in, and it is necessary to hold it together. When these two conditions are matched, it is necessary to hold four original frames.

FIG. 3 shows the allocation order of original frames when encoding is performed with an appearance cycle M = 3 of I or P using a storage area for four frames. Where I, B, P
Indicates the prediction type of the frame. Also, ()
This is the time sequence of the original frame, and t is time. The points of allocation shown in this figure are (1) not only the original frame input order but also I (2), B (0), B (B) before the two B frames preceding I or P frame.
(1), P (5), B (3), B (4), P (8), B
(6), B (7), P (11),...,..., (2) Frame input is performed on a vacant area after processing. It is. In this figure, the hatched portion indicates that encoding is being performed, and the halftone dot portion indicates that input is being performed.

FIG. 4 is a block diagram of a conventional video data storage device in which original frames can be allocated to the storage area. Here, the video input unit 101
This is a functional block that generates an address of a storage destination of a pixel data input based on vertical and horizontal synchronization signal inputs. On the other hand, the video output unit 201 receives a frame update request, a field even / odd, an in-field address signal, etc.
This is a functional block that generates a read destination address and outputs the read data as pixel data. The memory interface 60 is a functional block for generating a control signal for reading and writing, an address, and the like according to characteristics of the memory 70 to be used. Inside 101 and 201, the start address for each field generated by the field storage destination start address generator 32 or the in-field read destination start address generator 33, and the in-field address generated by the in-field address generator 22 or input from the outside. Are added by the adder 52 or 53 to the head address of.

[0008]

As described above, in the prior art, in order to realize a motion prediction of M = 3, a storage area for four original frames was required. However, in order to reduce the cost of the memory, it is desirable that this storage area can be reduced even slightly.

An object of the present invention is to provide a video encoding apparatus that reduces the number of stored original frames.

[0010]

In order to solve the above problems, the present invention encodes an original frame using motion estimation.
A video encoding apparatus that can store one original frame including an odd field and an even field, and
A memory capable of securing a plurality of original frame storage areas having four divided areas of B, C, and D; and storing an original frame in one of the plurality of original frame storage areas,
Means for fixedly storing the first half of the odd field and the second half of the even field in the partition areas A and D, respectively, and the second half of the odd field data and the first half of the even field data, or stored in C, or stored in the partitioned area C and B in reverse, and a means that stores switch each time to store the new original frame in each of the plurality of original frame storage area, New entry
When the input original frame is input at the start of the input original frame,
Original frame storage where the original frame being encoded is stored
Overwrite area from the end of encoding
The above-mentioned storage is performed .

Alternatively, the original frame is
In a video encoding apparatus that encodes a field, a storage area for one original frame composed of an odd field and an even field is divided into four equal areas A, B, C, and D in ascending order of address. A memory capable of securing a plurality of original frame storage areas, a means for generating an even / odd designation signal for distinguishing between an odd field and an even field based on a vertical synchronization signal, and distinguishing between a first half and a second half of a field based on a horizontal synchronization signal Means for generating an in-field address to obtain;
When the even / odd designation signal indicates an odd field, the head address of the partitioned area A is generated as a field storage destination head address. When the even / odd designation signal indicates an even field, the head address of the partitioned area C is generated as a field storage destination head address. Means for generating an offset value of zero when the even / odd designation signal indicates an odd field and the address in the field indicates the first half, or when the even / odd designation signal indicates an even field and the address in the field indicates the second half. When the even / odd designation signal indicates an odd field and the address in the field indicates the second half, or when the even / odd designation signal indicates an even field and the address in the field indicates the first half,
Zero necessary for the second half of the odd field to be the first address of the partitioned area B or zero for the first half of the even field to be the first address of the partitioned area C Is generated, the offset value required for the second half of the odd field to be the first address of the storage area or the first half of the even field is the same as the first half of the storage area. Means for switching between a case where an offset value required to become the head address of the area B is generated and each time a new original frame is stored in each of the plurality of original frame storage areas; by adding said offset value and the field address, means for generating a storage destination address of the original frame It has an original frame newly input
Is the original frame being encoded at the start of the input of the original frame.
Encoding of the original frame storage area where the
Generated storage to overwrite from the end of
The storage is performed at the destination address .

According to the present invention, each of the even and odd fields constituting the frame is divided into upper and lower fields, and each is divided and stored in an area where processing (encoding) is completed and which can be overwritten. Thus, the storage area for one frame is reduced. Specifically, (1) the storage area for one frame is divided into four divided areas A, B, C, and D. (2) For A and D in the divided areas, the first half of the odd field is A
, The latter half of the even field is fixedly assigned to B,
(3) Regarding B and C in the divided areas, each time a new frame is stored, the second half of the odd field data and the first half of the even field data are stored in B and C (referred to as a normal mode) or C. , B (half-half mode) is alternately switched.

By these three methods, the upper or lower side of the even or odd field of the newly input original frame is stored in the frame storage area being coded from the part where the coding has been completed. Is reduced by one sheet.

FIG. 2 shows B (0), B (1), I (2),
B (3), B (4), P (5), B (6), B (7),
FIG. 4 is a diagram showing the order in which original frames input in the order of P (8)... Are allocated to storage areas for three frames reduced by one from FIG.

Each storage area has four more areas A, B,
C and D are stored, and the first half or the second half of the field constituting the frame is stored in each. Subscript O
U, OL, EU, and EL represent the upper half and lower half of the odd field and the upper half and lower half of the even field, respectively. In the encoding of a frame structure that is currently mainstream, processing is performed on a frame basis. That is,
First, the upper half of the odd field and the upper half of the even field are encoded, and then the lower half of the odd field and the lower half of the even field are encoded. As shown in FIG. 2, the upper half and the lower half are stored for each field from the region where the encoding is completed and which can be overwritten.
A normal mode pattern in which odd fields are assigned to the divided areas A and B and an even field is assigned to the divided areas C and D, and a half-mode pattern in which odd fields are assigned to the divided areas A and C and even fields are assigned to the divided areas B and D. Are alternately switched. According to the present invention, such switching is performed by dividing the storage area for one frame into four areas in address order.
Area, and A, B, C, D
This is realized by switching the offset value to be added depending on whether the field is even or odd and the first half or the second half of the field when the address is generated.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[0017] Figure 1 is a block diagram of an embodiment of the present invention, using the motion prediction in video coding device
The original frame that is input to perform the encoding
2 shows a configuration of a video data storage device. Figure 1
Te, 100 denotes a video input unit, 200 video output unit, 60 is a memory interface, 70 is a memory. Also, 1
00 is composed of functional blocks such as 10, 20, 30, 50 and the like, and 200 is composed of functional blocks such as 21, 31, 41 and 51. Here, 10 is a field even-odd generation unit,
Reference numeral 20 denotes an in-field address generation unit, 21 denotes a field first / second half generator, 30 denotes a field storage destination start address generator, 31 denotes a field read destination start address generator, 40 and 41 denote offset generators, and 50 and 51 denote additions. It is a vessel. Hereinafter, the operation of the present embodiment will be described.

The video input unit 100 generates a write address necessary for storage in a normal mode or a half-split mode from a vertical and horizontal synchronization signal input from the outside together with pixel data. The video output unit 200 is required to read the original frame pixel data stored in the normal mode or the half mode from the externally supplied frame update request, the field even / odd, and the address in the field.
Generate a read address. Memory interface 6
0 generates control signals and address signals such as CAS (column address strobe), RAS (row address strobe), write enable, and read enable according to the memory to be used, and supplies them to the memory 70.

Inside the video input unit 100, a write address corresponding to switching between the normal mode and the half mode is generated as follows each time each storage area of the original frame is stored again in a new frame.

The field even / odd generator 10 receives a vertical synchronization signal input from the outside, generates a field even / odd designation signal, and generates an in-field address generator 20, a field storage destination head address generator 30, and an offset generator 4.
Output to 0.

The in-field address generator 20 receives the field even / odd designating signal from the field even / odd generator 10 and an externally input horizontal synchronizing signal, generates an address for storing pixel data, and outputs the address to the adder 50. I do.
Specific internal functions start at 0 at the beginning of the field
Next, one pixel per effective pixel input in the raster scanning order
By incrementing the address in the field by one
Generate an in-field address. Where the field
The even / odd designation signal is used to detect the beginning of the field.
The signal is used for detecting the head of the line, and the input image is
Proper addresses for valid images are generated even if slightly disturbed.
To be At the same time, whether the first half or the second half of the field is obtained is output to the offset generator 40 as the first half / second half signal. The address in the field is the field
If the length is 2L, it becomes 0-2L-1. A in the field
If the dress is 0 to L-1, the first half signal is L to 2L-1.
If so, the latter half signal is output.

Field storage destination start address generator 30
Generates the start address of the storage destination for each field from the field even / odd designation signal from the field even / odd generator 10 and outputs the generated address to the adder 50, and also outputs the normal mode / half-half mode designation signal for each field to its storage area. Is generated so that it is inverted each time it is stored again in a new frame, and is output to the offset generator 40. The head address generated here is a head address of one of the A and C divided areas of the three original frame storage areas shown in FIG. Access the B, C, and D partitioned areas of the original frame storage area.
The start address at the time of access is generated by adding the output of the in-field address generator 20 and the output of the offset generator 40 to the start address of the A and C partitioned areas as described below. When all offset values are 0
The, had there A is the leading address of (1) Field storage location
Indicates the start address of the segmented area C in the raster scanning order.
In-field address to be incremented (field length
Is 2L, the first half: 0 to L-1, the second half: L to 2L-
1) is added to the write address for the input field.
Is generated. (2) One storage area of the original frame is divided into four equal parts, and
The divided areas are A, B, C, and D in order from the smallest dress.
ing. Assuming that the field length is 2L, the divided area A,
Areas B, C, and D each have an area length of L. this
With the two, the odd address starts from the start address of the partitioned area A.
The first half of the field is stored in section A and the second half in section B
Even field starting from the start address of the segmented area C
The first half is divided into the divided area C, and the second half is divided into the divided area D.
Will be delivered. When M = 3, the allocation order of the original frames, which is the basis of the generation order of the head address of the storage destination for each field, is such that, as shown in FIG. It is made to correspond to the order of encoding to be processed first. In the offset generator 40, the first half of the odd field and the second half of the even field are fixedly stored in the divided areas A and D, respectively, and the second half of the odd field data and the first half of the even field data are respectively stored in the normal mode. To the divided areas B and C, and to the divided area C in the half-and-half mode
And the offset required to store the data in B in accordance with the normal mode / half-mode designation signal from the field storage destination start address generator 30 as follows.

When the normal mode is designated: Regardless of whether the field is even or odd or the first and second half of the field (either the field even / odd designation signal from the field even / odd generator 10 or the field first / second half signal from the intra-field address generator 20) independently), the offset to generate a 0
You .

In the case where the half-and-half mode is designated: when the second half of the odd field is designated by the field even / odd designation signal from the field even / odd generator 10 and the first / second field signal from the in-field address generator 20 When the first half of the even field is specified in the area C, an offset necessary for moving the storage destination from the normal mode storage area is generated so as to be stored in the divided area B, respectively. That is, assuming that the area length of a half of the field is L, when the latter half of the odd field is designated, +
When the offset of the value of L is designated as the first half of the even field, the offset of the value of -L is generated. For the other half of the odd field and the latter half of the even field, the storage area is the same as in the normal mode, and the offset is 0.

The adder 50 generates a write address corresponding to switching between the normal mode and the half-mode by adding the outputs of the intra-field address generator 20, the field storage destination head address generator 30, and the offset generator 40. I do.

Inside the video output unit 200, a read address corresponding to switching between the normal mode and the half-mode is generated as follows.

The field read destination head address generator 31 generates a field read destination start address from two signals, ie, a frame update request input from the outside and a field even / odd designation signal, and outputs it to the adder 51. Further, in addition to this output, a normal mode / half-mode designation signal determined for each field is generated and output to the offset generator 41. Here, when M = 3, the allocation order of the original frames which is the basis of the generation order of the read destination head address is as shown in FIG. Further, the generation of the normal mode / half-half mode designation signal is performed such that the signal is inverted each time a new frame is read from each storage area. The field first / second half generator 21 generates a field first / second half signal from an externally input in-field address signal and outputs the signal to the offset generator 41. The offset generator 41 designates the case where the half mode is designated by the normal mode / half mode designation signal from 31. The second half of the odd field is designated by the field even / odd designation signal from the outside and the first / last field signal from 21. If so: Generate an offset (+ L) necessary for movement from the divided area B, which is a storage area in the normal mode, so as to be read from the divided area C.

When the first half of the even field is designated by the field even / odd designation signal from the outside and the first / second field signal from the first / second address generator 21: storage in the normal mode so as to be read out from the divided area B An offset (-L) required for movement from the divided area C, which is an area, is generated.

In other cases, the offset is 0 so that the first half of the odd field is read from the partitioned area A, the second half is read from the partitioned area B, the first half of the even field is read from the partitioned area C, and the second half is read from the partitioned area D. Generate

The adder 51 includes a first-half / second-half field generator 21 and a field-reading-first address generator 3.
1. A read address corresponding to switching between the normal mode and the half-split mode is generated by adding the signals of the offset generator 41.

According to the above-described operation, in the present embodiment, the normal mode and the half mode access to the storage area of the original frame become possible, so that the storage area of the original frame required for encoding can be reduced to three frames. become.

In the above embodiment, the case where M = 3 has been described as an example, but the present invention is not limited to this. In short, it is sufficient to prepare a memory that can secure M number of original frame storage areas.

As described above, in the present embodiment,
Conventionally, the storage area of the original frame, which required a storage area for four frames to encode a video when M = 3, is reduced to three frames. In the video data of the PAL / 4: 2: 0 format, the data amount for one frame is about 5 Mbits, and the storage capacity is reduced accordingly.

Conventionally, to configure a video encoding device , a storage capacity of 5 M × 6 = 30 M bits was required only for storing the current frame and the reproduced image. To improve image quality, it is effective to insert an inter-frame difference suppression filter into the input unit. For this purpose, an additional 5 Mbits and a total of 35 Mbits are used.
A bit needed. However, in order to secure this storage capacity, three 16-M DRAMs with the lowest bit unit cost are currently required.

On the other hand, if the present invention is applied, 5M
The number of bits is reduced to 30 Mbits, and two 16 MDRAMs can cover all the storage capacity required for encoding and the inter-frame difference suppression filter. As described above, the present invention is extremely effective for economical use of a video encoding device .

[0036]

[0037]

As is apparent from the above description, according to the present invention, the storage area of the original frame required for the conventional video encoding can be reduced by one frame. For this reason, it is very effective in economicalizing the video encoding device .

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing the order of allocation of original frames when storage areas for three frames are used for storing original frames in the embodiment.

FIG. 3 is a diagram showing the assignment order of original frames when a storage area for four frames is used for storing original frames in the related art.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Field even-odd generator 20 ... In-field address generator 21 ... Field first / second half generator 30 ... Field storage destination head address generator 31 ... Field read destination head address generator 40, 41 ... Offset generator 50, 51 ... Adder 60 ... Memory interface 70 ... Memory 100 ... Video input unit 200 ... Video output unit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-8-107482 (JP, A) JP-A-8-18953 (JP, A) JP-A-9-37265 (JP, A) JP-A-9-1997 37267 (JP, A) JP-A-9-214956 (JP, A) JP-A-10-93909 (JP, A) Ishiwatari, Kitagaki, Demura, Otomo, Michinaka, Fuji, Development of MPEG2 decoder LSI-Efficient Memory allocation, Proc. Of the 1994 IEICE Spring Conference, Japan, March 10, 1994, Volume 5, p. 227 Takahata, Uramoto, Tanaka, Yoshimoto, DRAM Interface in MPEG2 Video Decoder LSI, Proceedings of the 1995 IEICE General Conference, Electronics 2, Japan, March 10, 1995, p. 179 (58) Surveyed field (Int.Cl. ⁷ , DB name) H04N ^7/ 24-7/68 JICST file (JOIS)

Claims (2)

(57) [Claims] 1. Encoding an original frame using motion prediction
A plurality of original frame storage areas capable of storing one original frame composed of an odd field and an even field and having four divided areas of A, B, C, and D are secured in the video encoding apparatus. Means for storing an original frame in one of the plurality of original frame storage areas, and fixedly storing the first half of the odd field and the second half of the even field in the divided areas A and D, respectively. The plurality of original frame storage areas determine whether the second half of the odd field data and the first half of the even field data are stored in the divided areas B and C or conversely, stored in the divided areas C and B, respectively. and means that stores switch each for storing a new original frame in each of the original frame newly inputted, the input opening of the raw frame
The original frame containing the original frame being encoded at the beginning
Overwrites the storage area with the end of encoding
It said storage image encoding <br/> apparatus characterized that you perform to. 2. An original frame is encoded using motion estimation.
In the video encoding apparatus, the storage area for one original frame including the odd field and the even field is stored in the order of A, B, C,
A memory capable of securing a plurality of original frame storage areas having four equally divided areas, a means for generating an even / odd designation signal for distinguishing between an odd field and an even field based on a vertical synchronization signal, and a horizontal synchronization signal Means for generating an in-field address capable of distinguishing between the first half and the second half of the field based on the following: when the even / odd designation signal indicates an odd field, generates a head address of the partitioned area A as a field storage destination head address; Means for generating the start address of the partitioned area C as a field storage start address when the even / odd designating signal indicates an even field; and when the even / odd designating signal indicates an odd field and the address in the field indicates the first half, or When the designated signal indicates an even field and the address in the field indicates the latter half Generates an offset value of zero, and when the even / odd designation signal indicates an odd field and the address in the field indicates the second half, or when the even / odd designation signal indicates an even field and the address in the field indicates the first half, Necessary for the storage destination top address of the latter half of the odd field to be the top address of the section area B;
Alternatively, the first half of the even field generates a zero offset value required for the first address of the storage area to become the address of the partitioned area C. Generating the offset value necessary to become the start address or the offset value necessary for the first half of the storage destination start address of the even field to become the start address of the partitioned area B; Means for switching every time a new original frame is stored in each of the storage areas; means for adding the field storage start address, the field address, and the offset value to generate a storage address of the original frame has the door, the original frame newly inputted, the input opening of the raw frame
The original frame containing the original frame being encoded at the beginning
Overwrites the storage area with the end of encoding
A video encoding device that stores the image at the generated storage destination address .