JP3290900B2 - Field-effect transistor, semiconductor integrated circuit device, and method of manufacturing field-effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor using a III-V group compound semiconductor, and more particularly to a field effect transistor suitable for forming a logic circuit. In the information processing field in recent years, a device capable of higher-speed logic operation is required, and the use of a field-effect transistor using a compound semiconductor (for example, GaAs) instead of a silicon device is being studied.

In a compound semiconductor device (for example, a microwave field-effect transistor or HEMT) used in an amplifier section of a cellular phone or the like, the compound semiconductor is also used when the logic section is further integrated into a body. A field effect transistor for the used logic is required.

[0003]

2. Description of the Related Art FIGS. 24A and 24B show a conventional field-effect transistor using a compound semiconductor, wherein FIG. 24A is a plan view and FIG. In the figure,
Reference numeral 101 denotes a compound semiconductor layer, which is made of semi-insulating GaAs in this example. Note that the compound semiconductor layer 101 may be formed over a substrate made of a compound semiconductor or may refer to the compound semiconductor substrate itself. Reference numeral 102 denotes a well region into which a p-type impurity has been introduced. Reference numeral 103 denotes a channel region into which an n-type impurity has been introduced. 104 is an LDD region,
An n-type impurity having a higher concentration than the channel region is introduced. Reference numeral 105 denotes a source region, and reference numeral 106 denotes a drain region, both of which have a higher concentration of n-type impurities than the LDD region 104. 107 is a source electrode, 108
Is a drain electrode, both of which are ohmically connected to the source and drain regions. A gate electrode 109 is in Schottky contact with the channel region 103.

As is clear from FIG. 24A, the gate electrode 109 is provided with a projection 109a. The protrusion 109a is provided for the following reason. That is, between the source / drain electrodes 107 and 108, in addition to the channel region 103 into which the n-type impurity is introduced, a compound semiconductor layer (semi-insulating GaAs layer) on the boundary portion or outside the region.
A minute channel in which carriers travel is formed in 101, and a short channel effect occurs. Therefore, the gate electrode 109 is extended above the compound semiconductor layer 1 to extend the protrusion 1
09a is provided to apply a gate electric field to carriers traveling in the minute channel, thereby suppressing the occurrence of the short channel effect.

The gate electrode 109 further has a gate pad portion 109b, and wirings and the like are connected to the gate pad portion 109b. The well region 102
Has a conductivity type opposite to that of the channel region 103, and suppresses generation of a short channel effect due to leakage of carriers from the channel region 103 to the compound semiconductor layer 101 side due to a pn junction with the channel region 103. is there.

[0006] In the field-effect transistor composed of such a compound semiconductor, the speed of carriers traveling in a crystal is much higher than that of a silicon device or the like, so that high-speed arithmetic processing can be expected.

[0007]

As described above, a field effect transistor using a compound semiconductor can operate at high speed, but has a problem that its static characteristics are particularly changed at a low frequency. That is, in a low frequency band, the drain current, the transconductance, and the drain conductance are dispersed, and as a result, the change point of the transistor operation (the timing of high-low or vice versa) varies. Such a variation is called a delay variation.

[0008] This problem is particularly acute in logic circuits. That is, the logic operation of the elements constituting the logic circuit is not executed as expected unless the change point is constant. Usually, the delay margin is dealt with by increasing the timing margin of the logic operation. However, an extra timing margin is added to the circuit operation, and the field effect transistor using the compound semiconductor is used. Has a problem that high-speed operation cannot be realized.

This delay variation is a phenomenon that occurs specifically when a compound semiconductor is used. When a single element crystal is used as in a silicon device, the delay variation does not occur substantially. In other words, the reason that the margin considering the delay variation must be added to the design of the logic circuit is a problem that is peculiar to a field-effect transistor using a compound semiconductor.

An object of the present invention is to solve the above-mentioned problems and to obtain a field-effect transistor in which delay fluctuation is reduced as much as possible.

[0011]

The first object of the present invention is to provide a compound semiconductor layer, a channel region of the first conductivity type provided in the compound semiconductor layer, and the compound semiconductor layer. A first conductivity type source and drain region provided opposite to each other with a channel region interposed therebetween, and a first conductivity type source and drain region provided on the channel region and extending in a direction crossing a direction in which the source and drain regions face each other; A gate electrode having a protrusion protruding outside the channel region; a source and drain electrode electrically connected to the source and drain regions; and the channel region formed in the compound semiconductor layer, the source; Surround them outside the drain region and the protrusion of the gate electrode, and deeper than the channel, source and drain regions. Made a, wherein the first conductivity type be solved by the first field effect transistor, characterized in that it comprises a well region of a second conductivity type opposite.

[0012] The second problem is that the gate electrode includes:
The problem is solved by the field effect transistor according to the first aspect of the present invention, wherein a gate pad portion having a width larger than that of the gate electrode is provided. The above task is the third
Preferably, the well region is formed so as to surround a region outside the region of the gate pad portion, and the field effect transistor according to the second invention is solved.

[0013] Fourthly, the above-mentioned problem is the fourth problem that the source and drain electrodes have portions protruding outside of the source and drain regions, and the well region is formed so as to surround the outside of these protruding portions. The problem is solved by the field-effect transistor according to the first aspect of the present invention. Fifth, the above-mentioned problem is caused by the following:
The problem is solved by the field-effect transistor according to the first aspect of the present invention, which protrudes outward by at least 0.5 μm from the channel region.

A sixth problem is that the distance from the outer peripheral edge of the well region to the region of the channel region, the source, the drain, and the protrusion of the gate electrode is 0.3 μm.
m or more, which is solved by the field effect transistor according to the fourth invention. The above task is the seventh
According to a sixth aspect of the present invention, there is provided a field-effect transistor, wherein the interval is larger than a value obtained by adding a mask alignment margin to 0.3 μm.

Eighthly, the object of the present invention is attained by a field effect transistor according to the first invention, wherein the compound semiconductor layer is provided on a semi-insulating compound semiconductor substrate. Ninth, the problem is solved by the field-effect transistor according to the first invention, wherein the well region is p-type, and the channel, source, and drain regions are n-type.

A tenth object of the present invention is that the well region is formed of n
The field-effect transistor of the first invention is characterized in that the channel, source and drain regions are p-type. Eleventhly, the above-mentioned object is attained by a field-effect transistor according to the first invention, wherein a potential applying electrode for applying a constant potential is connected to the well region.

According to a twelfth aspect, in the eleventh aspect, the second conductive type impurity is introduced into the region to which the potential applying electrode is connected at a higher concentration than the well region. The problem is solved by the field effect transistor according to the invention of the invention. The thirteenth problem is that the ground potential is applied to the constant potential application electrode.
The problem is solved by the field-effect transistor of the first aspect.

The fourteenth problem is that the impurity concentration in the channel region between the source electrode and the gate electrode and between the drain electrode and the gate electrode is higher than that in the channel region immediately below the gate electrode. And the first conductivity type LDD region having an impurity concentration lower than that of the drain region is provided.
The problem is solved by the field effect transistor according to the invention of the invention.

Fifteenth, the above problem is characterized in that an element isolation region having the same conductivity type as the well region and having a higher concentration than the well region is provided on the outer periphery of the well region. The problem is solved by the field effect transistor of the invention. Sixteenthly, the above object is attained by a semiconductor integrated circuit device wherein a plurality of the field effect transistors of the first invention are integrated in a compound semiconductor layer.

The seventeenth problem is that, among the plurality of integrated field effect transistors, those forming a circuit having a common output are formed by connecting the well layers of each field effect transistor to a compound semiconductor layer. The semiconductor integrated circuit device according to the sixteenth aspect is characterized in that the semiconductor integrated circuit device is connected in common. Eighteenthly, the above object is achieved by a semiconductor integrated circuit device according to the sixteenth invention, wherein the plurality of field effect transistors are connected in series.

According to a nineteenth aspect of the present invention, in the semiconductor integrated circuit device according to the eighteenth aspect, the well regions of the serially connected field-effect transistors are electrically separated from each other. Resolve.

A twentieth object is to provide a step of forming a second conductivity type well region in a compound semiconductor layer and selectively forming a first conductivity type opposite to the second conductivity type in a region inside the well region. Forming a channel region shallower than the well region by introducing an impurity of a mold type; and selectively introducing impurities into a region inside the well region to be shallower than the well region and facing the channel region. Forming a source and drain region of the first conductivity type; and depositing a gate electrode material on the compound semiconductor layer;
Inside the well region, extending in a direction crossing the direction in which the source and drain regions face each other,
Forming a gate mask of a pattern having a protrusion protruding outside the channel region on the gate electrode material, and patterning the gate electrode by selectively etching using the gate mask. And a step of forming source and drain electrodes electrically connected to the source and drain regions.

According to a twentieth aspect, in the twentieth aspect, the periphery of the well region is defined at least 0.3 μm outside the periphery of the channel, source, drain region, and gate mask. The problem is solved by the method for manufacturing a field effect transistor according to the invention. The above problem is the second
(2) The electric field according to the twenty-first aspect, wherein a peripheral edge of the well region is further defined by 0.3 μm or more outside the peripheral edge in addition to an alignment margin of the channel, the source / drain region and the gate mask. The problem is solved by a method of manufacturing an effect transistor.

The twenty-third object is to form a second conductive type compound semiconductor layer, and selectively introducing a first conductive type impurity opposite to the second conductive type into the compound semiconductor layer. Forming a channel region, selectively introducing the impurity of the first conductivity type into the compound semiconductor layer, forming source and drain regions facing each other with the channel region interposed therebetween, A step of depositing a gate electrode material on a semiconductor layer; and a step of extending on a surface of the compound semiconductor layer in a direction transverse to a direction in which the source and drain regions face each other and protruding outward from the channel region. Forming a gate mask of a pattern having a protruding portion on the gate electrode material, and selectively etching using the gate mask to form a gate electrode; Solved by method of manufacturing a field effect transistor and having a step of forming a source and a drain electrode electrically connected to the source and drain regions.

The present inventor, when examining the cause of the delay variation, estimates that the cause of the delay variation may be outside the region defined as the channel region, not in the channel region where the substantial carrier travels. Then, various experiments were performed. The details of these various experiments will be described in detail in an embodiment of the invention described later. The present inventor has found from the results of this experiment that delay fluctuation is significantly reduced by forming a well region in the compound semiconductor layer so as to surround the protruding portion of the gate electrode. Therefore, by configuring a field effect transistor having such a well region, the object of the present invention can be achieved.

Further, according to the present invention, a field effect transistor having a smaller delay fluctuation can be obtained by forming a well region so as to surround a protruding portion of the source and drain electrodes from the source and drain regions. In a field-effect transistor having a gate pad portion wider than the gate electrode, the delay variation can be further suppressed by forming the well region so as to surround the gate pad portion.

It should be noted that sufficient theoretical elucidation has not yet been made as to why the provision of the well region surrounding the protruding portion of the gate electrode significantly reduces the delay fluctuation. However, its remarkable effect on suppressing delay fluctuation has been confirmed by experiments by the present inventors.

[0028]

1A and 1B are a plan view showing a field effect transistor according to a first embodiment of the present invention and a cross-sectional view taken along the line II. In the figure, reference numeral 1 denotes a compound semiconductor layer, which is made of semi-insulating GaAs in this example. The compound semiconductor layer 1 may be formed on a substrate made of a compound semiconductor, or may refer to the compound semiconductor substrate itself. Reference numeral 2 denotes a well region into which a p-type impurity has been introduced. Reference numeral 3 denotes a channel region into which an n-type impurity has been introduced. Reference numeral 4 denotes an LDD region into which an n-type impurity having a higher concentration than the channel region is introduced. Reference numeral 5 denotes a source region, and reference numeral 6 denotes a drain region. In both cases, n-type impurities having a higher concentration than the LDD region 4 are introduced. 7
Is a source electrode, and 8 is a drain electrode, both of which are in ohmic connection with the source and drain regions. Further, both the source and drain electrodes 7 and 8 are formed beyond the boundaries between the source and drain regions 5 and 6. Reference numeral 9 denotes a gate electrode, which is in Schottky contact on the channel region 3.
The gate electrode 9 extends in a direction crossing the direction in which the source and drain regions 5 and 6 face each other, and has a protruding portion 9 a protruding outside the channel region 3. 9b is a gate pad portion connected to one protruding portion 9a.

In this embodiment, the p-type well region 2 includes a channel region 3, an LDD region 4, a source / drain region 5,
6, the projection 9a of the source and drain electrodes 7, 8, the projection 9a of the gate electrode 9, and the gate pad 9b have a shape that surrounds the surface of the semiconductor layer 1 at a further depth. In the present embodiment, by providing the well region 2 having such a shape, it is possible to significantly suppress the delay fluctuation as compared with the conventional device. A discussion of how delay fluctuation can be suppressed will be described later together with a comparative example performed by the inventor.

FIGS. 2A and 2B are a plan view showing a field-effect transistor according to a second embodiment of the present invention, and a cross-sectional view taken along the line II-II. In FIG. 2, the same parts as those in FIG. 1 are denoted by the same reference numerals.
Although the well region 2 is defined in the compound semiconductor layer 1 in the first embodiment shown in FIG. 1, in the second embodiment, the compound semiconductor layer 1a itself functions as a well region. And a conductivity type opposite to that of the channel region. That is, the compound semiconductor layer 1a has a p-type conductivity. Other configurations,
That is, the channel region 3, the LDD region 4, the source and drain regions 5, 6, the source and drain electrodes 7, 8, the gate electrode 9, the protrusion 9a, and the gate pad 9b are the same as those in the first embodiment shown in FIG. It has a configuration.

In this embodiment, the projection 9 of the gate electrode
Since the compound semiconductor layer 1a functioning as a well region is provided outside of "a", delay fluctuation can be suppressed as in the first embodiment. In order to obtain an optimum embodiment of the present invention, the present inventors formed field-effect transistors in which the structure of the well region was variously changed, and measured the delay fluctuation.

FIGS. 3 to 8 are diagrams showing various transistor structures examined and tested by the present inventor. In each drawing, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals. First, the comparative study example shown in FIG. 3 is the same as the conventional example shown in FIG. 19 in plan view as shown in FIG.
As shown in FIG. 6B, which is a cross-sectional view in the gate electrode direction III-III, the well region 2 is also provided immediately below the protrusion 9a of the gate electrode 9.

In the comparative example shown in FIG. 4, the well region 2 is provided immediately below the source electrode 7 and the drain electrode 8. That is, in the conventional example of FIG.
A part of the drain electrode 8 is in contact with the compound semiconductor layer 1 outside the source region 5 and the drain region 6.
FIG. 4 shows the well region 2 including this portion. 4A is a plan view of the field-effect transistor, and FIG. 4B is a cross-sectional view taken along the line IV-IV in FIG.

Next, FIG. 5 includes the structure of the well region 2 in both FIG. 3 and FIG. 4, and the channel 9 extends just below the protruding portion 9 a of the gate electrode 9 and the source electrode 7 and the drain electrode 8. An area 2 is provided. FIG. 5
(A) is a plan view of the field effect transistor, and FIG.
FIG. 5 is a sectional view taken along line VV in FIG. Next, FIG.
In the example of FIG. 4, the well region 2 is provided only directly below the source electrode 7 and the drain electrode 8 in the example of FIG. 4, but the well region 2 is extended to include the outside of the source electrode 7 and the drain electrode 8. It is. 6A is a plan view of the field effect transistor, and FIG. 6B is a view taken along the line VI-VI in FIG.
It is sectional drawing on a line.

FIG. 7 is similar to the example of FIG.
Compared to FIG. 4, the contact area between source electrode 7 and well region 2 maintained at a constant potential is expanded. With this configuration, further stabilization of the potential of the well region 2 can be expected. 7A is a plan view of the field-effect transistor, and FIG. 7B is a cross-sectional view taken along the line VII-VII of FIG.

FIG. 8 is similar to the example of FIG. 7, except that a contact region 10 having a high concentration is provided in order to further reduce the contact resistance between the well region 2 and the source electrode 7. Things. FIG. 8A is a plan view of the field effect transistor, and FIG.
FIG. 8 is a sectional view taken along line VIII-VIII of FIG. FIG. 9 shows the results of measuring the delay variation for each of the structures of FIGS. 1 and 2 according to the present invention, the structure of FIG. 24 of the conventional example, and the structures of FIGS. 3 to 8 studied by the present inventors. It shows.

The measurement results shown in FIG. 9 were obtained as follows. That is, as shown in FIG. 10A, a plurality of (for example, about 100) inverters constituted by field-effect transistors having respective structures are connected in series, and a delay between an input pulse (IN) and an output pulse (OUT) is obtained. Is measured.
The measurement of the delay amount is performed by changing the period of the input pulse. In the experiments of the inventor, the pulse width of the input pulse IN is set to 10 ns, and the period is changed in several steps from 20 ns to 40.96 μs, and the pulse width of the output pulse OUT is observed (timing shmoo measurement is performed). The delay fluctuation amount shown in FIG. 9 is the delay amount when the cycle is 20 ns,
It is determined by the ratio with the delay amount at 40 and 96 μs.

Next, a method of calculating the actual delay fluctuation will be briefly described. FIG. 10B shows a timing chart of the input pulse IN and the output pulse OUT. Here, a case where the pulse cycle is 100 ns is shown. For the input pulse IN having a pulse width of 10 ns, the timing of the falling Tdn and the timing of the rising Tup of the output pulse OUT are measured. This measurement is performed by changing the cycle of the input pulse IN. FIG. 10C shows the measurement results of the timing. The mark * in the figure indicates that the output is at the H (high) level. Therefore, the output level changes from H to L (low, *
Tdn is detected from the point changing to (the part without the mark), and Tup is detected from the point changing from L to H.

In FIG. 4C, the vertical axis indicates the period of the input pulse IN, and the measurement is performed from a period of 40.96 μs to 20 periods.
ns is performed over several steps. In order to determine the delay variation (Δ mark), first, the amount of timing variation at the falling Tdn of the output pulse is determined by equation (1), and the amount of timing variation at the rising Tup of the output pulse is determined by equation (2). The delay variation (Δ mark) is defined by equation (3). The result of FIG. 9 shows the value obtained by the equation (3) in percentage.

[0040]

(Equation 1)

[0041]

(Equation 2)

[0042]

(Equation 3)

As is clear from FIG. 9, the delay variation is 8.65% in the example of FIG. On the other hand, the configuration of FIG. 3 in which the well region 2 is extended just below the protrusion 9 a of the gate electrode 9, the configuration of FIG. 4 in which the well region 2 is extended just below the source electrode 7 and the drain electrode 8, and FIGS. In the configuration of FIG. 5 having the well regions 2 of both configurations in FIG. 4, the delay fluctuation is equal to that of the configuration of the conventional example, and the effect of expanding the well region 2 was not observed.

As shown in FIG. 6, when the well region 2 is extended outside the source electrode 7 and the drain electrode 8,
Although some effects were seen, the delay fluctuation was still 4.
80%, and the delay fluctuation cannot be sufficiently reduced. In order to stabilize the potential of the well region 2,
In the structure in which the contact area between the source electrode 7 and the well region 2 is increased as shown in FIG. 7 and the structure in which the contact region 10 is provided in the well region 2 in contact with the source electrode 7 as shown in FIG. The delay fluctuation was almost the same.

On the other hand, FIG. 1 and FIG.
In each of the apparatuses, the delay variation is 1.72%, and 1.27%.
It is 75%, which means that the delay variation is remarkably small and superior to the conventional example or the comparative example. Considering the above results, first, from the results of FIGS. 3 to 5, even if the well region 2 is extended to be provided immediately below the protruding portion of the gate electrode, the source and drain regions, and the source and drain electrodes, it is possible to prevent the delay variation. Has no effect,
From the results shown in FIG. 6, it can be seen that no significant effect can be obtained even if the well region is extended to the outside of only the source and drain electrodes while the protrusion of the gate electrode remains as it is.

On the other hand, it can be seen from the results of FIGS. 7 and 8 that the delay fluctuation is not improved at all when the potential of the well region is stabilized. Also, as shown in FIGS. 1 and 2, the formation of the protruding portion of the gate electrode, the source and drain regions, and the well region to the outside of the source and drain electrodes is only effective for delay variation. Can understand.

In the structure shown in FIGS. 1 and 2, although the principle on which the effect of suppressing the delay variation is exhibited is not clear, the gate electric field applied to the projection 9a of the gate electrode is not applied to the outside of the channel region. It is presumed that changing the potential of the compound semiconductor layer and inducing the fluctuation of unstable carriers located in the compound semiconductor layer causes delay fluctuation.

That is, in the case of FIG. 6, since the protruding portion of the gate electrode is also formed on the compound semiconductor layer outside the well region, unstable carriers existing in the compound semiconductor layer outside the well region are removed. 1 and 2, the protrusion of the gate electrode is surrounded by the well region, and unstable in the compound semiconductor layer outside the well region. It is considered that since the gate electric field is suppressed from being applied to the carriers, the high performance as described above can be realized.

The source and drain electrodes are also
The same phenomenon as the above-described protrusion of the gate electrode occurs in a portion directly in contact with the compound semiconductor layer. Therefore, by surrounding these portions with the well region in the same manner as the protruding portion of the gate electrode, the cause of the delay variation is reduced. In FIGS. 1 and 2, the well region is provided including the outside of the gate pad portion. However, since the region is generally a portion that does not greatly affect the operation of the field-effect transistor, the well region is replaced with the gate pad portion. It is considered that there is no effect on the effect of the present invention even if it is not expanded to include. Of course, if the gate pad portion is not provided structurally, the well region may be formed to include only the protruding portion of the gate electrode in a region that affects the operation of the transistor. FIG. 23 described later shows an embodiment of the present invention in a field-effect transistor having a structure not including a gate pad portion.

Further, in FIG. 1, the shape of the well region is shown by enlarging and copying the outer peripheral shape of the region of the field effect transistor. However, the shape is not limited to this. For example, the well region covers the entire field effect transistor. It may be square, circular, or the like. In short, it is necessary to have a structure in which a part of the electrode which does not substantially contribute to the operation as the field effect transistor is surrounded by a well layer (buried layer) having a conductivity type opposite to that of the channel layer. The impurity concentration of the well layer surrounding the electrode is equal to or higher than the concentration of the well layer below the channel layer.

Although the LDD region 4 is provided in FIGS. 1 and 2, this is not essential for the present invention, and the effect of the present invention does not change even if it is excluded. It is preferable that the projection of the gate electrode normally protrudes by 0.5 μm or more from the channel region for stable channel control. In the first embodiment of the present invention, the distance from the outer peripheral edge of the well region to the region of the protrusion of the gate electrode is
It is desirable that the thickness be 0.3 μm or more. This is because the gate potential applied to the compound semiconductor layer (the region where unstable carriers exist) is further reduced to achieve stabilization. In addition, in consideration of the alignment margin for mask alignment at the time of manufacturing, it is desirable that the above-mentioned interval has a value of [0.3 μm + alignment margin (0.2 to 0.5 μm)] at the time of design.

The compound semiconductor layer may itself constitute a compound semiconductor substrate, or may be provided on a separately prepared compound semiconductor substrate. When the channel is n-type, the source and drain regions need to be n-type, and the well region needs to be p-type. Similarly, if the channel is p-type,
The source and drain regions also need to be p-type, and the well region needs to be n-type.

Further, the well region may be connected to a source electrode maintained at a constant potential or a separately generated constant potential (for example, ground potential) electrode for stabilization. In order to reduce the contact resistance with an appropriate electrode, a portion serving as a contact region into which impurities are introduced at a high concentration may be formed. This embodiment is shown in FIG. 11 (third embodiment). 11A is a plan view, and FIG. 11B is a cross-sectional view taken along line XI-XI in FIG. This embodiment is characterized in that a potential applying electrode 11 for keeping the well region 2 at a specific potential is further provided in the field effect transistor having the structure shown in FIG. Electrode 1
Immediately below 1, p-type impurities are introduced at a high concentration to form ap ⁺ region 12, and an ohmic contact with the electrode 11 is established. Usually, the electrode 11 is connected to the ground potential.

Since the source electrode is mainly grounded, it is convenient to electrically connect the source electrode to the well region. (Similarly, the well region was stabilized in FIGS. 7 and 8, but the effect of the present invention did not appear because the well region was not formed including the outside of the protrusion of the gate electrode. On the other hand, the reason for adopting this configuration in the present invention to stabilize the potential of the well region is to minimize the influence of the potential applied by the protruding portion of the gate electrode from reaching the compound semiconductor layer. Note that a region having the same conductivity type as the well region and a higher concentration than the well region can be formed outside the well region defined by the present invention as an element isolation region. FIG. 12 is a view showing a fourth embodiment of the present invention, and shows a structure in which an element isolation region 13 is provided on the outer periphery of a well region 2. The same structure as that of FIG. Present. FIG.
As is clear from FIG. 12, even in the structure of FIG. 12, the delay variation can be suppressed to 1.70% which is equal to (or slightly improved) the structure of FIGS.

If a plurality of field-effect transistors according to the present invention are integrated to form a logic circuit, for example, delay fluctuation can be suppressed to an extremely low level, and operation can be performed at high timing. In that case, if the transistors are connected in parallel and have the same output, the well region may be shared in the compound semiconductor layer. However,
When the field-effect transistors are connected in series, the transistors perform different outputs. Therefore, it is preferable to electrically separate the well regions.

FIG. 13 is a plan view of a field-effect transistor according to a fifth embodiment of the present invention. Two transistors are connected in parallel via a drain electrode 8 to which an output terminal (not shown) is connected. It has a structure. Since both transistors have the same output, in this embodiment, the well region 2 is commonly connected in the compound semiconductor substrate.

14 to 20 are cross-sectional views for explaining the manufacturing steps. Among the transistors shown in FIG.
Although only one is shown, the other transistor is also manufactured in parallel in the same process. Next, a process of manufacturing a field-effect transistor having the structure of FIG. 13 will be described with reference to process cross-sectional views of FIGS.

Referring to FIG. 14, in this embodiment, a surface layer of a compound semiconductor substrate is used as compound semiconductor layer 1. As shown in FIG. 14, a mask 14 is selectively formed on the compound semiconductor layer 1, and a p-type impurity is ion-implanted through the mask to form a well region 2. Here, since the well region 2 needs to be formed so as to surround a gate electrode, an LDD region, a source and a drain region, and the outside of the source and drain electrodes to be formed later, the mask 14 is formed as shown in FIG. It has a shape as shown in FIG. Further, the size of the well region 2 is determined in consideration of the positional deviation of each mask to be formed later, and further taking into account the alignment margin.

The details of each part are as follows. Compound semiconductor substrate: semi-insulating GaAs compound semiconductor layer 1: semi-insulating GaAs mask 12: photoresist well region 2: impurity: Mg (p-type impurity) Acceleration energy: 150 to 250 (KeV) Dose: 1.0 × 10 ^{12 to} 2.0 × 10 ¹² (cm ⁻² ) See FIG. 15 After removing the mask 14 shown in FIG. 14, a mask 15 for newly defining a source, a drain, an LDD and a portion to be a channel region is formed. Then, an n-type impurity is ion-implanted using the resultant to form a first n-type region 3a.

Although the channel region is actually formed immediately below the gate electrode to be manufactured later, in the present embodiment, impurities are simultaneously introduced into the regions to be the source region, the drain region and the LDD region later. I have. The details of each part are as follows. Mask 15: Photoresist First n-type region 3a (including channel region 3): Impurity: Si (n-type impurity) Acceleration energy: 30 to 50 (KeV) Dose: 3.0 × 10 ^{12 to} 7.0 × 10 ¹² (cm ⁻² ) Next, the semiconductor substrate in the state of FIG. 15 is annealed in an atmosphere of an inert gas such as nitrogen. Annealing temperature is about 80
0 ° C., time is about 20 minutes.

Referring to FIG. 16, after removing the mask 15 in FIG. 15, a gate electrode material is applied, and a gate electrode 9 is formed by selective etching using a mask (not shown). The portion immediately below the gate electrode is a portion that actually operates as a channel. The details of the gate electrode 9 are as follows.

Gate electrode 9: Material: WSi Thickness: 4500 (angstrom) 3000 to 5000 (angstrom) is appropriate.

Gate length: 0.6 μm (an example) Processing method: Reactive ion etching (RIE) See FIG. 17 A new mask 16 is formed, and an n-type impurity is ion-implanted using this and the gate electrode 9 as a mask. , Second n-type region 4
a is formed.

Although the LDD region 4 is actually located between the channel region 3 and the source and drain regions, in the present embodiment, impurities including the regions to be the source and drain regions are introduced. ing. Details of the second n-type region 4a are as follows. Region 4a (including LDD region 4): Impurity: Si (n-type impurity) Acceleration energy: 40 to 80 (KeV) Dose: 1 × 10 ¹³ (cm ⁻² ) See FIG. 18 Remove mask 16 in FIG. After that, an insulating film made of silicon dioxide is applied on the entire surface, and then the entire surface is etched in the vertical direction to form sidewall insulating films 17 on both sides of the gate electrode. The region immediately below the sidewall insulating film 17 (region indicated by reference numeral 4) will be a portion that functions as an LDD later.

The details of the wall insulating film 17 are as follows. Sidewall insulating film 17: Material: silicon dioxide Processing method: reactive ion etching (RIE) See FIG. 19 A new mask 18 is formed and used as a mask together with the gate electrode 9 and the sidewall insulating film 17 to remove n-type impurities. By ion implantation, a source region 5 and a drain region 6 are formed.

Details of the source and drain regions are as follows. After the source and drain regions are formed, the substrate is annealed in an atmosphere of an inert gas such as nitrogen. The annealing temperature is about 750 ° C. and the time is about 20 minutes.

Referring to FIG. 20, after removing the sidewall insulating films 17 on both sides of the gate electrode 9,
A mask pattern (not shown) made of, for example, a photoresist is formed to selectively open the source and drain regions, and an electrode material is deposited by, for example, an evaporation method. Then
The source electrode 7 and the drain electrode 8 are selectively formed by a lift-off method in which the mask pattern is removed and thereby the electrode material on the mask pattern is simultaneously removed.

The details of the source and drain electrodes are as follows. Source electrode 7, drain electrode 8: Material: AuGe / Ni / Au Thickness: 3000 (angstrom) in total When each electrode is formed, it is annealed in an inert gas atmosphere such as nitrogen to alloy the electrode metal. I do. The annealing temperature is about 500 ° C. and the time is about 2-3 minutes.

According to the field-effect transistor of this embodiment manufactured by the above steps, the gate electrode, the LDD
Since the region, the source and drain regions, and the source and drain electrodes are formed inside the well region, unstable carriers in a region that operates as a transistor are suppressed, so that delay fluctuation can be reduced.

Therefore, according to the present embodiment, even if the operation timing is accelerated, the malfunction due to the delay variation can be eliminated, and a higher-speed circuit operation can be realized. In this embodiment, since the channel is n-type, the well region is p-type. Of course, the conductivity type is reversed, and the well region is n-type, and each of the channel, LDD region, source, and drain region is p-type. Is also good.

In manufacturing the field effect transistor according to the first embodiment of the present invention, FIGS.
It is not necessary to add a special process to each process shown in FIG. FIG. 1 shows a mask pattern for forming a well region.
Each process after FIG. 14 can be referred to except for the shape of the well region 2 shown in FIG. Further, in manufacturing the field-effect transistor according to the second embodiment of the present invention, an impurity of the opposite conductivity type may be added to the compound semiconductor layer, and a step of selectively forming a well region is not required. Specifically, for example, a p-type impurity is added to the compound semiconductor layer 1 made of semi-insulating GaAs so that the layer itself functions as a well region. For this purpose, for example, the concentration of impurity Mg is set to 1.0 × 10 ^{12 to} 2.0.
What is necessary is just to implant into the compound semiconductor layer 1 so that it may be set to × 10 ¹² (cm ⁻² ). After forming the compound semiconductor layer 1 in this manner, the steps after FIG. 15 (after the step of manufacturing the channel region) may be performed.

In the fifth embodiment, an example in which a parallel circuit of two transistors is realized has been described. However, a series circuit can be realized by using the present invention. FIG. 21 is a plan view of a field-effect transistor according to the sixth embodiment of the present invention, in which two transistors 20 and 21 define a region 22 serving as a source region of one transistor 20 and a drain region of the other transistor 21. It has a structure commonly connected in series. Note that a common electrode 24 serving as a source electrode of the transistor 20 and a drain electrode of the transistor 21 is formed over the region 22.

In the figure, 25 is the gate electrode of the transistor 20, 26 is the gate electrode of the transistor 21, 27 is the drain electrode of the transistor 20, 28 is the source electrode of the transistor 21, 29 is the gate electrode of the transistor 23, 30 is the drain electrode, And 31 indicate source electrodes. Also in this embodiment, the well region 32 is provided so as to surround the channel, the source and drain regions, and the protrusion of each electrode.

However, in the series circuit, since the output of each transistor may be different, it may be preferable that the well regions are not shared as in the present embodiment but are independent from each other. (Of course, even when the parallel circuit shown in FIG. 13 is formed, the well region may be formed separately.) In the fifth and sixth embodiments, the element as shown in FIG. Although the isolation region 13 is not formed, a high-concentration p-type (when the well region is a p-type) element isolation region may be formed with another element as necessary.

FIG. 22 is a view showing a seventh embodiment of the present invention, and is a plan view and a partially enlarged view of a cell array constituted by using a field-effect transistor according to the present invention. In the figure, 32 is a basic cell array, 33 is an input / output cell, and 34 is an input / output pad. One basic cell in the basic cell array 32 has a structure 3 shown in FIG.
It is composed of a number of field effect transistors. FIG.
In FIG. 3, reference numeral 40 denotes a source electrode of the first transistor, and reference numeral 41 denotes a common electrode which is both a drain electrode of the first transistor and a source electrode of the second transistor. 42 is a drain electrode of the second transistor, and 43 and 44 are gate electrodes of the first and second transistors. Reference numeral 45 denotes a source electrode of the third transistor, 46 denotes a drain electrode, and 47 denotes a gate electrode.

In the cell array of FIG. 22, the basic cells are arranged such that the arrangement of the cells is vertically symmetrical between the upper, lower, left and right cells. The enlarged view schematically shows the layout relationship of four basic cells adjacent to each other. In the drawing, the symbol F in each basic cell 35 is a mere symbol indicating a symmetric relationship between adjacent cells.

As shown in FIG. 22, in a cell array using a considerable number of field-effect transistors of the present invention, delay fluctuations in individual transistors can be suppressed to a small value, and high-speed operation is required as a whole cell. In a cell array, the effect is enormous.
In each of the embodiments described above, the compound semiconductor layer 1 is formed using semi-insulating GaAs.
A similar effect can be obtained even with a field-effect transistor using another compound semiconductor such as lnP.

In the first embodiment of the present invention shown in FIG. 1, the well region covers the outside of the source and drain regions. ) IEEE released in December
JOURNAL OF SOLID-STATECIRCUITS, VOL.25, No.6
p1544 〜p1549 ”A p-Well GaAs MESFET Technolog
y for Mixed-Mode Applications ”.

This known document has a sectional view in the gate length direction.
Although only (Fig. 8) is described, the area marked as p-well is described. This region is located at the same site as the well head castle in the present invention, and at first glance, appears to be similar to the configuration of the present invention. However, this known document surrounds the channel region with p-Well (well region),
It is intended to electrically separate from the wiring (side gate), etc., and it is not described that a protrusion is formed on the gate electrode as in the present invention, and the influence of the protrusion on the compound semiconductor layer is not described. Is not considered at all.

In short, since the purpose of this known document is to electrically isolate the channel region, only the channel region needs to be surrounded by the well region, and there is no reason to surround the protruding portion of the gate electrode with the well region. Therefore, it is appropriate to judge that the configuration and effect are almost the same as those in FIG. Japanese Patent Application Laid-Open No. 3-104239, published on May 1, 1991, discloses a technique for forming a well region below a wiring. However, unlike the present invention described above, a well region is not provided in the field effect transistor region itself, and this known document does not disclose or suggest the present invention.

A well-known document in which a well region is provided in the field-effect transistor region itself is disclosed in Japanese Patent Application Laid-Open No. 58-5, published on April 4, 1983.
No. 6471. In this known document, a technique of forming a well region around the source electrode and the drain electrode is disclosed, but the gate electrode is not surrounded by the well region. In addition, since the conductivity type of the well region is the same n-type as the channel region, it can be said that the well region is completely unrelated to the present invention.

[0082]

As described above, according to the present invention, since the delay fluctuation can be suppressed to a low level, even if the operation timing is accelerated, a malfunction due to the delay fluctuation can be eliminated and a higher-speed circuit operation can be realized. . This means that the original high-speed property of the field-effect transistor using the compound semiconductor can be realized, and particularly in a logic circuit that requires a high-speed operation,
The effect is enormous.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams illustrating a configuration of a field-effect transistor according to a first embodiment of the present invention, wherein FIG. 1A is a plan view thereof, and FIG. 1B is a cross-sectional view taken along line II of FIG. FIG.

FIGS. 2A and 2B are diagrams illustrating a configuration of a field-effect transistor according to a second embodiment of the present invention, wherein FIG. 2A is a plan view thereof, and FIG. 2B is a diagram II-II of FIG. It is sectional drawing on a line.

FIGS. 3A and 3B are diagrams illustrating the structure of a first field-effect transistor compared and studied in forming the present invention, wherein FIG. 3A is a plan view thereof, and FIG. FIG. 3 is a sectional view taken along line III.

4A and 4B are diagrams for explaining the structure of a second field-effect transistor compared and studied in forming the present invention, wherein FIG. 4A is a plan view thereof, and FIG. FIG. 4 is a sectional view taken along line IV.

FIGS. 5A and 5B are diagrams illustrating the structure of a third field-effect transistor compared and studied in forming the present invention, wherein FIG. 5A is a plan view thereof, and FIG. 5B is a view taken on line VV in FIG. It is sectional drawing.

FIGS. 6A and 6B are diagrams illustrating the structure of a fourth field-effect transistor compared and studied in forming the present invention, wherein FIG. 6A is a plan view thereof, and FIG. FIG. 6 is a sectional view taken along line VI.

FIGS. 7A and 7B are diagrams illustrating the structure of a fifth field-effect transistor compared and studied in forming the present invention, wherein FIG. 7A is a plan view thereof, and FIG. It is sectional drawing on a VII line.

FIGS. 8A and 8B are diagrams illustrating the structure of a sixth field-effect transistor compared and studied in forming the present invention, wherein FIG. 8A is a plan view thereof, and FIG. VIII
It is sectional drawing on a line.

FIG. 9 is a diagram for explaining the results of measuring delay fluctuations in the respective field-effect transistors of the present invention, the comparative example, and the conventional example.

FIG. 10 is a diagram showing a measuring method for obtaining the graph of the delay variation shown in FIG. 9;
FIG. (B) is a timing chart showing the measurement, and FIG. (C) is a diagram showing the result of the timing measurement.

11A and 11B are diagrams illustrating the structure of a field-effect transistor according to a third embodiment of the present invention, where FIG. 11A is a plan view thereof, and FIG. 11B is a diagram XI-XI of FIG. It is sectional drawing on a line.

12A and 12B are diagrams illustrating the structure of a field-effect transistor according to a fourth embodiment of the present invention, wherein FIG. 12A is a plan view thereof, and FIG. 12B is a view along line XII-XII in FIG. It is sectional drawing.

FIG. 13 is a plan view showing a structure of a field-effect transistor according to a fifth embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a first step in the process of manufacturing the field-effect transistor according to the fifth embodiment of the present invention.

FIG. 15 is a cross-sectional view showing a second step in the process of manufacturing the field-effect transistor according to the fifth embodiment of the present invention.

FIG. 16 is a cross-sectional view showing a third step in the process of manufacturing the field-effect transistor according to the fifth embodiment of the present invention.

FIG. 17 is a cross-sectional view showing a fourth step in the process of manufacturing the field-effect transistor according to the fifth embodiment of the present invention.

FIG. 18 is a cross-sectional view showing a fifth step in the process of manufacturing the field-effect transistor according to the fifth embodiment of the present invention.

FIG. 19 is a cross-sectional view showing a sixth step in the process of manufacturing the field-effect transistor according to the fifth embodiment of the present invention.

FIG. 20 is a cross-sectional view showing a seventh step in the process of manufacturing the field-effect transistor according to the fifth embodiment of the present invention.

FIG. 21 is a plan view showing a structure of a field-effect transistor according to a sixth embodiment of the present invention.

FIG. 22 is a diagram illustrating a structure of a semiconductor integrated circuit device according to a seventh embodiment of the present invention.

23 is a plan view showing a configuration of one basic cell in the semiconductor integrated circuit device shown in FIG.

FIG. 24 is a diagram showing a structure of a field-effect transistor according to a conventional example of the present invention, where FIG.
FIG. 2B is a cross-sectional view taken along the line YY in FIG.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-6-260552 (JP, A) JP-A-2-29761 (JP, A) JP-A-1-228176 (JP, A) JP-A-4- 307755 (JP, A) JP-A-4-93038 (JP, A) JP-A-63-124471 (JP, A) JP-A-1-194365 (JP, A) JP-A-4-356957 (JP, A) JP-B-51-16314 (JP, B1) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/338 H01L 21/06 H01L 21/8232 H01L 29/812 H01L 29/872

Claims (23)

(57) [Claims] A first conductive type channel region provided in the compound semiconductor layer; and a first conductive type channel region provided in the compound semiconductor layer so as to face the channel region. Source and drain regions of a mold, and provided on the channel region, extending in a direction crossing a direction in which the source and drain regions face each other,
A gate electrode having a protrusion protruding outside the channel region; a source and drain electrode electrically connected to the source and drain regions; and a gate electrode formed in the compound semiconductor layer and viewed on a plane. Including a channel region, the source and drain regions, the gate electrode and a protrusion thereof, and viewed from a cross section,
A well region of a second conductivity type opposite to the first conductivity type, formed deeper than the channel region, the source region, and the drain region. 2. The field effect transistor according to claim 1, wherein said gate electrode is provided with a gate pad portion having a width wider than said gate electrode. 3. The field effect transistor according to claim 2, wherein said well region is formed so as to surround a region outside a region of said gate pad portion. 4. The semiconductor device according to claim 1, wherein said source and drain electrodes have portions protruding outside of said source and drain regions, and said well region is formed so as to surround outside these protruding portions. The field-effect transistor according to claim 1. 5. The field-effect transistor according to claim 1, wherein the projecting portion of the gate electrode projects outside the channel region by 0.5 μm or more. 6. The distance from an outer peripheral edge of the well region to a region of the channel region, the source, the drain, and the protrusion of the gate electrode is 0.3 μm or more. Field effect transistor. 7. The apparatus according to claim 6, wherein the distance is larger than a value obtained by adding a mask alignment margin to 0.3 μm.
The field-effect transistor according to any one of the preceding claims. 8. The semiconductor device according to claim 1, wherein said compound semiconductor layer is provided on a semi-insulating compound semiconductor substrate.
The field-effect transistor according to any one of the preceding claims. 9. The field effect transistor according to claim 1, wherein said well region is p-type, and said channel, source and drain regions are n-type. 10. The field effect transistor according to claim 1, wherein said well region is n-type, and said channel, source and drain regions are p-type. 11. The field effect transistor according to claim 1, wherein a potential applying electrode for applying a constant potential is connected to said well region. 12. The field effect type device according to claim 11, wherein said second conductivity type impurity is introduced into said region to which said potential applying electrode is connected at a higher concentration than said well region. Transistor. 13. The field effect transistor according to claim 11, wherein a ground potential is applied to said constant potential applying electrode. 14. The channel region between the source electrode and the gate electrode and between the drain electrode and the gate electrode has a higher impurity concentration than a channel region immediately below the gate electrode, and has a higher impurity concentration than the source and drain regions. 2. The field effect transistor according to claim 1, wherein said first conductivity type LDD region having a low impurity concentration is provided. 15. The field effect transistor according to claim 1, wherein an element isolation region having the same conductivity type as the well region and having a higher concentration than the well region is provided on an outer periphery of the well region. . 16. A semiconductor integrated circuit device comprising a plurality of the field effect transistors according to claim 1 integrated in a compound semiconductor layer. 17. Among a plurality of integrated field effect transistors, those forming a circuit having a common output are connected to the well layers of the field effect transistors in a compound semiconductor layer. 17. The semiconductor integrated circuit device according to claim 16, wherein: 18. The method according to claim 18, wherein the plurality of field-effect transistors are:
17. The semiconductor integrated circuit device according to claim 16, wherein the semiconductor integrated circuit device is connected in series. 19. The semiconductor integrated circuit device according to claim 18, wherein said well regions of said series-connected field-effect transistors are electrically separated from each other. 20. A step of forming a second conductivity type well region in a compound semiconductor layer, and selectively introducing an impurity of a first conductivity type opposite to the second conductivity type into a region inside the well region. Forming a channel region shallower than the well region; selectively introducing impurities into a region inside the well region, shallower than the well region, and opposed to each other with the channel region interposed therebetween; Forming source and drain regions of the first conductivity type; applying a gate electrode material on the compound semiconductor layer; and forming a gate electrode material on the compound semiconductor layer inside the well region and facing the source and drain regions. While extending in the transverse direction,
Forming a gate mask of a pattern having a protrusion protruding outside the channel region on the gate electrode material; and selectively patterning the gate electrode by using the gate mask to pattern the gate electrode. And forming a source and drain electrode electrically connected to the source and drain regions. A method for manufacturing a field effect transistor, comprising: 21. The field effect transistor according to claim 20, wherein the periphery of said well region is defined to be 0.3 μm or more outside the periphery of said channel, source, drain region and gate mask. Manufacturing method. 22. The electric field according to claim 21, wherein a peripheral edge of said well region is defined outside the peripheral edge by 0.3 μm or more, in addition to an alignment margin of said channel, source, drain and gate mask. Manufacturing method of effect type transistor. 23. A step of forming a compound semiconductor layer of a second conductivity type, and selectively introducing an impurity of a first conductivity type opposite to the second conductivity type into the compound semiconductor layer to form a channel region. The step of selectively introducing the impurity of the first conductivity type into the compound semiconductor layer, forming source and drain regions opposed to each other with the channel region interposed therebetween, and forming a gate on the compound semiconductor layer. A step of applying an electrode material, and on the compound semiconductor layer, extending in a direction crossing a direction in which the source and drain regions face each other;
Forming a gate mask of a pattern having a protruding portion protruding outside the channel region on the gate electrode material; and selectively etching using the gate mask to form a gate electrode. Forming a source and drain electrode electrically connected to the source and drain regions.