JP3291374B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a wiring layout for transmitting an internal reference potential in a semiconductor memory device using an internal reference potential different from an external power supply voltage.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, it is necessary to recognize whether an external signal is at H level or L level. Generally, the following two methods are used for that purpose.

(1) Threshold adjustment method of logic circuit: The threshold voltage of the first-stage logic circuit to which an external signal is input is adjusted to an intermediate value of the input level standard value. If the level of the external signal is higher than the intermediate value, it is determined to be H level, and if lower, it is determined to be L level.

(2) Comparison method with internal reference potential: An internal reference potential VBREF is generated inside a semiconductor chip, and the internal reference potential VBREF is compared with the level of an external signal. If the level of the external signal is higher than the internal reference potential VBREF, it is determined to be H level, and if it is lower than the internal reference potential VBREF, it is determined to be L level. Incidentally, the internal reference potential VBREF is usually set at an intermediate value of the standard value of the input level of the external signal. For example, at the 5V TTL level, the H input level standard value V
The internal reference potential VBREF is calculated from IH and the L input level standard value VIL.
Is set.

VBREF = (VIH + VIL) / 2 = (2.4 + 0.8) /2=1.6 V (1) Of the above two methods, from the viewpoints of high speed, controllability, and stability, in recent years, The method (2) or the mixed method (1) (2) has been widely adopted.

For example, in a semiconductor memory device, a mixed method of (1) and (2) is adopted in a data input buffer and a row address buffer. FIG. 4 shows an example of a circuit arrangement on a chip in a semiconductor memory device.

On the semiconductor chip 51, a reference potential generating circuit 52, a memory cell 53, a data input buffer 54, a row address buffer 55, and a power supply pad VCC are arranged. The internal reference potential VBREF generated by the reference potential generation circuit 52 is supplied to the input buffer 5
4 and the row address buffer 55.

FIG. 5 shows an input circuit portion of the input buffer 54 or the row address buffer 55. This input circuit section is constituted by each of the MOS transistors 61 to 68. Then, an external signal Vin (data in the case of the input buffer 54, the row address buffer 5) is input to the input pad 69.
In the case of 5, the row address is applied. In this circuit, when φSIG becomes H level, the source of each of the NMOS transistors 67 and 68 becomes
The current difference between the drains is detected, and the PMOS transistor 6 is detected.
2 and 63, a sensing operation occurs, and a node 69
Data is taken into a and 69b.

FIG. 6 shows another example of the input circuit section of the input buffer 54 or the row address buffer 55. This input circuit section includes a CMOS inverter 71 and an NMOS transistor 72. Then, an external signal Vin (data in the case of the input buffer 54, row address in the case of the row address buffer 55) is applied to the input pad 69. In this case, the internal reference potential VBREF is equal to the H input level standard value VIH and the external signal V
It is set to a level slightly lower than the total value of in (VIH + Vin). In this circuit, the internal reference potential VBREF causes NM
By controlling the OS transistor 72, whether the external signal Vin is at the H level or the L level is determined by a constant threshold value regardless of the fluctuation of the high-potential-side power supply voltage VCC, thereby suppressing the through current during standby. Note that the internal reference potential VBR
EF is generated by a reference potential generating circuit 52a including a resistor R1, an NMOS transistor 81, and a diode D.

Incidentally, the internal reference potential VBREF is required to have stability during operation. In order to supply a stable internal reference potential VBREF, reference potential generation circuits 52 of various circuit types as shown in FIGS. 7 to 9 have been developed.

In the circuit shown in FIG. 7, inputs and outputs of a CMOS inverter are connected, and a PMOS transistor 82 is connected.
The high-potential power supply voltage VCC and the low-potential power supply voltage VSS
(Ground potential = 0 V) to generate a reference potential VBREF. This circuit has the disadvantage that the reference potential VBREF is highly dependent on the power supply voltage and the stability is poor, but has the advantage that the occupied area on the semiconductor chip is relatively small.

In the circuit shown in FIG. 8, the reference potential VBREF is generated by dividing the high-potential power supply voltage VCC and the low-potential power supply voltage VSS by the resistors R1 and R2. This circuit, similarly to the circuit shown in FIG. 7, has a drawback that the reference potential VBREF is highly dependent on the power supply voltage. Moreover, the resistance R1,
Since R2 has a larger occupied area on the semiconductor chip than transistors 81 and 82, the circuit shown in FIG. 8 also has a disadvantage that the occupied area is larger than the circuit shown in FIG.

In the circuit shown in FIG. 9, a plurality of diodes D are added in series between the resistor R2 and the low-potential-side power supply VSS (ground) in the circuit shown in FIG. The reference potential VBREF is generated by the resistance division by the resistors R1 and R2. Since this circuit utilizes the forward voltage drop caused by each diode D, it has a higher reference potential VBR than the circuit shown in FIG. 7 or FIG.
There is an advantage that the power supply voltage dependency of the EF is reduced.

The reference potential generating circuit 52a shown in FIG.
The resistor R2 of the circuit shown in FIG.
And can be said to be a combination type using the circuit shown in FIG. 7 and the circuit shown in FIG.

[0015]

By the way, in order to enhance the stability of the internal reference potential VBREF, the reference potential generation circuit 52
In addition to lowering the power supply voltage dependency, the noise resistance of the wiring 56 for transmitting the internal reference potential VBREF must be increased. For that purpose, it is necessary to reduce the coupling noise from the wiring adjacent to the wiring 56. Accordingly, the wiring layout of the wiring 56 must be considered, but no special consideration has been given in the past.

For example, as shown in FIG. 10, a wiring 91 (line width: 1.4 μm, line thickness: 0.9 mm) for transmitting a control signal SIG (a control signal for read and write operations) of a semiconductor memory device.
8 μm) and wiring 56 (line width: 1.4 μm, line thickness: 0.8 μm)
) May be adjacent to each other and the wiring interval may be extremely narrow (both wirings 91 and 56 are formed of the second-layer aluminum wiring, and the minimum value of the wiring interval is 1.4 μm).

In this case, as shown in FIG.
The internal reference potential V with respect to the potential fluctuation of SIG (maximum 4V)
BREF generates coupling noise of about 1/10 of that level (maximum 0.4 V). When such large coupling noise occurs, the input buffer 54 and the row address buffer 55 may malfunction.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to transmit an internal reference potential in a semiconductor device or a semiconductor memory device using an internal reference potential different from an external power supply voltage. An object of the present invention is to provide a semiconductor device or a semiconductor storage device capable of improving the noise resistance of wiring.

[0019]

[Means for Solving the Problems]

[0020]

[0021]

[0022]

According to the first aspect of the present invention, in a semiconductor memory device in which each buffer operates based on an internal reference potential different from an external power supply voltage, a wiring transmitting an internal reference potential and a potential in a read and write cycle vary. The gist of the present invention is to arrange a wiring whose potential does not fluctuate even in a read and write cycle between the wiring to be performed.

According to a second aspect of the present invention, in a semiconductor memory device in which each buffer operates based on an internal reference potential different from an external power supply voltage, a wiring for transmitting an internal reference potential and a potential in a read and write cycle vary. In addition to arranging the wiring whose potential does not fluctuate even in the read and write cycles between the wiring to be performed and the wiring that transmits the internal reference potential and the wiring whose potential fluctuates, the gist thereof is to I do.

[0025]

[Action]

According to the first aspect of the present invention, the wiring that transmits the internal reference potential is shielded by the non-variable wiring disposed between the wiring that transmits the internal reference potential and the wiring that changes the potential. . As a result, the noise resistance of the wiring transmitting the internal reference potential can be improved.

According to the second aspect of the present invention, the synergistic effect of the first or third aspect of the present invention provides:
The noise resistance of the wiring for transmitting the internal reference potential can be further improved.

[0028]

Embodiments of the present invention will be described below. In each embodiment, the same components and signals as those in the conventional example have the same reference numerals, and a detailed description thereof will be omitted.

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described. In this embodiment, by increasing the distance between the wiring 91 transmitting the control signal SIG and the wiring 56 transmitting the internal reference potential VBREF, the width of the wiring 56 is increased.
To reduce the coupling noise generated at the same time to increase the noise resistance.

FIG. 1 shows a wiring 91 (line width; 1.4 μm, line thickness: 0.8 μm) and a wiring 56 (line width: 1.4 μm, line thickness;
8 μm) shows the change in coupling noise when the interval is changed. Note that both the wirings 91 and 56 are formed of a second-layer aluminum wiring. Further, as shown in FIG. 11, the maximum potential fluctuation of the control signal SIG is 4 V, and FIG.
As shown by 0, the coupling noise is 1 when the minimum value of the wiring interval is 1.4 μm.

As can be seen from FIG. 1, the coupling noise is sharply reduced by increasing the wiring interval. When a plurality of wirings including the wiring 56 run at the same interval, a wiring having a large potential variation (for example, a wiring for transmitting a control signal for read and write operations) and a wiring 56
As wide as possible. As a result, noise resistance can be improved without increasing the area occupied by the semiconductor chip.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described. In the present embodiment, coupling noise generated in the wiring 56 is reduced by arranging a wiring whose potential does not fluctuate between the wiring 91 transmitting the control signal SIG and the wiring 56 transmitting the internal reference potential VBREF. Reduce and increase noise resistance.

For example, as shown in FIG. 2, a wiring 11 for supplying a low-potential-side power supply VSS is provided between a wiring 91 and a wiring 56.
(Ground wire). The low-potential-side power supply VSS is applied from the outside, and the potential VSS is always 0 V without fluctuating depending on the operation state of the semiconductor memory device. Therefore, coupling noise generated in the wiring 56 can be reduced by the shielding effect of the wiring 11.

As shown in FIG. 3, a wiring 12 for transmitting an internal reference potential VINTREF different from the internal reference potential VBREF is arranged between the wiring 91 and the wiring 56. Internal reference potential VINTREF is generated by a reference potential generation circuit different from reference potential generation circuit 52, and the potential is always constant without fluctuating depending on the operation state of the semiconductor memory device.
Therefore, similarly to the case where the wiring 11 is arranged, coupling noise generated in the wiring 56 can be reduced.
However, in this case, coupling noise occurs in the wiring 12. Therefore, in practice, each wiring 1
It is necessary to determine the arrangement according to the priority of noise reduction with respect to 1 and 12.

Further, a wiring for supplying the high-potential-side power supply VCC is provided between the wiring 91 and the wiring 56. The high-potential-side power supply VCC is applied from the outside, and the potential VCC is always constant without changing depending on the operation state of the semiconductor memory device. Therefore, as in the case where the wiring 11 is arranged, the wiring 5
6 can be reduced.

In recent years, in semiconductor memory devices, it has been required to lower the power supply voltage in order to reduce power consumption and achieve higher integration.
The V system is shifting to the 3.3 V system. However, there are some users who wish to use the 5V system as before. Therefore, the external power supply voltage (5
V) is generated to generate an internal power supply voltage. In this case, between the wiring 91 and the wiring 56,
By arranging the wiring for supplying the internal power supply voltage, it is possible to obtain the same effects as those of the above examples.

The present invention is not limited to the above embodiments, and for example, the first embodiment and the second embodiment may be used in combination. In that case, the noise resistance of the wiring 56 can be further improved by the synergistic effect of the two embodiments .

[0038]

As described in detail above, according to the present invention, a semiconductor memory using an internal reference potential different from the external power supply voltage is used.
In the storage device , there is an excellent effect that the noise resistance of the wiring for transmitting the internal reference potential can be improved.

[Brief description of the drawings]

FIG. 1 is a measurement diagram for explaining the effect of the first embodiment.

FIG. 2 is a plan view for explaining a second embodiment.

FIG. 3 is a plan view for explaining a second embodiment.

FIG. 4 is a plan view showing an example of a circuit arrangement on a chip in the semiconductor memory device.

FIG. 5 is a circuit diagram showing an input circuit section of the input buffer 54 or the row address buffer 55.

FIG. 6 is a circuit diagram showing an input circuit unit of the input buffer 54 or the row address buffer 55.

FIG. 7 is a circuit diagram of a reference potential generation circuit 52;

FIG. 8 is a circuit diagram of a reference potential generation circuit 52;

FIG. 9 is a circuit diagram of a reference potential generation circuit 52;

FIG. 10 is a plan view showing a wiring layout of a conventional wiring 56 for transmitting an internal reference potential.

FIG. 11 is a waveform chart for explaining coupling noise generated in a wiring 56 for transmitting an internal reference potential.

[Explanation of symbols]

 11, 12 Wiring without potential fluctuation 54 Input buffer 55 Low address buffer 56 Wiring for transmitting internal reference potential 91 Wiring with potential fluctuation VCC External power supply voltage (high-potential-side power supply voltage) VBREF Internal reference potential

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Kiwawa Hamakawa 2-18-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (56) References JP-A-4-207707 (JP, A) JP-A JP-A-4-196226 (JP, A) JP-A-5-226340 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/822 G11C 11/401 G11C 11/41 H01L 27 / 04

Claims (2)

(57) [Claims] 1. A method in which each buffer is different from an external power supply voltage.
In semiconductor memory devices that operate based on local reference potentials
Wiring to transmit the internal reference potential, and read and write
Lead between the wiring whose potential fluctuates in the cycle
And wiring whose potential does not fluctuate even in the write cycle
A semiconductor memory device characterized by disposing. 2. The method according to claim 1, wherein each buffer is different from an external power supply voltage.
In semiconductor memory devices that operate based on local reference potentials
Wiring to transmit the internal reference potential, and read and write
Lead between the wiring where the potential fluctuates in the cycle
And wiring whose potential does not fluctuate even in the write cycle
In addition to arranging the internal reference potential,
The feature is to increase the distance between the line and the line where the potential fluctuates.
Semiconductor storage device.