JP3292966B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an insulated gate type field effect semiconductor device comprising a source region, a drain region, and a gate electrode provided between the two regions via a gate insulating film. The present invention relates to, for example, a latch-type static memory or a sense amplifier circuit in which a plurality of are arranged symmetrically with each other so as to form a balanced flip-flop.

[0002]

2. Description of the Related Art Conventional CMOS (Complementary Met)
A highly integrated latch-type static random access memory (hereinafter, abbreviated as SRAM) having an al oxide semiconductor (structure) is composed of memory cells having a circuit configuration as shown in FIG.

[0003] The memory cell circuit to symmetrically arranged power Vss ₁ or Vss ₂ side of the N-channel MO mutually
It has S transistors N ₁ and N ₂ and P-channel MOS transistors P ₁ and P ₂ on the power supply Vdd ₁ or Vdd ₂ side symmetrically arranged, and these transistors N ₁ , N ₂ , P _{2 1,} a CMOS flip-flop, respectively the input and output of the CMOS inverter pair by hand is connected to P _2, which are cross-connected balanced to each other,
And N-channel MOS transfer transistors denoted by X ₁ and X ₂ .

[0004] Then, the word line W / L ₁ or W / L
Input from the bit line B / L ₁ or B / L ₂ through the transistor X ₁ or X ₂ selected by ₂ is held in the node Q or Q ', writing of information is performed. In addition, information is read by the reverse operation.

[0005] That is, when information is "1" (the node Q is high = Vdd level), the conduction P ₁ and N _2, a N ₁ and P ₂ is non-conductive, also information is "0 when "(the node Q is at a low level = Vss level), P ₁ and N ₂ being in the non-conducting and conducting N ₁ and P ₂ are. As a result, in this cell, the current consumption other than the leakage current component during standby is Vdd-V
Since the current does not flow between ss, extremely low standby power consumption can be realized.

The layout of this memory cell is shown in FIG. 13 (for one memory cell) and FIG. 14 (in a state where many memory cells are incorporated). 1, 2, 3, 4, 5, 6,
Reference numerals 7 and 8 denote N ⁺ -type semiconductor regions serving as source or drain regions of each N-channel MOS transistor, respectively.
Reference numerals 9, 10, 11 and 12 denote P ⁺ -type semiconductor regions which serve as source or drain regions of the respective P-channel MOS transistors.

The transistors P ₁ and N ₁ and the transistors P ₂ and N ₂ have the same gates G ₁ and G ₂ , and these gates are formed of TiN called a local interconnect.
The transistors P ₂ , N ₂ ,
X ₂ , P ₁ , N ₁ , and X ₁ semiconductor regions 11, 4, 7,
9, 2, and 5, respectively. A P ⁺ type semiconductor region 13 is provided adjacent to an end of the semiconductor region 3 (source region) of the transistor N ₂ as a substrate electrode for substrate contact for fixing the substrate potential to Vss (a PN junction is formed). T) is formed.

Such memory cells M-CEL are integrated at a high density as shown in FIG. 14, adjacent memory cells are symmetrical to each other, and have a predetermined semiconductor region and a power supply line for Vss or Vdd (not shown). Is shared.

In the above memory cell layout, FIG.
As clearly shown in FIG. 13, in order to reduce the cell area, the MOS transistors N ₁ and N ₂ forming the cell latch must have a structure in which the moat grounded to the power supply is separated (that is, the semiconductor region 3 and the MOS transistor N ₂₎ . 1) and a substrate contact (P ⁺ type semiconductor region 13) is provided only on one side (semiconductor region 3).

[0010]

Heretofore, it has been thought that the substrate contact 13 is merely for fixing the substrate to a power source and maintaining the electrical stability of the substrate. However, as shown in FIG. 15, the high-concentration N ⁺ -type silicon (source region) 3 and the high-concentration P ⁺ -type silicon (semiconductor region) 13 are joined, and the upper portion is electrically connected by a silicide layer 76 of TiSi ₂ or the like. to be short-circuited, when the structure is connected to the power supply Vss ₂ via the electrode 53 of tungsten or the like, revealed significant impact in reducing the Vss contact resistance of the source side of the MOS transistor N _2. Incidentally, the silicide layer 77,58 is also provided on the drain region 4 and the polysilicon gate electrode G _2, also 47 in the figure P ^- -type silicon substrate, 87 N ^-
The mold well region 50 is a sidewall such as a nitride.

[0011] The short-circuit structure by the silicide layer 76 is V
The reason that has a great effect on the reduction of ss contact resistance is that
High concentration N ⁺ type silicon 3 and high concentration P ⁺ type silicon 13
When the Schottky barrier between the N ⁺ -type silicon layer 3 and the silicide layer 76 is high due to a process variation, a channel current (drain current) 120 flows through the Zener diode ZD. The current flows to the Schottky diode SD between the low-resistance P ⁺ -type silicon 13-silicide layer 76, which eventually flows to the Vss ₂ current, thereby substantially reducing the substantial Vss contact resistance of the source. It is thought that this would lead to

Referring to FIG. 16, the above phenomenon is described in terms of a circuit. R _NS and R _NS ′ in the figure are the contact resistance (30 to 1 kΩ) between the source region 3 or the source region 1 and the silicide layer 76. , R _PS is the contact resistance (about 10Ω) between the semiconductor region 13 and the silicide layer 76, and Rz is the source region 3 and the semiconductor region 13
Resistance (Zener diode resistance) (100Ω
) And R _SUB is the bulk resistance (about 10 kΩ) of the silicon substrate including the semiconductor region 13. Therefore, the resistance of the Zener diode ZD and the semiconductor region 13-silicide layer 76
If the resistance R _PS between them is much smaller than the resistance R _NS between the source region 3 and the silicide layer 76, the current 120 mainly flows to the power supply through the Zener diode ZD. This diode current can be 1 mA or more, which means that the transistor drive current is several hundred μA (1
mA), the channel current is sufficiently absorbed.

These phenomena were quantitatively measured as follows. That is, in the structure shown in FIG. 15, the two regions 3 and 13 are formed independently as shown in FIGS.
Is a field oxide film, and 49 is an electrically significant difference as compared with the gate insulating film. As shown in Table 1 below, M
It has been found that the threshold voltage of the OS transistor brings about a difference of about 0.2 V and the current driving capacity brings about a difference of about 15%.

[0014] * Sum of diffusion resistance of source and drain regions * With P ⁺ / N ⁺ Zener diode (Fig. 15) *** Without Zener diode (however, P ⁺ /
P ^- / N ⁺ diode present) (FIG. 17)

These phenomena have been elucidated by the present inventors as follows. First, the substrate electrode (P ⁺ type region 13) is
Moat for source electrode of S transistor (source region 3)
In the case of the structure shown in FIG.
In 47, the moat for the substrate electrode is formed of high-concentration P ⁺ -type silicon 13 (impurity doping amount is 1 × 10 ²⁰ / cm ³ ), while the moat for the source of the MOS transistor is formed of high-concentration N ⁺ Type silicon 3 (impurity doping amount is 1 × 10
²¹ / cm ³ ), but when these two types of silicon are joined adjacently, a so-called Zener diode Z is formed.
D is formed (see FIG. 19). The profile of the impurity concentration shown in FIG.
Determined by TSUPREM4 (manufactured by TMA),
The work function of silicide is obtained by converting the work function value of ordinary TiSi ₂ into a two-dimensional device simulator: MEDICI (TMA
(The same applies hereinafter).

Although this Zener diode has a size of about 0.1 μm, as shown in FIG. 20, it has a property of flowing a current of 1 mA or more by tunneling at a reverse bias of 0.1 V. In contrast, the substrate electrode moat 13 is
In the case of FIG. 17, which is provided separately from the moat 3 for the source electrode of the OS transistor, as shown in FIG. 21, the junction of ordinary N-type silicon and low-concentration P-type silicon is obtained, and as shown in FIG. No current flows in a normal reverse bias state.
It is considered that such a difference in voltage-current characteristics greatly affects the operation of the MOS transistor, and appears as a difference in current driving capability as shown in Table 1 above.

Next, in the memory cell shown in FIGS. 13 to 15, although the substrate contacts 13 on only one side (Vss ₂ side) is installed as described above, without the substrate contact side (Vss ₁ On the side), although the silicide layer is provided on the surface of the source region 1, when the Schottky barrier between the source region 1 and the silicide layer becomes higher, the potential of the N ⁺ type silicon 1 becomes lower than the substrate potential due to the Schottky barrier. Will also emerge. As a result, the threshold voltage of the MOS transistor N1 rises higher than the threshold voltage of the MOS transistor N2 with the zener diode, the electrical symmetry of the cell latch is broken, and the cell data is easily destroyed on the high Vcc side. This phenomenon has been found to cause a problem of significantly lowering the performance of the device.

This problem has been solved as follows.
First, as a problem of the MOS transistor having the source and drain regions whose surfaces are metallized (silicided) by the self-aligned silicide process, there is a problem with silicide and highly doped silicon (ie, silicon).
A sufficient ohmic characteristic and a sufficiently low resistance cannot be obtained due to the Schottky barrier with the above region 3).

Since it is difficult to evaluate such ohmic characteristics, a device may be manufactured without noticing the above problem. As a result, when sufficient ohmic characteristics cannot be obtained at the interface between silicide and silicon, or when a sufficiently low contact resistance cannot be obtained, the moat for the substrate electrode becomes the moat for the source electrode of the MOS transistor. In the MOS transistor N1 which is not provided adjacent to the MOS transistor N1, a phenomenon occurs in which the source-side region rises with respect to the silicide forming the Schottky junction.

That is, this is connected to a transistor N1 and a transistor N3 (G
₁ 'is the gate electrode, 2' is the drain region)
Referring to FIG. 25, when one transistor N1 is turned off and the other transistor N3 is operated during driving as shown in FIG. 23B, a channel current (drain current) flows into the source region 1. After that, it can be seen that it has spread considerably within the same area. The data in FIGS. 23 to 25 is a two-dimensional device simulator: MEDICI (T
MA Co., Ltd.).

That is, when N1 is off and N3 is on (FIG. 23B, FIG. 25), the equipotential level layers 60, 61, 62, 63 formed in the source region 1 (There is a potential difference of about 0.1 V between the potential level layers: the same applies to the following layers.) Of the current flowing in by turning on N3, the potential rises near the channel end like the layer 63 (and further the layer 64). At the same time, a potential rise of about 0.2 V is observed at the channel end of the turned off N1 like the layer 65 (see FIG. 25). In other words, it can be seen that the potential of the silicon region 1 under the silicide layer 76 rises above Vss even if only a normal Schottky barrier is assumed.

Then, in this state, as shown in FIG.
When N1 is turned on while turning on No. 3 and the driving current is compared with the driving current of N3 before that, deterioration of about 15% is seen. This is because the source potential of N1 rises because N3 is turned on (see FIG. 25), and as shown in FIG. 23B, the potential near the channel end on the N1 side is caused by the channel current of N3 as shown in layer 63. (The result is a rise of about 0.2 V: the effective threshold is about 0.2 V)
(Equivalent to a rise in V).

This will be described with reference to FIGS. 26 and 27.
When only N3 and N1 are on, B indicates that both N3 and N1 are on. However, the rise of the potential of the source region is substantially equal to the rise of the source potential, and FIG.
As shown in the figure, when the MOS is turned on, the drive current is
Since it is constant in the OS, it is equal to the fact that the threshold voltage of N1 has effectively increased from V _{th1 to} V _th2 . Also, the potential rise of the source side region is MOS
The larger the drive current, the more remarkable it becomes.
As shown at 27, the maximum drive current is significantly degraded (ie, the drive current is much smaller in N1 than in N3 when compared at the same V _th ).

As described above, in the cell structure as shown in FIGS. 13 to 15, the threshold value of the transistor N1 is easily increased by the silicification, and the adjacent transistor N3 (for example, a virtual line in FIG. (Transfer transistors as shown in the figure) are connected (interference by neighboring cells). Even if the transistor N3 does not exist, it is understood from the above description that even with the transistor N1 alone, the source potential rises above Vss due to the Schottky barrier due to the silicification.

Such a rise in the potential, that is, an increase in the threshold potential of the transistor N1, has a bad influence on the memory performance, and cell data is easily destroyed. This will be described with reference to FIG. 12. When the node Q is at a high level (information "1").
When the transistor N1 is turned on to a low level (information "0") from the state described above, the transistor N1 does not turn on even if the node Q 'is at a high level because the threshold value of the transistor N1 is high. However, at this time, although the node Q 'should be already at the high level and the node Q should be at the low level, the transistor N2 is turned on because the node Q still maintains the high level, and the node Q' high levels Vss ₂ levels (i.e., low level) decreases to. As a result, the node Q ′ goes low in a state where the node Q does not easily go low, and the data to be written into the memory is destroyed.

[0026]

SUMMARY OF THE INVENTION It is an object of the present invention to improve the data holding ability and the current driving ability of a static memory cell and the like, improve the margin of a device manufacturing process,
It is to improve the performance of the device.

[0027]

That is, the present invention provides an insulated gate type field effect semiconductor device comprising a source region, a drain region, and a gate electrode provided between the two regions via a gate insulating film. A plurality of circuits are arranged so as to maintain symmetry with each other in a circuit (for example, to form a balanced flip-flop), and adjacent to each source region or drain region, have opposite conductivity to the source region or the drain region. Semiconductor regions are formed, Zener diodes are respectively formed between the two regions, and each of these Zener diodes is connected between the respective source region or drain region and the power supply or the ground side. The present invention relates to a semiconductor device.

According to the semiconductor device of the present invention, in a balanced flip-flop such as a static memory cell constituted by MOS transistors, a Zener diode is symmetrically provided in a source region (or a drain region) of a paired transistor. This is achieved by arranging these Zener diodes between a source region (or a drain region) and a power supply or a ground side. Due to these pairs of Zener diodes, the cell margin is reduced due to the asymmetry inherent in the structure in which the moat connected to the power supply is separated as described above in order to reduce the cell area. Can be greatly improved. That is,
With this configuration, a current to each source region (or drain region) of a paired transistor effectively flows to the power supply or the ground side via the Zener diode by the tunneling effect described above, so that the source region (or the drain region)
As described above, the floating of the potential can be reduced, and the rise of the threshold value of the transistor can be suppressed, whereby the symmetry of the pair of transistors can be maintained, and the performance of the memory cell such as the data holding ability and the current driving ability can be improved. Can be enhanced.

Accordingly, the semiconductor device of the present invention constitutes a latch type static memory cell, and a Zener diode is formed in each source region of a pair of insulated gate type field effect semiconductor elements forming a cell latch of the memory cell. Or a sense amplifier circuit, and a Zener diode is provided between each of the source regions of the pair of insulated gate type field effect semiconductor elements connected to the discharge circuit section of the sense amplifier circuit and the discharge circuit section. It is suitable when connected.

In the semiconductor device of the present invention, the respective source regions of the pair of insulated gate type field effect semiconductor elements can be separately or commonly connected to a power supply or a ground via a Zener diode.

In addition, the semiconductor region of the opposite conductivity type is formed adjacent to each source region, and this semiconductor region is connected between the power source of each source region and the semiconductor base, and the potential of the semiconductor substrate (for example, Vss ) Can be used for fixing, so that the degree of integration of the device can be improved and the device can be miniaturized.

As a structure for providing a power supply contact, a silicide layer is formed over each surface of the source region and the semiconductor region of the opposite conductivity type, and a power supply or ground side contact is provided in the silicide layer. Alternatively, separate power supply or ground side contacts may be separately provided for the source region and the opposite conductivity type semiconductor region, and further, the source region and the opposite conductivity type semiconductor region may be provided separately. May be provided with a common power supply or ground side contact.

In the case where the silicide layer (eg, TiSi ₂ ) is formed, even if sufficient ohmic characteristics or low contact resistance cannot be obtained at the interface between silicide and silicon as described above, the reverse contact is made adjacent to the source region. Since a conductive type semiconductor region is formed and connected to a power supply or a ground side via the Zener diode, floating of the potential of the source region can be effectively prevented, and a problem due to a Schottky barrier due to the silicide layer is eliminated. Can be eliminated.

Therefore, by forming the silicide layer, the device can be miniaturized, and at the same time, the restricted device manufacturing conditions required to suppress the Schottky barrier (ie, the power supply contact resistance with respect to the source) are as follows. This becomes unnecessary or is alleviated, so that the manufacturing process can have a margin. In particular, a large margin can be obtained with respect to fluctuations in the conditions of silicidation, fluctuations in the surface concentration of the source and drain, and fluctuations during the formation of contacts, thereby increasing the quality of highly integrated devices. It is possible to produce at a yield.

[0035]

Embodiments of the present invention will be described below.

Embodiment 1 FIGS. 1 to 5 show a latch type static memory (S) according to the present invention.
1 shows a first embodiment applied to a (RAM).

The layout of the memory cell of the SRAM according to the present embodiment is, as shown in FIGS.
14 are denoted by the same reference numerals and description thereof may be omitted, but as a fundamentally different configuration, a pair of MOS transistors N2 forming a cell latch
And N1, P ⁺ type semiconductor regions (substrate contacts) 13 and 83 are formed adjacent to the source regions 3 and 1, respectively, and the same Zener diodes ZD and ZD ′ as described above are connected to the respective source regions. Area and power supply Vss ₂
And that connected between the Vss _1. In this example, the transistors N1 and N2 are provided on a P ⁻ -type substrate, and the transistors P1 and P2 are provided on an N-type well region.

FIGS. 3 and 4 are cross-sectional views each showing a portion provided with the above-described Zener diodes ZD and ZD '. FIG. 3 shows a transistor N2 portion similar to that described with reference to FIG. 80 an interlayer insulating film in the drawing), also conventional in FIG. 4 fundamentally changed simply a structure has been provided a silicide layer 76 on the source region 1 of the transistor N1, the same as FIG. 3 here also P ⁺ A type semiconductor region 83 is provided adjacently to form a Zener diode ZD ′ (however, 93 in FIG.
Power Vss ₁ of the electrodes).

FIG. 5 shows a pair of transistors N2 and N1.
Although the equivalent circuit of the portion is shown, compared with the circuit of FIG.
The diode resistance R _Z ′ by the Zener diode ZD ′, the contact resistances R _NS ′ and R _PS ′ with the silicide layer, and the substrate bulk resistance R _SUB ′ are also connected to the transistor N 1 side symmetrically to the transistor N 2 side, respectively ( These resistors are respectively equivalent to those of the transistor N2).

As described above, according to the present embodiment, the Zener diodes ZD and ZD 'are symmetrically arranged in both the transistors N2 and N1 forming a pair of the memory cells.
The current to each of the source regions 3 and 1 of the transistors N2 and N1 is changed by the tunneling effect as described above.
D, since the effective flow to the power supply Vss _2, Vss ₁ side through the ZD ', to reduce the lifting of the above potentials of the source regions 1, it is possible to suppress an increase in the threshold of the transistor N1.

[0041] Thus, in a write operation of data, on the transistor N1 is normally off and the low level by grounding the node Q by turning on the transistor N1 when a node Q 'becomes high level to Vss ₁ side (Information “0”), and the high level of the node Q ′ can be held by turning off the transistor N2. Thus, the data to be written to the memory is not destroyed, and the data holding ability can be improved.

By forming the silicide layers 76 and 77, the device can be miniaturized, and at the same time, the Schottky barrier (that is, the power supply contact resistance with respect to the source) described above
The restricted device manufacturing conditions required to suppress the problem become unnecessary or relaxed, so that the manufacturing process can have a margin. In particular, a large margin can be obtained with respect to fluctuations in the conditions of silicidation, fluctuations in the surface concentration of the source and drain, and fluctuations during the formation of contacts, thereby increasing the quality of highly integrated devices. It is possible to produce at a yield.

Embodiment 2 FIG. 6 shows a second embodiment of the present invention.

In this embodiment, unlike the first embodiment, a power contact is provided without providing a silicide layer. That is, in each of the transistors N2 and N1, V
They are taken separately ss ₂ or Vss ₁ for the contact 53a, 53b and the source region 3 or 1 and the semiconductor region 13 or 83.

That is, the source region 3 or 1 is in contact with
53a has a contact 53b with the P ⁺ type semiconductor region 13 or 83.
Are connected respectively. These can be connected at different points and lead to a common power supply wiring.

With such a structure, the same operation and effect as described in the first embodiment can be obtained. In addition, since the silicide layer is not provided, the problem due to the Schottky barrier does not need to be taken into consideration. Integration can be realized.

Embodiment 3 FIG. 7 shows a third embodiment of the present invention.

In the case of this example, the power supply contact 53 is enlarged in contrast to the separate power supply contact in the second embodiment, and is shared by the source region 3 or 1 and the semiconductor region 13 or 83.

According to this embodiment, the same operation and effect as those described in the first and second embodiments can be obtained, and the contact can be easily formed by the common power supply contact.

Embodiment 4 FIG. 8 shows a fourth embodiment of the present invention.

In each of the first to third embodiments, the structure in which the source region and the substrate contact region are adjacent to each other has been described. However, the adjacent structure and the independent structure as shown in FIG. Alternatively, they may be all independent structures.

That is, in order to connect the Zener diode to the source region 3 or 1, the entire periphery of the P ⁺ type semiconductor region 81 of the opposite conductivity type is surrounded by the source region 3 or 1. The P ⁺ type semiconductor region 13 or 83 for substrate contact is provided at another position (not shown).

Even with such a configuration, the same operation and effect as described in the first embodiment can be obtained by the Zener diode ZD or ZD '.

Embodiment 5 FIGS. 9 and 10 show a fifth embodiment of the present invention.

In the SRAM memory cell of this embodiment, the source regions of the transistors N1 and N2 are common to the first embodiment, and a P ⁺ type semiconductor region 13 is provided adjacent to the common source region 1. A zener diode (N ⁺ / P ⁺ ZD) is formed between them, and is connected to the power supply Vss in the same manner as described with reference to FIG. 3 (however, the silicide layer 76 is not shown). On the other hand, transistors P1, P
2 also has a common source region, an N ⁺ type semiconductor region 93 is provided adjacent to the common source region 9, a Zener diode (P ⁺ / N ⁺ ZD) is formed between them, and the power source Vcc They are commonly connected (however, a silicide layer is not shown).

Therefore, the floating of the potential of the source region 1 can be reduced by the above-mentioned common N ⁺ / P ⁺ ZD, the symmetry of the transistors N1 and N2 can be maintained, and the data holding ability can be increased. Then, the above common P ⁺ / N
The floating of the potential of the drain region 9 is reduced by ⁺ ZD.

With such a structure, the same operation and effect as those described in the first embodiment can be obtained, and even if the source regions of the pair of transistors are connected to the power supply in common, the above-mentioned Zener diode can be used. Since the current driving capability is improved, the device can be operated with high reliability.

Embodiment 6 FIG. 11 shows a sixth embodiment of the present invention.

In this example, the present invention is applied to a sense amplifier circuit which also requires electrical symmetry in place of the SRAM described above. This sense amplifier circuit is composed of a flip-flop circuit as shown in FIG.
When a small potential difference occurs between L ₁ and B / L ₂ , the potential of S ₂ is gradually lowered to activate the sense amplifier.
Left and right nodes a, of b, potential lower amount is discharged through the transistor Q ₅ or Q _6, the potential difference is amplified. When a sufficient potential difference occurs between nodes a and b,
The S ₂ rapidly lowered to 0V to complete 0V and the low potential side,
Subsequently, the recharge circuit is operated to recharge only the bit line on the high potential side to the Vcc level. In this way,
After the sense amplifier determines “H” and “L” for the left and right bit lines having a small potential difference, the “H” side bit line potential is set to the complete “H” level, and the “L” side The bit line is set to the complete "L" level, and this data is written into the memory cell again (= rewrite and refresh).

In this sense amplifier circuit, the above-mentioned N ⁺ / P ⁺ ZD is connected to the common source region on the discharge circuit side of the transistors Q ₅ and Q ₆ , and the power supply side of the transistors Q ₁ and Q ₂ is connected. As described above, the drain region also has P
⁺ / N ⁺ ZD. Therefore, also in this example, it is possible to improve the current driving capability while maintaining the symmetry of the transistor operation by these zener diodes, and perform good sensing.

Although the embodiments of the present invention have been described above, these embodiments can be further modified based on the technical idea of the present invention.

For example, the size and layout of each semiconductor region forming the above-mentioned Zener diode, and
The configuration of the S-transistor, the material of each part, the manufacturing process, its conditions, and the like may be variously changed. Further, the conductivity type of the above-described semiconductor region can be changed to a reverse type.

The present invention may be applied to devices other than the CMOS device or the SRAM device other than those described above, and may be applied to other various devices. For example, SRAM
Can be applied to a known high-resistance load type or E / D type.
The present invention may be applied to an AM (for example, an N-channel MOS formed on a silicon substrate and a P-channel MOS of a TFT formed on a silicon substrate).

[0064]

As described above, according to the present invention, a plurality of insulated gate type field effect semiconductor elements are arranged so as to maintain symmetry with each other in circuit (for example, to constitute a balanced flip-flop). A semiconductor region of the opposite conductivity type is formed adjacent to each source region or drain, and a Zener diode is respectively formed between the two regions. Each of these Zener diodes is connected to the respective source region or drain region and a power supply or Since it is configured to be connected to the ground side, the current to each source region or drain region of the paired semiconductor element effectively flows to the power supply or the ground side via the Zener diode due to the tunneling effect, To reduce the rise in the potential of the source or drain region and suppress a rise in the threshold voltage of the transistor Can, thereby retaining the symmetry of the semiconductor device of the pair, the performance such as data retention capability and current driving capability of the memory cell can be enhanced.

The semiconductor region of the opposite conductivity type forming the Zener diode is adjacent to the source region. This is connected between the power supply of the source region and the semiconductor substrate to fix the potential of the semiconductor substrate. When used in such a case, the degree of integration of the device can be improved and the device can be miniaturized.

When a silicide layer is formed over the surfaces of the source region and the semiconductor region of the opposite conductivity type, the device can be miniaturized, and at the same time, the Schottky barrier (that is, the power supply contact resistance with respect to the source) can be obtained. ) Becomes unnecessary or alleviated, and the manufacturing process can have a margin. In particular, a large margin can be obtained with respect to fluctuations in the conditions of silicidation, fluctuations in the surface concentration of the source and drain, and fluctuations during the formation of contacts, thereby increasing the quality of highly integrated devices. It is possible to produce at a yield.

[Brief description of the drawings]

FIG. 1 shows a latch type SRAM according to a first embodiment of the present invention.
3 is a schematic plan view of the memory cell of FIG.

FIG. 2 is a schematic plan view of a memory cell section incorporating a large number of the memory cells.

FIG. 3 is a sectional view taken along the line III-III of FIGS. 1 and 2;

FIG. 4 is a sectional view taken along the line IV-IV in FIGS. 1 and 2;

FIG. 5 is an equivalent circuit diagram of a main part of the memory cell.

FIG. 6 shows an MO of a memory cell according to a second embodiment of the present invention;
FIG. 4 is an enlarged schematic cross-sectional view of a portion illustrating a current path through a Zener diode in an S transistor.

FIG. 7 shows an MO of a memory cell according to a third embodiment of the present invention;
FIG. 4 is an enlarged schematic cross-sectional view of a portion illustrating a current path through a Zener diode in an S transistor.

FIG. 8 shows an MO of a memory cell according to a fourth embodiment of the present invention;
FIG. 4 is an enlarged schematic cross-sectional view of a portion illustrating a current path through a Zener diode in an S transistor.

FIG. 9 shows a latch type SRAM according to a fifth embodiment of the present invention.
3 is a schematic plan view of the memory cell of FIG.

FIG. 10 is an equivalent circuit diagram of a main part of the memory cell.

FIG. 11 is an equivalent circuit diagram of a sense amplifier according to a sixth embodiment of the present invention.

FIG. 12 is an equivalent circuit diagram of a memory cell of a conventional latch type SRAM.

FIG. 13 is a schematic plan view of the memory cell.

FIG. 14 is a schematic plan view of a memory cell unit incorporating a large number of the memory cells.

FIG. 15 is an enlarged schematic cross-sectional view partially illustrating a current path through a Zener diode in a MOS transistor of the memory cell.

FIG. 16 is an equivalent circuit diagram of a main part of the memory cell.

FIG. 17 is a schematic sectional view of a conventional MOS transistor.

FIG. 18 is an equivalent circuit diagram of a main part of a memory cell incorporating the transistor.

19 is an impurity concentration profile diagram of a Zener diode portion of the MOS transistor of FIG.

FIG. 20 is a graph showing a potential of a Zener diode portion of the MOS transistor and a diode current.

FIG. 21 is an impurity concentration profile diagram of a diode portion of a MOS transistor having no Zener diode.

FIG. 22 is a graph showing a potential of a diode portion of the MOS transistor and a diode current.

FIG. 23 is a schematic cross-sectional view with a potential distribution for explaining a floating phenomenon of a source potential of a MOS transistor.

FIG. 24 is a potential distribution diagram when a plurality of MOS transistors are off.

FIG. 25 is a potential distribution diagram when one of the plurality of MOS transistors is turned on.

FIG. 26 shows that the drive current of the plurality of MOS transistors is lo
It is a graph shown on a g scale.

FIG. 27 is a graph showing drive currents of the plurality of MOS transistors on a linear scale.

[Explanation of symbols]

1, 2, 3, 4, 5, 6, 7, 8... N ⁺ type semiconductor region (source or drain region) 9, 10, 11, 12... P ⁺ type semiconductor region (source or drain region) 13,83 ··· P ⁺ -type semiconductor region (substrate contact) 47 ... P ^- -type silicon substrate 53,93 ... electrode or contact 76, 77 ... silicide layer 87 ... N ^- -type well region N1, N2, N3, P1, P2, X1, X2... MO
S transistors G _1, G ₂ ··· gate electrode LI · · · connecting conductor ZD, ZD '··· zener diode _{Vss 1, Vss 2, Vdd 1} , Vdd 2 ··· Power B / L _1, B / L ₂ ··· bit line _{W / L 1, W / L} 2 ··· word line

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-63-99562 (JP, A) JP-A-4-11769 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8234 H01L 27/088 H01L 21/8244 H01L 27/11

Claims (8)

(57) [Claims] A plurality of insulated gate field effect semiconductor devices each comprising a source region, a drain region, and a gate electrode provided between the two regions with a gate insulating film interposed therebetween have a symmetrical circuit structure. Is arranged to hold the
A semiconductor region of the opposite conductivity type to the source region or the drain region is formed adjacent to the source region or the drain region, and a Zener diode is formed between the two regions. Each Zener diode is connected to the source region. A semiconductor device configured to be connected between a region or a drain region and a power supply or a ground side. 2. A latch type static memory cell, wherein a Zener diode is formed in each source region of a pair of insulated gate field effect semiconductor elements forming a cell latch of the memory cell. The described semiconductor memory device. 3. A sense amplifier circuit, wherein a Zener diode is provided between each of the source regions of a pair of insulated gate type field effect semiconductor elements connected to a discharge circuit portion of the sense amplifier circuit and the discharge circuit portion. The semiconductor device according to claim 1, which is connected. 4. The pair of insulated gate field effect semiconductor devices according to claim 1, wherein respective source regions are separately or commonly connected to a power supply or a ground via a Zener diode. 2. The semiconductor device according to 1. 5. The semiconductor device according to claim 1, wherein the semiconductor region of the opposite conductivity type to the source region or the drain region is connected between the power supply or the ground side and the semiconductor substrate. 6. A silicide layer is formed over each surface of the source region and a semiconductor region of the opposite conductivity type to the source region, and a power supply or ground contact is provided in the silicide layer. The semiconductor device according to any one of claims 1 to 5. 7. The semiconductor device according to claim 1, wherein a power supply or a ground side contact is separately provided in the source region and the semiconductor region of the opposite conductivity type to the source region. . 8. The semiconductor device according to claim 1, wherein a power-supply or ground-side contact is provided commonly to the source region and the semiconductor region of the opposite conductivity type to the source region. .