JP3297301B2 - Optically driven zero-cross type triac - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a triac having a zero-cross function driven by light, and to improve the light sensitivity and dV / dt resistance of the triac.

[0002]

2. Description of the Related Art FIG. 4 is an equivalent circuit diagram of a general zero-cross type triac.

A triac can be thought of as a set of thyristors connected in anti-parallel, and each thyristor can be thought of as a combination of two transistors as shown. Transistors Q ₁ and Q ₂ connected between terminals T ₁ and T ₂ constitute one thyristor, and transistors Q ₃ and Q 2
₄ constitutes the other thyristor. The collector and the transistor of the transistor Q ₁ or Q ₃ Q ₂ or Q ₄
The base is connected to the terminal T ₂ or T ₁ by resistance R _GK1 or R _GK2, respectively the gate cathode resistance.

The source of MOSFET 1 or 1-1 is connected to the base of transistor Q ₂ or Q ₄ ,
Drain of FET1 or 1-1 is connected to the collector of the transistor Q ₂ or Q _4. MOSFET1
Or 1-1 of the gate is connected to the emitter and collector of the transistor Q ₂ or Q _4.

[0005] left thyristor operating current flows to the terminal T ₂ consisting of the terminal T ₁ comprising an anode (A) and cathode (K), the right side of thyristor operating current and the cathode from the terminal T ₂ to the anode switching is performed flows to the terminal T ₁ composed.

When a steep voltage is applied between both terminals of the thyristor, the thyristor may erroneously turn on without a gate input. This is because, in the case of a P-gate thyristor, if a P-gate diffusion region is formed on the surface of an N-type substrate, a displacement current is generated due to a sudden increase in voltage at the junction between the two, which acts as a gate current, and the thyristor operates. It is because it turns on. The critical voltage change rate (dV / dt) leading to the turn-on state is called a critical off-voltage rise rate. The higher this value is, the more difficult the thyristor is to malfunction against noise. This is called dV / dt characteristics.

Conventionally, in order to improve the dV / dt characteristics, the sensitivity of the thyristor has been lowered or the resistance R _GK has been lowered. However, any of these methods greatly reduces the light sensitivity of the device. Become.

An optically driven zero-cross type triac that triggers only at a zero-cross point is used as an on / off switch for AC control in order to suppress an inrush current. This zero-crossing function is generally achieved by connecting an MO between the thyristor terminals T ₁ and T ₂ between the emitter, collector and base of the transistor Q ₂ or Q ₄ as shown in FIG.
This is realized by connecting SFET1 or 1-1. At this time, there is a method of using a punch-through diode for limiting the voltage applied to the gate (hereinafter, referred to as a punch-through diode method) as protection of the gate oxide film dielectric breakdown of the MOSFET.

FIG. 5 is a schematic sectional view of an element constituting the thyristor on the left side of the zero-cross type triac of FIG.
Although the right thyristor is not shown to simplify the drawing, the right thyristor has substantially the same structure.

This thyristor is an example of a planar type, and the entire thyristor is formed on the surface of an N-type substrate 4 and the portion other than the electrode extraction portion is covered with an oxide film 5 of, for example, SiO ₂ .

The thyristor has a P-type anode diffusion region 15, a P-gate diffusion region 6, formed on the surface of an N-type substrate 4.
An anode electrode 12-1, a cathode electrode 12-2, and a P-gate electrode 12-3 made of Al are extracted from the respective electrode extraction portions. A back surface electrode is formed on the back surface.

The MOSFET has a P-type well diffusion layer 7 formed on the surface of an N-type substrate 4, an N-type source diffusion layer 8 and a drain diffusion layer 9 diffused on the surface thereof, and a source diffusion through an oxide film 5. It is composed of a gate electrode 13 made of Al formed so as to extend over the layer 8 and the drain diffusion 9. The source electrode 1 made of Al from the respective electrode extraction portions from the source diffusion layer 8 and the drain diffusion layer 9.
2-4, the drain electrode 12-5 is taken out. The electrode 12-7 of the P-type well diffusion layer 7 is connected to the cathode electrode and has the same potential as the cathode.

The punch-through diode is formed by forming a P-type diffusion layer 10 on the surface of an N-type substrate 4. The diode electrode 12-6 made of Al is extracted from the electrode extraction portion.

A terminal A is connected to the anode electrode 12-1 and a terminal K
Represents the cathode electrode 12-2 and the source electrode 12-4,
The drain electrode 12-5 is connected to the P gate electrode 12-3, and the gate electrode 13 is connected to the diode electrode 12-6. On the surface of the oxide film 5 between the anode electrode 12-1 and the cathode electrode 12-2, a nitride film 11 for protecting the element surface is formed.

This punch-through diode has the following problems. M used conventionally in such devices
6, the source diffusion layer 8 and the drain diffusion layer 9 below the gate electrode 13 were formed parallel to the surface of the well diffusion layer 7, as shown in the schematic plan view of FIG. The on-resistance during the operation was several kΩ.

Although not shown, a resistor R _GK1 connecting the P gate diffusion region 6 and the cathode diffusion region 14 is formed on the surface of the insulating film 5 on the element surface.

[0017]

As described above, dV /
If the sensitivity of the thyristor is reduced or the resistance of the resistor R _GK is reduced in order to improve the dt characteristics, the light sensitivity of the device is greatly reduced.

In the punch-through diode method, a voltage is applied from the diode electrode 12-6 to the gate electrode 13 in FIG. 5 to protect the gate oxide film of the MOSFET from breakdown. Since the gate of the MOSFET is filled only by the reverse leakage current of the PN junction of the punch-through diode, the MOS
It takes time for the gate of the FET to charge until the MOSFET is turned on, and the response of the MOSFET is slowed, so that the noise immunity such as dV / dt is reduced.

[0019]

According to the present invention, dV
In order to improve the / dt characteristics, the on-resistance during the operation of the MOSFET is reduced to, for example, 1 kΩ or less. As a means for this, the area of the opposing portion of the source and drain diffusion layers of the MOSFET is increased.

When the punch-through diode method is used, the response of the MOSFET is improved to improve the dV / dt characteristics. As a means, a capacitor is formed in parallel with the punch-through diode.

[0021]

FIG. 1 is a schematic sectional view showing an example of an embodiment of the present invention. FIG. 6 is a schematic sectional view of an element corresponding to FIG. 5 and corresponding to the left half of the equivalent circuit diagram of the triac of the present invention in FIG. 2.

1 and 2, FIG. 4 and FIG.
The same reference numerals indicate the same parts. Although this embodiment differs from the conventional example of FIG. 5 in the sectional view, the arrangement of the source diffusion layer 8 and the drain diffusion layer 9 on the surface of the well diffusion layer 7 constituting the MOSFET is shown in FIG. As shown, for example, a comb-shaped diffusion layer is formed on the surface of the well diffusion layer 7 so as to mesh with each other, and the channel width is larger than that of the conventional example of FIG. In addition to the comb shape, for example, a double spiral shape can be used to increase the channel width. That is, the channel width is increased by forming the source diffusion layer 8 and the drain diffusion layer 9 so as to sandwich the other side therebetween.

By increasing the channel width in this manner, the resistance when the MOSFET is turned on can be reduced to 1 kΩ or less.

According to this apparatus, d of 5 kV / μs or more
When V / dt is input, the MOSFET is turned on before the thyristor is turned on, and the displacement current generated by dV / dt is short-circuited between the gate and the cathode with a low resistance of 1 kΩ or less, and the post-operation is performed. Can be prevented.

Next, the difference between the embodiment of FIG. 1 and the conventional example of FIG. 5 is that the oxide film 5 on the surface of the N-type substrate 4 is partially removed, and that portion is used as a protective film on the element surface. The nitride film 11-1 is formed and patterned, and a capacitor electrode 12-8 made of Al is deposited and patterned on the nitride film 11-1, and is connected to the gate electrode 13 and the electrode 12-6 of the punch-through diode.

In the prototype chip, the area of the nitride film was 0.015 mm ² , the film thickness was 1 μm, and the capacity was about 10 pS. Thus, as shown in the equivalent circuit diagram of FIG. 2, the capacitor 2 (2-1) is inserted in parallel with the punch-through diode 3 (3-1).

Zener diode ZD1 connected between the gate and drain of MOSFET 1 shown in FIG.
Is formed between the P-type diffusion layer 10 and the N-type substrate 4 in FIG. The Zener diode ZD- shown in the right half of FIG.
The same applies to 1.

In a zero-cross type triac of the punch-through diode type, the delay of the MOSFET is reduced from 1 to 5 ms to 100 to 500 ns by adding a capacitor 3 of 10 pF or more in parallel with the punch-through diode 2 as shown in FIG. , MOSFET is dV / d
It was possible to operate at high speed with respect to t input, and to prevent malfunction.

Although the response of the MOSFET can be improved by reducing the MOS gate capacitance and increasing the area of the punch-through diode, the former makes it difficult to control the _Vth of the MOSFET and makes it difficult to obtain a sufficient response. . In addition, the latter is not preferable because it increases the chip area.

When a capacitor is added, a nitride film is used to form the capacitor, and since the dielectric constant is higher than that of an oxide film, the desired 10 pF
Can be achieved. Since the nitride film is used as a surface protective film of the device, there is no need to add a new process.

[0031]

As described above, according to the present invention, a high light sensitivity (for example, I _FT = 5 mA) and a high dV / dt resistance (5
(kV / μs or more) can be realized without increasing the chip size or adding new processes.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of one embodiment of the present invention.

FIG. 3 is a schematic plan view of a MOSFET according to an embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram of a conventional optically driven zero-cross type triac.

FIG. 5 is a schematic sectional view of a conventional optically driven zero-cross type triac.

FIG. 6 shows a conventional triac MOSFET for zero crossing.
It is a schematic plan view of T.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 MOSFET 2 capacitor 3 punch-through diode 4 N-type substrate 5 oxide film 6 P-gate diffusion region 7 well diffusion layer 8 source diffusion layer 9 drain diffusion layer 10 P-type diffusion layer 11, 11-1 nitride film 12-1 to 12-12 -8 electrode 13 gate electrode 14 cathode diffusion region 15 anode diffusion region

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/74 H01L 29/747

Claims (5)

(57) [Claims] 1. A light-driven zero crossing type triac using MOSFET, the source diffusion layer and drain diffusion layers of M OSFET is during MOSFET operation by enlarging the channel width sandwiched mating with each other on
Means for reducing resistance and improving dV / dt characteristics;
MOSFET charging when OSFET input is off
To prevent delay of MOSFET response due to
An optically driven zero-cross type triac having means for improving the performance . 2. The optically driven zero-cross type triac according to claim 1, wherein the source diffusion layer and the drain diffusion layer of the MOSFET are each formed in a comb shape and arranged so as to be interposed therebetween. 3. An optically driven zero-crossing type triac using a MOSFET, comprising a punch-through diode for protecting a gate oxide film of the MOSFET from being damaged.
An optically driven zero-cross type triac characterized in that a capacitor is formed in parallel with a punch-through diode in order to prevent a response delay of the MOSFET due to charging of the MOSFET when the input of the SFET is off and to improve a dV / dt resistance. 4. The optically driven zero-cross type triac according to claim 3, wherein a nitride film is used as a dielectric of the capacitor. 5. An optically driven zero-cross type triac using a MOSFET, means for reducing on-resistance during operation of the MOSFET and improving dV / dt characteristics;
4. A device according to claim 3, further comprising means for preventing a delay in response of the MOSFET due to charging of the MOSFET when the input of the OSFET is in an off state and improving dV / dt characteristics.
Or an optically driven zero-cross type triac according to 4.