JP3298193B2 - Effect adding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for delaying an input digital signal at a predetermined timing and outputting the delayed signal, or when a waveform having a large amplitude is input at an arbitrary timing and delaying the waveform for a predetermined time. And an effect adding device.

[0002]

2. Description of the Related Art Conventionally, in an effect adding device, an effect such as a delay applied to an input sound is generally changed according to a change in a tempo such as an automatic accompaniment. When musical sound waveform data having a certain amplitude or more is input from an electronic musical instrument or the like, the musical sound waveform data is
It is also known that data is written in an AM (Random Access Memory) or the like, read from the RAM after the writing is completed, and output at a timing different from the input timing, for example, at fixed time intervals.

[0003] However, when the effect such as a delay is simply changed in accordance with a change in tempo such as the above-mentioned automatic accompaniment, if the changed tempo is constant thereafter, the delay time once changed in accordance with the change in tempo is also constant thereafter. For this reason, the delay sound of a musical tone input at the same timing as the automatic accompaniment is sounded with a delay time synchronized with the automatic accompaniment. It is sounded with a delay of the determined delay time. For this reason, the delay sound which should be added for the purpose of enhancing the performance effect without synchronizing with the automatic accompaniment actually deteriorates the performance atmosphere and adversely affects the performance as a whole.

[0004] Further, those which read out the musical tone waveform data after completion of the writing and output it at a timing different from that at the time of inputting are not real-time, so that they remain unsatisfactory in that they lack interest.

[0005] To solve these problems, there is an effect that digital input data such as musical sounds and voices input at an arbitrary timing can be delayed and output in real time at a predetermined interval or at a constant timing corresponding to the beat of an accompaniment melody. Additional devices have been proposed. In this proposal, an envelope value is used to detect a signal to be output as a delay.
Then, a signal having a signal storage address when the envelope value is equal to or more than a predetermined value as a start address and a signal having an end address using the signal storage address when the envelope value is equal to or less than a predetermined value is output with delay.

[0006]

However, in the case of storing the start address and end address of the signal and delaying the signal in real time, the signal of the start address is output immediately from the state where the output signal is 0 at the output timing. Therefore, the output signal may not rise smoothly and noise may be generated. Similarly, even near the end address where the output signal stops sounding, the output signal suddenly becomes 0, which may also cause noise. It is considered that there is a problem.

SUMMARY OF THE INVENTION In view of the above circumstances, it is an object of the present invention to provide real-time delay output of digital input data such as musical sound and voice input at an arbitrary timing at a predetermined interval or at a constant timing in accordance with the beat of an accompaniment melody. It is an object of the present invention to provide an effect adding device capable of real-time delay output in which a signal changes smoothly at the rise and fall of an output signal.

[0008]

The means of the present invention are as follows. First, according to the present invention , the address is incremented at regular intervals.
Thus, a signal storage means for storing an input signal is provided. The means is, for example, a RAM (Random Acce
ss Memory) and the like.

Next, a first aspect of the present invention is a first detecting means for detecting that the envelope value of the input signal has increased to a predetermined value, and wherein the envelope value of the input signal is calculated from the predetermined value. Second detecting means for detecting the decrease . Both means are, for example, CPU (Ce
ntral Processing Unit), registers, etc.

Furthermore, the present invention provides ene base rope values the input by the first detecting means is increased to the predetermined value
Envelope value the input decreases from the predetermined value and the first address storage unit that stores a start address of the signal storage means stored in said signal when it is detected that there, by the second detecting means it has has a second address storage means for storing an end address of the signal storage means stored in said signal when it is detected.
Both means are, for example, DSP (Digital Signal Pro)
cess o r) consisting of provided the register or the like in the.

The present invention provides a first address storage device.
A predetermined address before the start address stored in the means
Address storage for storing the start address of the memory
Having means. The means includes , for example, a register provided in the DSP.

Still further, the present invention provides the method of
It has counting means for performing counting and detecting beat timing . The means comprises, for example, a clock counter or the like.
Next, in the present invention, the above-mentioned input is made by the first detecting means.
Check that the signal envelope value has increased to the specified value.
And after the counting means detects the beat timing
From before the period in which the predetermined address is incremented, from the start-up address stored in the third address storage means of the signal storage means to the end stored in the second address storage means.
Reading means for sequentially reading the signals from an end address to a fall end address after a predetermined address . The means comprises, for example, a CPU or the like.

Finally, according to the present invention, when the read means reads from the start address stored in the third address storage means to the head address stored in the first address storage means, the rising envelope is read. In the first envelope means to be added and the reading means,
From the end address stored in the second address storage means
A second envelope means for adding a falling envelope when reading up to the rising end address . Both means consist of, for example, a DSP or the like.

[0014]

The operation of the present invention is as follows. The signal storage means stores the input signal by incrementing the address at regular intervals . The first detecting means detects that the envelope value of the input signal has increased to a predetermined value . The second detecting means detects that the envelope value of the input signal has decreased from the predetermined value . The first address storage means increases the envelope value input by the first detection means to the predetermined value.
When it is detected that the signal has been read, the head address of the signal storage means in which the signal is stored is stored. The second address storage means stores an end address of the signal storage means in which the signal is stored when the second detection means detects that the input envelope value has decreased from the predetermined value. I do. The third address storage means includes:
Start address stored in the first address storage means
Stores the start address before the specified address from
You. The counting means performs counting at the above-mentioned fixed period, and
Ming is detected. The reading means is provided by the first detecting means.
The envelope value of the input signal increases to a predetermined value.
Count is detected and the counting means
From the start-up start address stored in the third address storage means of the signal storage means from the start of the period before the predetermined address is incremented from the detection of the first address.
The above signals are sequentially read out from the input end address to the falling end address after a predetermined address . The first envelope means adds a rising envelope when the reading means reads from the start address stored in the third address storage means to the start address stored in the first address storage means. The second envelope means reads from the end address stored in the second address storage means the read end address by the read end means.
When reading until the vinegar, adding the envelope of falling.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is an overall configuration diagram of an electronic keyboard instrument incorporating an effect adding device according to an embodiment of the present invention.

In FIG. 1, a keyboard 101 is a performance operation unit, and a user can play a melody by pressing a key. The CPU 102 captures the key depression state of the keyboard 101 and generates a sound source 103 based on each key depression operation.
, And generates digital sound source data for instructing the melody sound to be generated, and outputs the generated digital sound source data to the sound source 103 together with the separately generated envelope data.

The sound source data includes a sounding channel, a sounding flag, waveform data including a waveform start address, a waveform end address, and a waveform loop address, and frequency data. The tone generation channel indicates the timing of time division processing for enabling the tone generator 103 to process a plurality of musical tones in parallel. The pronunciation flag indicates whether to sound or mute a musical tone. The waveform start address and the waveform end address indicate a start address and an end address for the sound source 103 to read waveform data from the waveform memory 104. The waveform loop address indicates a repetition address for the sound source 103 to repeatedly read waveform data in a certain address range from the waveform memory 104. This makes it possible to produce a musical tone for a long time. The frequency data indicates a step width when the sound source 103 reads the waveform data from the waveform memory 104. Thereby, the pitch of the musical tone to be generated is determined.

The tone generator 103 reads out the tone waveform data from the waveform memory 104 based on the tone generator data, adds the envelope characteristics based on the envelope data to the data, generates tone data, and outputs the tone data to the DSP 105 which performs an effect adding process. .

The DSP 105 performs a process for each cycle of each tone data input from the sound source 103. At this time, the DSP 105 receives the input musical sound data (hereinafter referred to as
The input tone data is referred to as input data, and the input tone data is temporarily written into the input data memory 115, and the written tone data (hereinafter, the input data written to the memory is referred to as tone data) is read out in a certain manner described later. The data is read out based on the interval time and output to the D / A converter 107.

The processing of digital input data in the DSP 105 is based on the above-mentioned key depression.
Is input from the analog input circuit 113 having a microphone,
The same applies to digital tone signals (or digital audio signals) that are digitally converted by the / D converter 114 and input.

As a result, two systems of input data input from the keyboard 101 and the analog input circuit 113
At 105, effect processing, for example, delay processing,
After being converted into an analog tone signal by the D / A converter 107, the signal is emitted from the speaker 109 via the amplifier 108.

FIG. 2 shows the internal registers of the DSP 105. The current write address register 301 shown in the figure stores the input data write address of the input data memory 115, and the address is incremented every cycle.

The previous envelope value register 310 stores "1" when the amplitude of the previous input data is equal to or larger than a predetermined value, and stores "0" when the amplitude is smaller than the predetermined value. The current envelope value register 302 stores “1” when the amplitude of the current input data is equal to or larger than a predetermined value, and stores “0” when the amplitude of the input data is smaller than the predetermined value.

Next read start address register 303
When the value of the previous envelope value register 310 is “0” and the value of the current envelope value register 302 is “1”, that is, when the tone waveform rises, the input data write address of the current write address register 301 is stored. I do.

Next read end address register 304
When the value of the previous envelope value register 310 is “1” and the value of the current envelope value register 302 is “0”, that is, when the waveform of the input data falls,
The address immediately before the input data write address of the current write address register 301 is stored.

The read interval register 311 stores read interval time data set in advance. The read interval counter 305 is a subtraction counter, and measures the elapse of the read interval time set in the read interval register 311.

The current read address register 306 stores an address transferred from the next read start address register 303, and the address is incremented each time data is read.

The read end address register 307 stores the address transferred from the next read end address register 304. The input FLAG register 308 is a register that stores a flag, and stores “1” when there is data to be read at the data read timing, and stores “0” when there is no data to be read or when data read is started. Remember.

The FLAG register 309 during reading is also a flag register, and the current reading address register 30
"1" is stored while data is read from the address stored in No. 6 to the address stored in the read end address register 307; otherwise, "0" is stored.

The rising FLAG register 312 stores "1" for a period of several samples before the reading interval counter 305 becomes "0", that is, before the timing for reading the tone data. During the period in which the content stored in the rising FLAG register 312, that is, the flag is “1”, in the DSP 105, the tone data is enveloped so that the output gradually rises.

The falling FLAG register 313 stores "1" for a period of several samples after the address of the current read address register 306 matches the address of the read end address register 307. While this flag is “1”, the tone data is enveloped in the DSP 105 so that the output gradually falls.

The falling counter 314 is a counter for counting the number of samples until the output completely becomes "0" (silence) when the flag of the falling FLAG register 313 is "1".

The LFO counter 312 counts the period for changing the read interval set in the read interval register 311. The value of the LFO counter 312 is decremented each time the DSP performs one process.

The read interval MAX value register 313 '
The maximum value of the read interval is stored. Read interval register 3
11 reaches the value of the read interval MAX value register 313 ', the LFO increase / decrease FLAG register 31 described later.
5 'is changed, and thereafter, the read interval register 311
Are sequentially reduced.

The read interval MIN value register 314 '
The minimum value of the read interval is stored. Read interval register 3
When the value of 11 reaches the value of the read interval MIN value register 314 ', the value of the LFO increase / decrease FLAG register 315' is changed, and thereafter, the value of the read interval register 311 is sequentially increased.

The LFO increase / decrease FLAG 315 'stores "1" when increasing the value of the read interval register 311 and stores "0" when decreasing the value of the read interval register 311.

The LFO set value register 316 'is a register for setting a cycle for changing the value of the read interval register 311. When the value of the LFO counter 312' becomes "0", the LFO set value register 316 'is set. The value of 316 'is reset to the LFO counter 312'.

Next, FIG. 3 schematically shows the outline of the operation performed by the DSP 105 using each of the above-described internal registers.
In this example, eight processing cycles are set as the fixed interval time. The start of the measurement of the fixed interval time is indicated by time T0, and the times at which the fixed interval time elapses are indicated by T1, T2,.

9A shows the input data (tone data) written in the input data memory 115, FIG. 9B shows the write address thereof, and FIG. 9C shows the current envelope value register 30.
2 (“1” or “0”), (d) is ON / OFF (“1” / “0”) of the FLAG register 309 during reading, and (e) is read output data (tone data). And the rising and falling envelopes added to the tone data, (f) is the read address thereof, and (g) is the on / off of the rising FLAG register 312 ("1" /
“(0)”, (h) is the on / off (“1” / “0”) of the falling FLAG register 313, (i) is the count value of the falling counter 314, and (j) is the read interval counter 305.
And (k) indicate ON / OFF of the input FLAG 309.

Referring to FIG.
The measurement of the 0 processing cycle time starts at time T0, and the digital input data input to the DSP 105 is sequentially written from the address “0” of the input data memory 115 for each processing cycle (see FIG. 3A). ).

In the fourth processing cycle, the write address, which is the value of the current write address register 301, becomes "3", and the value of the read interval counter 305, which subtracts and measures 10 processing cycles, which is a fixed time, becomes "7". ". At this time, the envelope value of the input data is less than a certain value, that is, “0” (see FIGS. 3A and 3J).

Then, in the next processing cycle, when the waveform data is inputted to the address "4" with an amplitude value exceeding a certain value like the input data 31 (see FIG. 7A), the rising of the waveform is detected. The value of the current envelope value register 302 is set to "1" in synchronization with the detected rising edge of the waveform (see FIG. 3C), and the input FLAG 308 is set to "1" (see FIG. 4C). (See (k)), and the address “4” at the rising edge of the waveform is set in the next read start address register 303 as the read start address.

Subsequently, input data having an envelope value equal to or greater than a certain value is sequentially written to addresses "5" and "6",
The value of the current envelope value register 302 is "1" (see FIGS. 3A, 3B, and 3C).

In the next processing cycle, when the envelope value of the input data at address "7" becomes less than a predetermined value and a falling edge of the waveform is detected (see FIG. 3B), the detected waveform rising edge is detected. The value of the current envelope value register 302 is set to “0” in synchronization with the fall (see FIG.
(See (c)), the address “6” immediately before the falling edge of the waveform is set in the next read end address register 304 as the read end address.

Eventually, the time T1 of the lapse of the fixed interval time T2
When the time before the processing cycle is reached (the value of the read interval counter 305 is “2”), the input FLAG 308 is “1” and the reading FLAG register 309 is set.
Is set to “1” and the input FLAG 308 is set to “0”
(See FIGS. 3 (d) and 3 (k)). At the same time, an address obtained by subtracting two addresses from the address “4” of the next read head address register 303, that is, the address “2” two immediately before is set in the current read address register 306 as the actual read head address (see FIG. Figure
(See (f)), and the next read end address register 3
04 is transferred to the read end address register 307. Then, from the read start address to the read end address, the tone waveform data 31 written in the input data memory 115 is read as output data.

A rising envelope is added to the read musical tone waveform data because the rising flag is "1" for a period of two processes from the start of reading. Further, since the falling flag is "1" for a period of two processes from the reading end address, the musical tone waveform data of two addresses is further read, and a falling envelope is added (FIG. 3A, (See (b), (e) and (f)).

In the case of the input data 32 shown in FIG.
The difference is that the waveform rising address is "F", therefore, the read address is "D", the waveform falling address is "11", and thus the end address is "12", and the other processing is the same.

In the above, within a certain period of time,
For example, if there is no rising of the input data between times T2 and T3, the tone data is not read at the next read timing. Next, the processing operation of the DSP 105 that performs the above-described processing will be further described with reference to the flowcharts of FIGS.

In this processing, when the power is turned on, predetermined read interval time data (“9” in this example) is set in the read interval register 311, and the read interval time data “9” is read. After being transferred to the interval counter 305 and set, "0" is set in the other registers, and each register is initialized. And CPU1
On the basis of the control signal from 02, the processing described below is performed at a constant cycle.

First, the DSP 105 takes in tone data output from the sound source 103 as input data (step 401). Subsequently, the current write address register 30
1 is incremented by "1" (step 402). Thereby, the acquired input data (hereinafter referred to as the sound source 10
3 or the data directly taken from the analog input circuit 113 is referred to as input data, and the data after the data is written to the input data memory 115 is referred to as musical sound data).

Next, the fetched input data is written as musical tone data to the address set in the current write address register 301 of the input data memory 115 (step 403). Thus, as shown in FIGS. 3A and 3B, the input tone waveform data is written in the input data memory 115 in the order of addresses.

Following the above, the read interval counter 305
Is decremented by "1" (step 404), and the read interval counter 305 is referred to to determine whether the value has become "2" (step 405). As a result, it is determined whether or not the time is two processes before the elapsed time (time T1, T2,... In the example of FIG. 3) at a predetermined constant interval.

In the processing so far, the input data is sequentially written into the input data memory 115 as musical sound data (steps 401 to 403), while the read start time of the written musical sound data is counted (step 404). It is determined whether or not the read start time has come (step 405).

If the read interval counter 305 is not "2", it is further determined whether the read interval counter 305 is "0" (step 41).
1). Thereby, it is determined whether the processing timing is immediately after the power is turned on or immediately after the elapse of the certain interval time, or during the certain interval period.

In the above determination, if the read interval counter 305 is "0", it is determined that the processing timing is immediately after the power is turned on or immediately after the elapse of a predetermined interval time. The value of 311 is set (step 412). As a result, FIG.
In the example shown in (1), the read interval time data "9" is set in the read interval counter 305, and the fixed interval time indicated by the count values "8" to "0" is measured at each processing timing from the next time.

Subsequently, the rising FLAG register 312
Is set to "0" (step 413). As a result, when the reading of the tone data, which will be described later, has been started, the addition of the rising envelope by the DSP 105 is stopped, and the tone generated by the sound source 103 is subjected to normal envelope processing.

Following the above, the address of the current read address register 306 is incremented by "1" (step 414). This process is a process for sequentially reading out the tone data in the subsequent step 416 when the reading of the tone data has been started.

Next, it is determined whether or not the reading FLAG register 309 is "1" (step 415). In this discrimination, for example, FLAG being read out immediately after the start
If the register 309 is "0", it is determined that the tone data is not being read, and in this case, the tone data is set to "0" (silence) (step 417). Then, it is confirmed that the rising FLAG register 312 is "0" (step 418), and the falling FLA is further checked.
After confirming that the G register 313 is also "0" (step 420), the tone data set to "0" (silence) is output to the D / A converter 107 (step 42).
3). As a result, unless the tone data is being read out,
Musical notes are not pronounced.

Next, the envelope value of the input data fetched in step 401 is extracted, and if the extracted envelope value is equal to or larger than a predetermined value, the current envelope value register 302 is set to "1". ,
If it is less than the certain value, it is set to "0" (step 42).
4).

Subsequently, the previous envelope value register 31
Whether the value of “0” is “0” and the value of the current envelope value register 302 set in step 424 is “1”;
That is, it is determined whether or not the input data has risen (step 425) (see address "4" or address "F" in FIG. 3A).

If it is determined that the input data has risen, first, the current write address register 301
Is set in the next read start address register 303 (step 426). Thereby, for example, "4", which is the rising address of the input data 31 shown in FIG. 3A, is set as the read head address for reading at the next timing.

Next, the next read end address register 30
4 is set to "-1" (also step 426).
This indicates that the read end address of the musical tone data to be read at the next timing is undecided.

Subsequently, the input FLAG register 308 is set to "1" (step 427). This allows
The presence of musical tone data to be read out based on the read signal from the CPU 102 is indicated for the subsequent processing.

Then, the value of the current envelope value register 302 is set in the previous envelope value register 310 (step 432). Accordingly, the envelope value of the input data can be determined again in the next process by setting the envelope value of the current input data as the previous envelope value and the envelope value of the next input data as the current envelope value. .

If the input data has not risen in step 425, it is determined whether the value of the previous envelope value register 310 is "1" and the value of the current envelope value register 302 is "0". That is, it is determined whether or not the input data has fallen (step 428). If it is determined that the input data has not yet fallen, the process immediately proceeds to step 432. Thus, for example, the input data 31 of FIG. 3A is sequentially compared with the envelope value of the preceding data and the envelope value of the succeeding data from address “4” to address “7”.

If it is determined in step 428 that the input data has fallen (see the waveform data at address "7" in FIG. 3A), the address of the current write address register 301 is subtracted by "1". To calculate the previous write address, and set the calculated previous write address in the next read end address register 304 (step 429). Thus, for example, the address “6” which is the falling address of the input data 31 shown in FIG.
Is set as the read end address of the tone data to be read at the next timing.

Subsequently, steps 430 and 431
As described above, the tone data is sequentially written to the input data memory 115, and the rising and falling addresses of the waveform data are stored in the next read start address register 303 and the next read end address register 304, as described above. After each setting, in step 405 described above, it is determined that the value of the read interval counter 305 has become "2".
It is determined whether or not the value of the G register 308 is "1" (step 406), and since the value is "1", the value of the G register 308 is changed from the previous beat (for example, time T0 shown in FIG. 3) to the current beat (for example, It is confirmed that there is input data before the time T2 shown in FIG. 3 (see the waveform data 31 in FIG. 3A), and the address of the next read head address register 303 is subtracted by "2". This is set in the current read address register 306, and the address of the next read end address register 304 is set in the read end address register 3.
07 (step 407). Thus, for example, the write addresses “2” and “6” shown in FIG.
Are set as a read start address and a read end address, respectively. Subsequently, the FLAG register 309 during reading is set to "1" (step 40).
8). Thus, it is set that the tone data is being read.

Next, the rising FLAG register 312 is set to "1" (step 4090). Thus, it is set that the tone data is rising. Further, the input FLAG register 308 is set to "0" (step 410). As a result, preparation for detecting the next input data is made.

In the above step 406, the input FL
If the AG register 308 is “0”, the process immediately proceeds to step 410. After confirming that the reading FLAG register 309 is "1" (step 415), the tone data is read from the address of the current reading address register 306 of the input data memory 115 (step 416).

Thus, the current read address register 3
The tone data 31 is sequentially read from the address 06 to the address of the read end address register 307, for example, from the addresses "2" to "6" shown in FIG.

Subsequently, the rising FLAG register 312
Is determined (step 418). If the rising FLAG register 312 is "1", it is determined that the processing is in the rising processing period, and the rising envelope processing is performed (step 419). As a result, a rising envelope is added to the musical sound data so that the output gradually rises during several processing periods (two processing periods in the example shown in FIG. 3) immediately after the start of musical sound reading.

Then, the tone data is output to the D / A converter 107 (step 423). As a result, if the tone data reading rises, a tone with a rising envelope added so as to gradually rise as described above is generated.

At step 418, the rising FLAG
If the register 312 is “0”, the falling F
It is determined whether or not the LAG register 313 is "1" (step 420). If the falling FLAG register 313 is also "0", it is determined that the tone data is between the current read address and the read end address, and immediately. The process of step 423 is performed. As a result, a normal tone to which an envelope is added is generated by the sound source.

If it is determined in step 420 that the falling FLAG register 313 is "1", it is determined that a falling processing period is in progress, and falling envelope processing is performed (step 421). Then, after the value of the falling counter 314 is decremented by "1" (step 422), the processing of step 423 is performed.

Thus, falling FLAG register 3
When 13 is "1", a period during which the falling process set in the falling counter 314 is performed is counted. During this time, the tone data at the address following the address of the reading end address register 307 is read out. A falling envelope is added to the tone data so that the output gradually falls, and the tone data is generated.

The rising envelope processing and the falling envelope processing described above are different from the normal envelope processing in the sound source, in that, for example, a multiplier from 0.0 to 1.0 is simply added to the tone data read in step 416. It is processing like multiplying.

Here, the description returns to step 430 and subsequent steps following step 429 described above. In step 430, referring to the value of the read end address register 307,
If the value is "-1", the falling of the musical tone data which has been set in the reading start state in step 408 and is in the reading start state has not been detected yet, is set in step 426, and the reading ends in step 407. It is determined that the read end address transferred to the address register 307 is undecided, that is, the input data that has just fallen is the tone data that is currently being read out. Is subtracted by "1" to calculate the previous write address which is the falling address of the input data which is the tone data currently being read, and sets the calculated falling address in the read end address register 307 ( Step 431). As a result, the read end address of the tone data read during the input is set.

If the determination in step 430 is not "-1", it is the read end address set at the current read timing, and it is determined that it is not necessary to specify a new read end address until the next read timing. Then, the process immediately proceeds to step 432 described above.

Subsequent to step 432, it is next determined whether or not the address of the current read address register 306 matches the address of the read end address register 307 (step 433). As a result, if the tone data is being read, it is determined whether or not the address of the current read address register 306, which is sequentially incremented by "1" in the above-described step 414, has reached the read end address.

If the two addresses do not match, that is, if there is music data to be continuously read out (see addresses "2" to "6" in FIG. 3A), the falling FLAG register 313 sets "1". It is determined whether or not it is "1" (step 436).
It is determined that the tone data being read is not falling, and in this case, it is next determined whether or not the LFO counter 312 'is "0" (step 527).
If not, the value is decremented by "1" (step 528). As a result, a change period of the interval time of the reading interval at which the elapsed time is determined in step 405 or step 411 described above is measured.

If it is determined in step 433 that the address of the current read address register 306 has become the read end address, the falling FLAG register 313 is set to "1" (step 434). This allows
It is set that the tone data falls.

Subsequently, "2" is set in the falling counter 314.
Is set (step 435). Thereby, the fall processing time for two processing timings is set. Then, in the determination of step 436, since the falling FLAG register 313 is set to "1", it is determined that the falling process is to be performed. In this case, the falling counter 314 is further set to "0". Is determined (step 437). If it is not "0", the flow shifts to step 537. As a result, at step 414 of the next next two processing timings, the musical tone data of two more addresses are read from the read end address, and the falling envelope processing is performed.

After the falling envelope processing at the two processing timings, it is confirmed in step 437 that the falling counter 314 has become "0", and "0" is set in the falling FLAG register 313. (Step 438). Thereby, the end of the fall processing is set.

Subsequently, during reading, the FLAG register 309 is read.
Is set to "0" (step 439). Thereby, the end of reading is set. Step 527 above
When the LFO counter 312 'is "0", L
The set value is set to the FO counter 312 '(step 529). As a result, a set value set in advance by input or the like, that is, a change cycle of the interval time is set again in the LFO counter 312 '.

Then, it is determined whether or not the LFO increase / decrease FLAG register 315 'is "1" (step 53).
0), if it is "1", the value of the read interval register 311 is incremented by "1" (step 531). As a result, the LFO increase / decrease FLAG register 315 'becomes "1".
In the case of, the read interval is extended for each change cycle measured by the LFO counter 312 '.

Then, it is determined whether or not the extended read interval matches or exceeds the read interval set in the read interval MAX value register 313 '(step 5).
32) If the value does not match or exceed, the process ends immediately. If the value matches or exceeds, the LF
"0" is set in the O increase / decrease FLAG register 315 '(step 533). As a result, the read interval sequentially extended in each change cycle becomes the read interval M
If the read interval set in the AX value register 313 'coincides with or exceeds the read interval, the read interval is sequentially reduced from the next processing timing for each change cycle.

That is, in the above step 530, LF
If the O increase / decrease FLAG register 315 'is "0", the value of the read interval register 311 is decremented by "1" (step 534). As a result, the LFO increase / decrease F
When the LAG register 315 'is "0", the LFO
The read interval is shortened for each change period counted by the counter 312 '.

Then, it is determined whether or not the shortened read interval matches or is shorter than the read interval set in the read interval MIN value register 314 '(step 5).
35) If not coincident or short, the process is immediately terminated, while if coincident or short, in this case, "1" is set to the LFO increase / decrease FLAG register 315 '(step 536). As a result, the read interval that is sequentially shortened for each change cycle is changed to the read interval
When the read interval set in the value register 314 'coincides with or becomes shorter than the read interval, the read interval is sequentially extended again at every change cycle from the next processing timing.

As described above, in the present embodiment, not only an effect is applied to an input digital signal such as tone data or audio data, but also the effected input digital signal is transmitted to a predetermined signal regardless of the input timing. The delay can be output at a certain interval of time, or an automatically applied digital data such as an automatic accompaniment melody can be applied as it is or by applying an effect, and an effect can be applied at each timing of the automatically generated beat. Input digital signal can be output as a delay.

Also, when the tone data in the input data memory is output, an envelope is applied inside the DSP so that the output changes smoothly before and after the tone data, so that a more beautiful and more effective delay is provided. The effect can be obtained.

Further, the LFO or the like expands or contracts the above-mentioned fixed time interval between the maximum time and the minimum time which are arbitrarily set in advance, thereby providing a delay sound effect. Is slightly shifted from the regular timing, so that a more effective sound effect can be added without becoming monotonous.

In the above embodiment, when changing the readout interval, 1 is simply added or subtracted (triangular wave), but the change may be made by another waveform such as a sine wave. By adjusting the period of a sine wave or the like to the generally known "1 / f fluctuation", a sound effect that is more comfortable for humans can be obtained.

[0093]

As described above, according to the present invention,
Input signals such as musical sounds and voices input at arbitrary timing can be output in real time at a predetermined interval or at a constant timing in accordance with the beat of an accompaniment melody. The output is output after being delayed in synchronization with automatic accompaniment and the like, so that the performance effect can be sufficiently enhanced without impairing the atmosphere of the performance. Also, when the musical sound data is output from the memory, an envelope is applied before and after the musical sound data, so that the output changes smoothly, and a beautiful and more effective delay effect without distortion can be obtained. Further, since the above-mentioned constant timing is changed between a certain maximum time and a certain minimum time at every certain change period, the output of the delay sound effect slightly deviates from the regular timing, and therefore does not become monotonous. Sound effects that are even more effective.

Since these effects are added in real time, it is possible to enjoy a very interesting performance.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of an electronic keyboard instrument incorporating an effect adding device according to a first embodiment.

FIG. 2 is a configuration diagram of a DSP internal register.

FIG. 3 is a diagram illustrating a schematic operation of a DSP.

FIG. 4 is a flowchart (part 1) for explaining the operation of the DSP;

FIG. 5 is a flowchart (part 2) for explaining the operation of the DSP;

FIG. 6 is a flowchart (part 3) for explaining the operation of the DSP;

[Explanation of symbols]

 101 Keyboard 102 CPU 103 Sound Source 104 Waveform Memory 105 DSP 106 Mixer Circuit 107 D / A Converter 108 Amplifier 109 Speaker 113 Analog Input Circuit 114 A / D Converter 115 Input Data Memory 301 Current Write Address Register 310 Previous Envelope Value Register 302 Current envelope value register 303 Next read start address register 304 Next read end address register 311 Read interval register 305 Read interval counter 306 Current read address register 307 Read end address register 308 Input FLAG register 309 Reading FLAG register 312 Rising FLAG register 313 Standing Falling FLAG register 314 Falling counter 312 'LFO counter 313' Read Interval MAX value register 314 'Read interval MIN value register 315' LFO increase / decrease FLAG register 316 'LFO setting value register

Claims (1)

(57) [Claims] An address is incremented at regular intervals.
More, a signal storage means for storing a signal input, the envelope value of the signal to be the input is increased to a predetermined value
First detecting means for detecting that have envelope value of the signal to be the input from the predetermined value
A second detecting means for detecting that the signal is decreasing, and the signal is stored when the input envelope value is detected to be increasing to the predetermined value by the first detecting means. First address storage means for storing a head address of the signal storage means; and storage of the signal when the second detection means detects that the input envelope value has decreased from the predetermined value. A second address storage means for storing an end address of the signal storage means, and a third start-up address for storing a start-up address a predetermined address before the head address stored in the first address storage means . Address storage means, counting means for performing counting at the constant period, and detecting a beat timing, and embedding of the signal inputted by the first detecting means.
After detecting that the rope value is increasing to the specified value
When the counting means detects the beat timing, the predetermined
From the start-up start address stored in the third address storage means of the signal storage means before the end address stored in the second address storage means, before the period of stepping up the address.
Reading means for sequentially reading the signals from a dress to a falling end address after a predetermined address; and in the reading means, the starting address stored in the third address storing means is stored in the first address storing means. When reading up to the stored top address,
First envelope means for adding a rising envelope, and the reading means for reading from the end address stored in the second address storage means to the rising end address , And a second envelope means for adding an effect.